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体验新版 GitCode,发现更多精彩内容 >>
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afe3848b
编写于
8月 23, 2008
作者:
W
Wolfgang Denk
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差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-ppc4xx
上级
0bb86d82
5d4b3d2b
变更
6
隐藏空白更改
内联
并排
Showing
6 changed file
with
120 addition
and
73 deletion
+120
-73
cpu/ppc4xx/44x_spd_ddr2.c
cpu/ppc4xx/44x_spd_ddr2.c
+13
-4
cpu/ppc4xx/4xx_pcie.c
cpu/ppc4xx/4xx_pcie.c
+5
-5
cpu/ppc4xx/cpu_init.c
cpu/ppc4xx/cpu_init.c
+13
-0
include/asm-ppc/ppc4xx-sdram.h
include/asm-ppc/ppc4xx-sdram.h
+33
-17
include/ppc440.h
include/ppc440.h
+0
-47
include/ppc4xx.h
include/ppc4xx.h
+56
-0
未找到文件。
cpu/ppc4xx/44x_spd_ddr2.c
浏览文件 @
afe3848b
...
...
@@ -2249,17 +2249,26 @@ static void program_memory_queue(unsigned long *dimm_populated,
}
}
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
/*
* Enable high bandwidth access on 460EX/GT.
* This should/could probably be done on other
* PPC's too, like 440SPe.
* Enable high bandwidth access
* This is currently not used, but with this setup
* it is possible to use it later on in e.g. the Linux
* EMAC driver for performance gain.
*/
mtdcr
(
SDRAM_PLBADDULL
,
0x00000000
);
/* MQ0_BAUL */
mtdcr
(
SDRAM_PLBADDUHB
,
0x00000008
);
/* MQ0_BAUH */
/*
* Set optimal value for Memory Queue HB/LL Configuration registers
*/
mtdcr
(
SDRAM_CONF1HB
,
mfdcr
(
SDRAM_CONF1HB
)
|
SDRAM_CONF1HB_AAFR
|
SDRAM_CONF1HB_RPEN
|
SDRAM_CONF1HB_RFTE
);
mtdcr
(
SDRAM_CONF1LL
,
mfdcr
(
SDRAM_CONF1LL
)
|
SDRAM_CONF1LL_AAFR
|
SDRAM_CONF1LL_RPEN
|
SDRAM_CONF1LL_RFTE
);
mtdcr
(
SDRAM_CONFPATHB
,
mfdcr
(
SDRAM_CONFPATHB
)
|
SDRAM_CONFPATHB_TPEN
);
#endif
}
...
...
cpu/ppc4xx/4xx_pcie.c
浏览文件 @
afe3848b
...
...
@@ -638,7 +638,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
switch
(
port
)
{
case
0
:
SDR_WRITE
(
PESDR0_L0CDRCTL
,
0x00003230
);
SDR_WRITE
(
PESDR0_L0DRV
,
0x0000013
6
);
SDR_WRITE
(
PESDR0_L0DRV
,
0x0000013
0
);
SDR_WRITE
(
PESDR0_L0CLK
,
0x00000006
);
SDR_WRITE
(
PESDR0_PHY_CTL_RST
,
0x10000000
);
...
...
@@ -649,10 +649,10 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
SDR_WRITE
(
PESDR1_L1CDRCTL
,
0x00003230
);
SDR_WRITE
(
PESDR1_L2CDRCTL
,
0x00003230
);
SDR_WRITE
(
PESDR1_L3CDRCTL
,
0x00003230
);
SDR_WRITE
(
PESDR1_L0DRV
,
0x0000013
6
);
SDR_WRITE
(
PESDR1_L1DRV
,
0x0000013
6
);
SDR_WRITE
(
PESDR1_L2DRV
,
0x0000013
6
);
SDR_WRITE
(
PESDR1_L3DRV
,
0x0000013
6
);
SDR_WRITE
(
PESDR1_L0DRV
,
0x0000013
0
);
SDR_WRITE
(
PESDR1_L1DRV
,
0x0000013
0
);
SDR_WRITE
(
PESDR1_L2DRV
,
0x0000013
0
);
SDR_WRITE
(
PESDR1_L3DRV
,
0x0000013
0
);
SDR_WRITE
(
PESDR1_L0CLK
,
0x00000006
);
SDR_WRITE
(
PESDR1_L1CLK
,
0x00000006
);
SDR_WRITE
(
PESDR1_L2CLK
,
0x00000006
);
...
...
cpu/ppc4xx/cpu_init.c
浏览文件 @
afe3848b
...
...
@@ -301,6 +301,19 @@ cpu_init_f (void)
val
|=
0x400
;
mtsdr
(
SDR0_USB2HOST_CFG
,
val
);
#endif
/* CONFIG_460EX */
#if defined(CONFIG_405EX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
/*
* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
*/
mtdcr
(
plb0_acr
,
(
mfdcr
(
plb0_acr
)
&
~
plb0_acr_rdp_mask
)
|
plb0_acr_rdp_4deep
);
mtdcr
(
plb1_acr
,
(
mfdcr
(
plb1_acr
)
&
~
plb1_acr_rdp_mask
)
|
plb1_acr_rdp_4deep
);
#endif
/* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
}
/*
...
...
include/asm-ppc/ppc4xx-sdram.h
浏览文件 @
afe3848b
...
...
@@ -259,23 +259,39 @@
/*
* Memory queue defines
*/
#define SDRAMQ_DCR_BASE 0x040
#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0)
/* rank 0 base address & size */
#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1)
/* rank 1 base address & size */
#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2)
/* rank 2 base address & size */
#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3)
/* rank 3 base address & size */
#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5)
/* configuration 1 HB */
#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7)
/* error status HB */
#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8)
/* error address upper 32 HB */
#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9)
/* error address lower 32 HB */
#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA)
/* PLB base address upper 32 LL */
#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB)
/* configuration 1 LL */
#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC)
/* error status LL */
#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD)
/* error address upper 32 LL */
#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE)
/* error address lower 32 LL */
#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF)
/* configuration between paths */
#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10)
/* PLB base address upper 32 LL */
#define SDRAMQ_DCR_BASE 0x040
#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0)
/* rank 0 base address & size */
#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1)
/* rank 1 base address & size */
#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2)
/* rank 2 base address & size */
#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3)
/* rank 3 base address & size */
#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5)
/* configuration 1 HB */
#define SDRAM_CONF1HB_AAFR 0x80000000
/* Address Ack on First Request - Bit 0 */
#define SDRAM_CONF1HB_PRPD 0x00080000
/* PLB Read pipeline Disable - Bit 12 */
#define SDRAM_CONF1HB_PWPD 0x00040000
/* PLB Write pipeline Disable - Bit 13 */
#define SDRAM_CONF1HB_PRW 0x00020000
/* PLB Read Wait - Bit 14 */
#define SDRAM_CONF1HB_RPEN 0x00000800
/* Read Passing Enable - Bit 20 */
#define SDRAM_CONF1HB_RFTE 0x00000400
/* Read Flow Through Enable - Bit 21 */
#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7)
/* error status HB */
#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8)
/* error address upper 32 HB */
#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9)
/* error address lower 32 HB */
#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA)
/* PLB base address upper 32 LL */
#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB)
/* configuration 1 LL */
#define SDRAM_CONF1LL_AAFR 0x80000000
/* Address Ack on First Request - Bit 0 */
#define SDRAM_CONF1LL_PRPD 0x00080000
/* PLB Read pipeline Disable - Bit 12 */
#define SDRAM_CONF1LL_PWPD 0x00040000
/* PLB Write pipeline Disable - Bit 13 */
#define SDRAM_CONF1LL_PRW 0x00020000
/* PLB Read Wait - Bit 14 */
#define SDRAM_CONF1LL_RPEN 0x00000800
/* Read Passing Enable - Bit 20 */
#define SDRAM_CONF1LL_RFTE 0x00000400
/* Read Flow Through Enable - Bit 21 */
#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC)
/* error status LL */
#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD)
/* error address upper 32 LL */
#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE)
/* error address lower 32 LL */
#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF)
/* configuration between paths */
#define SDRAM_CONFPATHB_TPEN 0x08000000
/* Transaction Passing Enable - Bit 4 */
#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10)
/* PLB base address upper 32 LL */
#if !defined(CONFIG_405EX)
/*
...
...
include/ppc440.h
浏览文件 @
afe3848b
...
...
@@ -341,53 +341,6 @@
#define PLB4_ACR_WRP (0x80000000 >> 7)
/* Nebula PLB4 Arbiter - PowerPC440EP */
#define PLB_ARBITER_BASE 0x80
#define plb0_revid (PLB_ARBITER_BASE+ 0x00)
#define plb0_acr (PLB_ARBITER_BASE+ 0x01)
#define plb0_acr_ppm_mask 0xF0000000
#define plb0_acr_ppm_fixed 0x00000000
#define plb0_acr_ppm_fair 0xD0000000
#define plb0_acr_hbu_mask 0x08000000
#define plb0_acr_hbu_disabled 0x00000000
#define plb0_acr_hbu_enabled 0x08000000
#define plb0_acr_rdp_mask 0x06000000
#define plb0_acr_rdp_disabled 0x00000000
#define plb0_acr_rdp_2deep 0x02000000
#define plb0_acr_rdp_3deep 0x04000000
#define plb0_acr_rdp_4deep 0x06000000
#define plb0_acr_wrp_mask 0x01000000
#define plb0_acr_wrp_disabled 0x00000000
#define plb0_acr_wrp_2deep 0x01000000
#define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
#define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
#define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
#define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
#define plb1_acr (PLB_ARBITER_BASE+ 0x09)
#define plb1_acr_ppm_mask 0xF0000000
#define plb1_acr_ppm_fixed 0x00000000
#define plb1_acr_ppm_fair 0xD0000000
#define plb1_acr_hbu_mask 0x08000000
#define plb1_acr_hbu_disabled 0x00000000
#define plb1_acr_hbu_enabled 0x08000000
#define plb1_acr_rdp_mask 0x06000000
#define plb1_acr_rdp_disabled 0x00000000
#define plb1_acr_rdp_2deep 0x02000000
#define plb1_acr_rdp_3deep 0x04000000
#define plb1_acr_rdp_4deep 0x06000000
#define plb1_acr_wrp_mask 0x01000000
#define plb1_acr_wrp_disabled 0x00000000
#define plb1_acr_wrp_2deep 0x01000000
#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000
/* UART1 Mode Enable */
...
...
include/ppc4xx.h
浏览文件 @
afe3848b
...
...
@@ -46,6 +46,62 @@
#define CONFIG_SDRAM_PPC4xx_IBM_DDR2
/* IBM DDR(2) controller */
#endif
/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
#if defined(CONFIG_405EX) || \
defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
#define PLB_ARBITER_BASE 0x80
#define plb0_revid (PLB_ARBITER_BASE + 0x00)
#define plb0_acr (PLB_ARBITER_BASE + 0x01)
#define plb0_acr_ppm_mask 0xF0000000
#define plb0_acr_ppm_fixed 0x00000000
#define plb0_acr_ppm_fair 0xD0000000
#define plb0_acr_hbu_mask 0x08000000
#define plb0_acr_hbu_disabled 0x00000000
#define plb0_acr_hbu_enabled 0x08000000
#define plb0_acr_rdp_mask 0x06000000
#define plb0_acr_rdp_disabled 0x00000000
#define plb0_acr_rdp_2deep 0x02000000
#define plb0_acr_rdp_3deep 0x04000000
#define plb0_acr_rdp_4deep 0x06000000
#define plb0_acr_wrp_mask 0x01000000
#define plb0_acr_wrp_disabled 0x00000000
#define plb0_acr_wrp_2deep 0x01000000
#define plb0_besrl (PLB_ARBITER_BASE + 0x02)
#define plb0_besrh (PLB_ARBITER_BASE + 0x03)
#define plb0_bearl (PLB_ARBITER_BASE + 0x04)
#define plb0_bearh (PLB_ARBITER_BASE + 0x05)
#define plb0_ccr (PLB_ARBITER_BASE + 0x08)
#define plb1_acr (PLB_ARBITER_BASE + 0x09)
#define plb1_acr_ppm_mask 0xF0000000
#define plb1_acr_ppm_fixed 0x00000000
#define plb1_acr_ppm_fair 0xD0000000
#define plb1_acr_hbu_mask 0x08000000
#define plb1_acr_hbu_disabled 0x00000000
#define plb1_acr_hbu_enabled 0x08000000
#define plb1_acr_rdp_mask 0x06000000
#define plb1_acr_rdp_disabled 0x00000000
#define plb1_acr_rdp_2deep 0x02000000
#define plb1_acr_rdp_3deep 0x04000000
#define plb1_acr_rdp_4deep 0x06000000
#define plb1_acr_wrp_mask 0x01000000
#define plb1_acr_wrp_disabled 0x00000000
#define plb1_acr_wrp_2deep 0x01000000
#define plb1_besrl (PLB_ARBITER_BASE + 0x0A)
#define plb1_besrh (PLB_ARBITER_BASE + 0x0B)
#define plb1_bearl (PLB_ARBITER_BASE + 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE + 0x0D)
#endif
/* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
#if defined(CONFIG_440)
/*
* Enable long long (%ll ...) printf format on 440 PPC's since most of
...
...
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