pci: fix errant data types and corresponding access functions

In a couple of places, unsigned int and pci_config_*_dword were being
used when u16 and _word should be used.  Unsigned int was also being
used in a couple of places that should be pci_addr_t.
Signed-off-by: NAndrew Sharp <andywyse6@gmail.com>

drivers/pci/pci.c

@@ -118,11 +118,11 @@ PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 {
 	pci_addr_t pci_bus_addr;
-	u32 bar_response;
+	pci_addr_t bar_response;
 
 	/* read BAR address */
 	pci_read_config_dword(pdev, bar, &bar_response);
-	pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
+	pci_bus_addr = bar_response & ~0xf;
 
 	/*
 	 * Pass "0" as the length argument to pci_bus_to_virt.  The arg
@@ -385,7 +385,8 @@ int pci_hose_config_device(struct pci_controller *hose,
 			   pci_addr_t mem,
 			   unsigned long command)
 {
-	unsigned int bar_response, old_command;
+	pci_addr_t bar_response;
+	unsigned int old_command;
 	pci_addr_t bar_value;
 	pci_size_t bar_size;
 	unsigned char pin;

drivers/pci/pci_auto.c

@@ -88,15 +88,15 @@ void pciauto_setup_device(struct pci_controller *hose,
 			  struct pci_region *prefetch,
 			  struct pci_region *io)
 {
-	unsigned int bar_response;
+	pci_addr_t bar_response;
 	pci_addr_t bar_value;
 	pci_size_t bar_size;
-	unsigned int cmdstat = 0;
+	u16 cmdstat = 0;
 	struct pci_region *bar_res;
 	int bar, bar_nr = 0;
 	int found_mem64 = 0;
 
-	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 	cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
 
 	for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
@@ -167,7 +167,7 @@ void pciauto_setup_device(struct pci_controller *hose,
 		bar_nr++;
 	}
 
-	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 		CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
@@ -179,9 +179,9 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 	struct pci_region *pci_mem = hose->pci_mem;
 	struct pci_region *pci_prefetch = hose->pci_prefetch;
 	struct pci_region *pci_io = hose->pci_io;
-	unsigned int cmdstat;
+	u16 cmdstat;
 
-	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 
 	/* Configure bus number registers */
 	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
@@ -229,7 +229,8 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 	}
 
 	/* Enable memory and I/O accesses, enable bus master */
-	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND,
+					cmdstat | PCI_COMMAND_MASTER);
 }
 
 void pciauto_postscan_setup_bridge(struct pci_controller *hose,