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体验新版 GitCode,发现更多精彩内容 >>
提交
ad10dd9a
编写于
2月 14, 2003
作者:
S
stroese
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
Add "pcidelay" environment variable (in ms, enabled via CONFIG_PCI_BOOTDELAY).
上级
e5ad56b1
变更
29
隐藏空白更改
内联
并排
Showing
29 changed file
with
176 addition
and
121 deletion
+176
-121
CHANGELOG
CHANGELOG
+6
-0
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
+1
-1
board/bmw/bmw.c
board/bmw/bmw.c
+1
-1
board/cu824/cu824.c
board/cu824/cu824.c
+1
-1
board/eltec/bab7xx/pci.c
board/eltec/bab7xx/pci.c
+1
-1
board/eltec/elppc/pci.c
board/eltec/elppc/pci.c
+1
-1
board/esd/common/pci.c
board/esd/common/pci.c
+1
-1
board/evb64260/pci.c
board/evb64260/pci.c
+1
-1
board/mousse/pci.c
board/mousse/pci.c
+1
-1
board/mpl/common/pci.c
board/mpl/common/pci.c
+1
-1
board/musenki/musenki.c
board/musenki/musenki.c
+1
-1
board/oxc/oxc.c
board/oxc/oxc.c
+1
-1
board/pcippc2/pcippc2.c
board/pcippc2/pcippc2.c
+1
-1
board/pn62/pn62.c
board/pn62/pn62.c
+1
-1
board/sandpoint/sandpoint.c
board/sandpoint/sandpoint.c
+1
-1
board/sc520_cdp/sc520_cdp.c
board/sc520_cdp/sc520_cdp.c
+62
-62
board/utx8245/utx8245.c
board/utx8245/utx8245.c
+1
-1
common/env_common.c
common/env_common.c
+3
-0
common/environment.c
common/environment.c
+3
-0
cpu/ppc4xx/405gp_pci.c
cpu/ppc4xx/405gp_pci.c
+2
-2
drivers/pci.c
drivers/pci.c
+19
-0
include/common.h
include/common.h
+2
-1
include/configs/AR405.h
include/configs/AR405.h
+4
-0
include/configs/CPCI405.h
include/configs/CPCI405.h
+3
-0
include/configs/CPCI4052.h
include/configs/CPCI4052.h
+3
-0
include/configs/CPCI440.h
include/configs/CPCI440.h
+4
-0
include/configs/DU405.h
include/configs/DU405.h
+4
-0
include/configs/OCRTC.h
include/configs/OCRTC.h
+2
-0
tools/env/fw_env.c
tools/env/fw_env.c
+44
-41
未找到文件。
CHANGELOG
浏览文件 @
ad10dd9a
...
...
@@ -2,6 +2,12 @@
Changes since U-Boot 0.2.1:
======================================================================
* Patch by Stefan Roese, 13 Feb 2003:
Add "pcidelay" environment variable (in ms, enabled via
CONFIG_PCI_BOOTDELAY).
PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after
RST# to respond to configuration cycles (33MHz -> 1s).
* Patch by Stefan Roese, 10 Feb 2003:
Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c)
...
...
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
浏览文件 @
ad10dd9a
...
...
@@ -107,7 +107,7 @@ int misc_init_r (void)
}
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
#ifndef CONFIG_RAMBOOT
articiaS_pci_init
();
...
...
board/bmw/bmw.c
浏览文件 @
ad10dd9a
...
...
@@ -102,7 +102,7 @@ int misc_init_f (void)
*/
struct
pci_controller
hose
;
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
pci_mpc824x_init
(
&
hose
);
/* pci_dev_init(0); */
...
...
board/cu824/cu824.c
浏览文件 @
ad10dd9a
...
...
@@ -113,7 +113,7 @@ struct pci_controller hose = {
#endif
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
pci_mpc824x_init
(
&
hose
);
}
board/eltec/bab7xx/pci.c
浏览文件 @
ad10dd9a
...
...
@@ -33,7 +33,7 @@
struct
pci_controller
local_hose
;
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
struct
pci_controller
*
hose
=
(
struct
pci_controller
*
)
&
local_hose
;
u32
reg32
;
...
...
board/eltec/elppc/pci.c
浏览文件 @
ad10dd9a
...
...
@@ -33,7 +33,7 @@
struct
pci_controller
local_hose
;
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
struct
pci_controller
*
hose
=
(
struct
pci_controller
*
)
&
local_hose
;
u16
reg16
;
...
...
board/esd/common/pci.c
浏览文件 @
ad10dd9a
...
...
@@ -166,7 +166,7 @@ static struct pci_controller pci9054_hose = {
config_table:
pci9054_config_table
,
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
struct
pci_controller
*
hose
=
&
pci9054_hose
;
...
...
board/evb64260/pci.c
浏览文件 @
ad10dd9a
...
...
@@ -597,7 +597,7 @@ struct pci_controller pci1_hose = {
};
void
pci_init
(
void
)
pci_init
_board
(
void
)
{
unsigned
int
command
;
...
...
board/mousse/pci.c
浏览文件 @
ad10dd9a
...
...
@@ -277,7 +277,7 @@ struct pci_controller hose = {
fixup_irq:
pci_mousse_fixup_irq
,
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
pci_mpc824x_init
(
&
hose
);
}
board/mpl/common/pci.c
浏览文件 @
ad10dd9a
...
...
@@ -90,7 +90,7 @@ static struct pci_controller hose = {
fixup_irq:
pci_pip405_fixup_irq
,
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
/*we want the ptrs to RAM not flash (ie don't use init list)*/
hose
.
fixup_irq
=
pci_pip405_fixup_irq
;
...
...
board/musenki/musenki.c
浏览文件 @
ad10dd9a
...
...
@@ -124,7 +124,7 @@ struct pci_controller hose = {
#endif
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
pci_mpc824x_init
(
&
hose
);
}
board/oxc/oxc.c
浏览文件 @
ad10dd9a
...
...
@@ -108,7 +108,7 @@ static struct pci_controller hose = {
#endif
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
pci_mpc824x_init
(
&
hose
);
}
...
...
board/pcippc2/pcippc2.c
浏览文件 @
ad10dd9a
...
...
@@ -135,7 +135,7 @@ int misc_init_r (void)
return
(
0
);
}
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
cpc710_pci_init
();
...
...
board/pn62/pn62.c
浏览文件 @
ad10dd9a
...
...
@@ -137,7 +137,7 @@ long int initdram (int board_type)
struct
pci_controller
hose
=
{
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
show_startup_phase
(
4
);
pci_mpc824x_init
(
&
hose
);
...
...
board/sandpoint/sandpoint.c
浏览文件 @
ad10dd9a
...
...
@@ -121,7 +121,7 @@ struct pci_controller hose = {
#endif
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
pci_mpc824x_init
(
&
hose
);
}
board/sc520_cdp/sc520_cdp.c
浏览文件 @
ad10dd9a
...
...
@@ -31,35 +31,35 @@
static
void
irq_init
(
void
)
{
/* disable global interrupt mode */
write_mmcr_byte
(
SC520_PICICR
,
0x40
);
write_mmcr_byte
(
SC520_PICICR
,
0x40
);
/* set irq0-7 to edge */
write_mmcr_byte
(
SC520_MPICMODE
,
0x00
);
/* set irq9-12 to level, all the other (8, 13-15) are edge */
write_mmcr_byte
(
SC520_SL1PICMODE
,
0x1e
);
/* set irq16-24 (unused slave pic2) to level */
write_mmcr_byte
(
SC520_SL2PICMODE
,
0xff
);
/* active low polarity on PIC interrupt pins,
/* active low polarity on PIC interrupt pins,
active high polarity on all other irq pins */
write_mmcr_word
(
SC520_INTPINPOL
,
0
);
/* set irq number mapping */
write_mmcr_byte
(
SC520_GPTMR0MAP
,
0
);
/* disable GP timer 0 INT */
write_mmcr_byte
(
SC520_GPTMR0MAP
,
0
);
/* disable GP timer 0 INT */
write_mmcr_byte
(
SC520_GPTMR1MAP
,
0
);
/* disable GP timer 1 INT */
write_mmcr_byte
(
SC520_GPTMR2MAP
,
0
);
/* disable GP timer 2 INT */
write_mmcr_byte
(
SC520_PIT0MAP
,
0x1
);
/* Set PIT timer 0 INT to IRQ0 */
write_mmcr_byte
(
SC520_PIT0MAP
,
0x1
);
/* Set PIT timer 0 INT to IRQ0 */
write_mmcr_byte
(
SC520_PIT1MAP
,
0
);
/* diable PIT timer 1 INT */
write_mmcr_byte
(
SC520_PIT2MAP
,
0
);
/* diable PIT timer 2 INT */
write_mmcr_byte
(
SC520_PCIINTAMAP
,
0x4
);
/* Set PCI INT A to IRQ9 */
write_mmcr_byte
(
SC520_PCIINTBMAP
,
0x5
);
/* Set PCI INT B to IRQ10 */
write_mmcr_byte
(
SC520_PCIINTCMAP
,
0x6
);
/* Set PCI INT C to IRQ11 */
write_mmcr_byte
(
SC520_PCIINTDMAP
,
0x7
);
/* Set PCI INT D to IRQ12 */
write_mmcr_byte
(
SC520_DMABCINTMAP
,
0
);
/* disable DMA INT */
write_mmcr_byte
(
SC520_DMABCINTMAP
,
0
);
/* disable DMA INT */
write_mmcr_byte
(
SC520_SSIMAP
,
0
);
/* disable Synchronius serial INT */
write_mmcr_byte
(
SC520_WDTMAP
,
0
);
/* disable Watchdor INT */
write_mmcr_byte
(
SC520_RTCMAP
,
0x3
);
/* Set RTC int to 8 */
...
...
@@ -69,28 +69,28 @@ static void irq_init(void)
write_mmcr_byte
(
SC520_GP0IMAP
,
6
);
/* Set GPIRQ0 (ISA IRQ2) to IRQ9 */
write_mmcr_byte
(
SC520_GP1IMAP
,
2
);
/* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
write_mmcr_byte
(
SC520_GP2IMAP
,
7
);
/* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
if
(
CFG_USE_SIO_UART
)
{
write_mmcr_byte
(
SC520_UART1MAP
,
0
);
/* disable internal UART1 INT */
write_mmcr_byte
(
SC520_UART2MAP
,
0
);
/* disable internal UART2 INT */
write_mmcr_byte
(
SC520_GP3IMAP
,
11
);
/* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
write_mmcr_byte
(
SC520_GP3IMAP
,
11
);
/* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
write_mmcr_byte
(
SC520_GP4IMAP
,
12
);
/* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
}
else
{
write_mmcr_byte
(
SC520_UART1MAP
,
12
);
/* Set internal UART2 INT to IRQ4 */
write_mmcr_byte
(
SC520_UART2MAP
,
11
);
/* Set internal UART2 INT to IRQ3 */
write_mmcr_byte
(
SC520_GP3IMAP
,
0
);
/* disable GPIRQ3 (ISA IRQ3) */
write_mmcr_byte
(
SC520_GP3IMAP
,
0
);
/* disable GPIRQ3 (ISA IRQ3) */
write_mmcr_byte
(
SC520_GP4IMAP
,
0
);
/* disable GPIRQ4 (ISA IRQ4) */
}
write_mmcr_byte
(
SC520_GP5IMAP
,
13
);
/* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
write_mmcr_byte
(
SC520_GP6IMAP
,
21
);
/* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
write_mmcr_byte
(
SC520_GP7IMAP
,
22
);
/* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
write_mmcr_byte
(
SC520_GP8IMAP
,
3
);
/* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
write_mmcr_byte
(
SC520_GP9IMAP
,
4
);
/* Set GPIRQ9 (ISA IRQ9) to IRQ9 */
write_mmcr_byte
(
SC520_GP10IMAP
,
9
);
/* Set GPIRQ10 (ISA IRQ10) to IRQ10 */
write_mmcr_byte
(
SC520_GP10IMAP
,
9
);
/* Set GPIRQ10 (ISA IRQ10) to IRQ10 */
write_mmcr_word
(
SC520_PCIHOSTMAP
,
0x11f
);
/* Map PCI hostbridge INT to NMI */
write_mmcr_word
(
SC520_ECCMAP
,
0x100
);
/* Map SDRAM ECC failure INT to NMI */
}
/* PCI stuff */
...
...
@@ -98,11 +98,11 @@ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
char
pin
;
int
irq
;
pci_hose_read_config_byte
(
hose
,
dev
,
PCI_INTERRUPT_PIN
,
&
pin
);
irq
=
pin
-
1
;
switch
(
PCI_DEV
(
dev
))
{
case
20
:
break
;
...
...
@@ -115,25 +115,25 @@ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
case
17
:
irq
+=
3
;
break
;
default:
default:
return
;
}
irq
&=
3
;
/* wrap around */
irq
+=
9
;
/* lowest IRQ is 9 */
pci_hose_write_config_byte
(
hose
,
dev
,
PCI_INTERRUPT_LINE
,
irq
);
#if 0
printf("fixup_irq: device %d pin %c irq %d\n",
#if 0
printf("fixup_irq: device %d pin %c irq %d\n",
PCI_DEV(dev), 'A' + pin -1, irq);
#endif
}
static
struct
pci_controller
sc520_cdp_hose
=
{
fixup_irq:
pci_sc520_cdp_fixup_irq
,
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
pci_sc520_init
(
&
sc520_cdp_hose
);
}
...
...
@@ -147,7 +147,7 @@ static void silence_uart(int port)
void
setup_ali_sio
(
int
uart_primary
)
{
ali512x_init
();
ali512x_set_fdc
(
ALI_ENABLED
,
0x3f2
,
6
,
0
);
ali512x_set_pp
(
ALI_ENABLED
,
0x278
,
7
,
3
);
ali512x_set_uart
(
ALI_ENABLED
,
ALI_UART1
,
uart_primary
?
0x3f8
:
0x3e8
,
4
);
...
...
@@ -155,21 +155,21 @@ void setup_ali_sio(int uart_primary)
ali512x_set_rtc
(
ALI_DISABLED
,
0
,
0
);
ali512x_set_kbc
(
ALI_ENABLED
,
1
,
12
);
ali512x_set_cio
(
ALI_ENABLED
);
/* IrDa pins */
ali512x_cio_function
(
12
,
1
,
0
,
0
);
ali512x_cio_function
(
13
,
1
,
0
,
0
);
/* SSI chip select pins */
ali512x_cio_function
(
14
,
0
,
0
,
0
);
/* SSI_CS */
ali512x_cio_function
(
15
,
0
,
0
,
0
);
/* SSI_MV */
ali512x_cio_function
(
15
,
0
,
0
,
0
);
/* SSI_MV */
ali512x_cio_function
(
16
,
0
,
1
,
0
);
/* SSI_SPI# (inverted) */
/* Board REV pins */
ali512x_cio_function
(
20
,
0
,
0
,
1
);
ali512x_cio_function
(
21
,
0
,
0
,
1
);
ali512x_cio_function
(
22
,
0
,
0
,
1
);
ali512x_cio_function
(
23
,
0
,
0
,
1
);
ali512x_cio_function
(
23
,
0
,
0
,
1
);
}
...
...
@@ -178,13 +178,13 @@ static void bus_init(void)
{
/* set up the GP IO pins */
write_mmcr_word
(
SC520_PIOPFS31_16
,
0xf7ff
);
/* set the GPIO pin function 31-16 reg */
write_mmcr_word
(
SC520_PIOPFS31_16
,
0xf7ff
);
/* set the GPIO pin function 31-16 reg */
write_mmcr_word
(
SC520_PIOPFS15_0
,
0xffff
);
/* set the GPIO pin function 15-0 reg */
write_mmcr_byte
(
SC520_CSPFS
,
0xf8
);
/* set the CS pin function reg */
write_mmcr_byte
(
SC520_CSPFS
,
0xf8
);
/* set the CS pin function reg */
write_mmcr_byte
(
SC520_CLKSEL
,
0x70
);
write_mmcr_byte
(
SC520_GPCSRT
,
1
);
/* set the GP CS offset */
write_mmcr_byte
(
SC520_GPCSRT
,
1
);
/* set the GP CS offset */
write_mmcr_byte
(
SC520_GPCSPW
,
3
);
/* set the GP CS pulse width */
write_mmcr_byte
(
SC520_GPCSOFF
,
1
);
/* set the GP CS offset */
write_mmcr_byte
(
SC520_GPRDW
,
3
);
/* set the RD pulse width */
...
...
@@ -192,40 +192,40 @@ static void bus_init(void)
write_mmcr_byte
(
SC520_GPWRW
,
3
);
/* set the GP WR pulse width */
write_mmcr_byte
(
SC520_GPWROFF
,
1
);
/* set the GP WR offset */
write_mmcr_word
(
SC520_BOOTCSCTL
,
0x1823
);
/* set up timing of BOOTCS */
write_mmcr_word
(
SC520_BOOTCSCTL
,
0x1823
);
/* set up timing of BOOTCS */
write_mmcr_word
(
SC520_ROMCS1CTL
,
0x1823
);
/* set up timing of ROMCS1 */
write_mmcr_word
(
SC520_ROMCS2CTL
,
0x1823
);
/* set up timing of ROMCS2 */
write_mmcr_word
(
SC520_ROMCS2CTL
,
0x1823
);
/* set up timing of ROMCS2 */
/* adjust the memory map:
* by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
* and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
* we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
* we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
/* SRAM = GPCS3 128k @ d0000-effff*/
write_mmcr_long
(
SC520_PAR2
,
0x4e00400d
);
write_mmcr_long
(
SC520_PAR2
,
0x4e00400d
);
/* IDE0 = GPCS6 1f0-1f7 */
write_mmcr_long
(
SC520_PAR3
,
0x380801f0
);
write_mmcr_long
(
SC520_PAR3
,
0x380801f0
);
/* IDE1 = GPCS7 3f6 */
write_mmcr_long
(
SC520_PAR4
,
0x3c0003f6
);
write_mmcr_long
(
SC520_PAR4
,
0x3c0003f6
);
/* bootcs */
write_mmcr_long
(
SC520_PAR12
,
0x8bffe800
);
write_mmcr_long
(
SC520_PAR12
,
0x8bffe800
);
/* romcs2 */
write_mmcr_long
(
SC520_PAR13
,
0xcbfff000
);
write_mmcr_long
(
SC520_PAR13
,
0xcbfff000
);
/* romcs1 */
write_mmcr_long
(
SC520_PAR14
,
0xabfff800
);
write_mmcr_long
(
SC520_PAR14
,
0xabfff800
);
/* 680 LEDS */
write_mmcr_long
(
SC520_PAR15
,
0x30000640
);
asm
(
"wbinvd
\n
"
);
/* Flush cache, req. after setting the unchached attribute ona PAR */
write_mmcr_long
(
SC520_PAR15
,
0x30000640
);
asm
(
"wbinvd
\n
"
);
/* Flush cache, req. after setting the unchached attribute ona PAR */
if
(
CFG_USE_SIO_UART
)
{
write_mmcr_byte
(
SC520_ADDDECCTL
,
read_mmcr_byte
(
SC520_ADDDECCTL
)
|
UART2_DIS
|
UART1_DIS
);
write_mmcr_byte
(
SC520_ADDDECCTL
,
read_mmcr_byte
(
SC520_ADDDECCTL
)
|
UART2_DIS
|
UART1_DIS
);
setup_ali_sio
(
1
);
}
else
{
write_mmcr_byte
(
SC520_ADDDECCTL
,
read_mmcr_byte
(
SC520_ADDDECCTL
)
&
~
(
UART2_DIS
|
UART1_DIS
));
write_mmcr_byte
(
SC520_ADDDECCTL
,
read_mmcr_byte
(
SC520_ADDDECCTL
)
&
~
(
UART2_DIS
|
UART1_DIS
));
setup_ali_sio
(
0
);
silence_uart
(
0x3e8
);
silence_uart
(
0x2e8
);
...
...
@@ -242,21 +242,21 @@ static void bus_init(void)
int
board_init
(
void
)
{
DECLARE_GLOBAL_DATA_PTR
;
init_sc520
();
init_sc520
();
bus_init
();
irq_init
();
/* max drive current on SDRAM */
write_mmcr_word
(
SC520_DSCTL
,
0x0100
);
/* enter debug mode after next reset (only if jumper is also set) */
write_mmcr_byte
(
SC520_RESCFG
,
0x08
);
/* configure the software timer to 33.333MHz */
write_mmcr_byte
(
SC520_SWTMRCFG
,
0
);
gd
->
bus_clk
=
33333000
;
return
0
;
}
...
...
@@ -277,14 +277,14 @@ int last_stage_init(void)
{
int
minor
;
int
major
;
major
=
minor
=
0
;
major
|=
ali512x_cio_in
(
23
)
?
2
:
0
;
major
|=
ali512x_cio_in
(
22
)
?
1
:
0
;
minor
|=
ali512x_cio_in
(
21
)
?
2
:
0
;
minor
|=
ali512x_cio_in
(
20
)
?
1
:
0
;
printf
(
"AMD SC520 CDP revision %d.%d
\n
"
,
major
,
minor
);
return
0
;
}
board/utx8245/utx8245.c
浏览文件 @
ad10dd9a
...
...
@@ -143,7 +143,7 @@ static struct pci_controller utx8245_hose = {
#endif
/*CONFIG_PCI_PNP*/
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
pci_mpc824x_init
(
&
utx8245_hose
);
...
...
common/env_common.c
浏览文件 @
ad10dd9a
...
...
@@ -128,6 +128,9 @@ uchar default_environment[] = {
#ifdef CONFIG_CLOCKS_IN_MHZ
"clocks_in_mhz=1
\0
"
#endif
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay="
MK_STR
(
CONFIG_PCI_BOOTDELAY
)
"
\0
"
#endif
#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
...
...
common/environment.c
浏览文件 @
ad10dd9a
...
...
@@ -164,6 +164,9 @@ env_t environment __PPCENV__ = {
#ifdef CONFIG_CLOCKS_IN_MHZ
"clocks_in_mhz="
"1"
"
\0
"
#endif
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay="
MK_STR
(
CONFIG_PCI_BOOTDELAY
)
"
\0
"
#endif
#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
...
...
cpu/ppc4xx/405gp_pci.c
浏览文件 @
ad10dd9a
...
...
@@ -376,7 +376,7 @@ static struct pci_controller hose = {
config_table:
pci_405gp_config_table
,
};
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
/*we want the ptrs to RAM not flash (ie don't use init list)*/
hose
.
fixup_irq
=
pci_405gp_fixup_irq
;
...
...
@@ -494,7 +494,7 @@ void pci_440_init (struct pci_controller *hose)
}
void
pci_init
(
void
)
void
pci_init
_board
(
void
)
{
pci_440_init
(
&
ppc440_hose
);
}
...
...
drivers/pci.c
浏览文件 @
ad10dd9a
...
...
@@ -505,4 +505,23 @@ int pci_hose_scan(struct pci_controller *hose)
return
pci_hose_scan_bus
(
hose
,
hose
->
first_busno
);
}
void
pci_init
(
void
)
{
#if defined(CONFIG_PCI_BOOTDELAY)
char
*
s
;
int
i
;
/* wait "pcidelay" ms (if defined)... */
s
=
getenv
(
"pcidelay"
);
if
(
s
)
{
int
val
=
simple_strtoul
(
s
,
NULL
,
10
);
for
(
i
=
0
;
i
<
val
;
i
++
)
udelay
(
1000
);
}
#endif
/* CONFIG_PCI_BOOTDELAY */
/* now call board specific pci_init()... */
pci_init_board
();
}
#endif
/* CONFIG_PCI */
include/common.h
浏览文件 @
ad10dd9a
...
...
@@ -149,10 +149,11 @@ void setenv (char *, char *);
# include <asm/u-boot-arm.h>
/* ARM version to be fixed! */
#endif
/* CONFIG_ARM */
#ifdef CONFIG_I386
/* x86 version to be fixed! */
# include <asm/ppcboot-i386.h>
# include <asm/ppcboot-i386.h>
#endif
/* CONFIG_I386 */
void
pci_init
(
void
);
void
pci_init_board
(
void
);
void
pciinfo
(
int
,
int
);
#if defined(CONFIG_PCI) && defined(CONFIG_440)
...
...
include/configs/AR405.h
浏览文件 @
ad10dd9a
...
...
@@ -122,6 +122,10 @@
#define CONFIG_PCI_PNP
/* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW
/* print pci devices @ startup */
#define CONFIG_PCI_BOOTDELAY 0
/* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x12FE
/* PCI Vendor ID: esd gmbh */
#define CFG_PCI_SUBSYS_DEVICEID 0x0403
/* PCI Device ID: ARISTO405 */
#define CFG_PCI_PTM1LA 0x00000000
/* point to sdram */
...
...
include/configs/CPCI405.h
浏览文件 @
ad10dd9a
...
...
@@ -74,6 +74,7 @@
CFG_CMD_IRQ | \
CFG_CMD_IDE | \
CFG_CMD_ELF | \
CFG_CMD_MII | \
CFG_CMD_EEPROM )
#define CONFIG_MAC_PARTITION
...
...
@@ -144,6 +145,8 @@
#define CONFIG_PCI_SCAN_SHOW
/* print pci devices @ startup */
#define CONFIG_PCI_BOOTDELAY 0
/* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x12FE
/* PCI Vendor ID: esd gmbh */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405
/* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406
/* PCI Device ID: CPCI-405-A */
...
...
include/configs/CPCI4052.h
浏览文件 @
ad10dd9a
...
...
@@ -80,6 +80,7 @@
CFG_CMD_DATE | \
CFG_CMD_JFFS2 | \
CFG_CMD_I2C | \
CFG_CMD_MII | \
CFG_CMD_EEPROM )
#define CONFIG_MAC_PARTITION
...
...
@@ -150,6 +151,8 @@
#define CONFIG_PCI_SCAN_SHOW
/* print pci devices @ startup */
#define CONFIG_PCI_BOOTDELAY 0
/* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x12FE
/* PCI Vendor ID: esd gmbh */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405
/* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406
/* PCI Device ID: CPCI-405-A */
...
...
include/configs/CPCI440.h
浏览文件 @
ad10dd9a
...
...
@@ -237,6 +237,10 @@
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
...
...
include/configs/DU405.h
浏览文件 @
ad10dd9a
...
...
@@ -120,6 +120,10 @@
#define CONFIG_PCI_PNP
/* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW
/* print pci devices @ startup */
#define CONFIG_PCI_BOOTDELAY 0
/* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x12FE
/* PCI Vendor ID: esd gmbh */
#define CFG_PCI_SUBSYS_DEVICEID 0x0404
/* PCI Device ID: CPCI-ISER4 */
#define CFG_PCI_PTM1LA 0x00000000
/* point to sdram */
...
...
include/configs/OCRTC.h
浏览文件 @
ad10dd9a
...
...
@@ -120,6 +120,8 @@
#define CONFIG_PCI_SCAN_SHOW
/* print pci devices @ startup */
#define CONFIG_PCI_BOOTDELAY 0
/* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x12FE
/* PCI Vendor ID: esd gmbh */
#define CFG_PCI_SUBSYS_DEVICEID 0x0410
/* PCI Device ID: OCRTC */
#define CFG_PCI_CLASSCODE 0x0b20
/* PCI Class Code: Processor/PPC*/
...
...
tools/env/fw_env.c
浏览文件 @
ad10dd9a
...
...
@@ -142,6 +142,9 @@ static uchar default_environment[] = {
#ifdef CONFIG_CLOCKS_IN_MHZ
"clocks_in_mhz="
"1"
"
\0
"
#endif
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay="
MK_STR
(
CONFIG_PCI_BOOTDELAY
)
"
\0
"
#endif
#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
...
...
@@ -387,8 +390,8 @@ static int flash_io (int mode)
char
*
data
;
if
((
fd
=
open
(
DEVNAME
(
curdev
),
mode
))
<
0
)
{
fprintf
(
stderr
,
"Can't open %s: %s
\n
"
,
fprintf
(
stderr
,
"Can't open %s: %s
\n
"
,
DEVNAME
(
curdev
),
strerror
(
errno
));
return
(
-
1
);
}
...
...
@@ -403,8 +406,8 @@ static int flash_io (int mode)
/* switch to next partition for writing */
otherdev
=
!
curdev
;
if
((
fdr
=
open
(
DEVNAME
(
otherdev
),
mode
))
<
0
)
{
fprintf
(
stderr
,
"Can't open %s: %s
\n
"
,
fprintf
(
stderr
,
"Can't open %s: %s
\n
"
,
DEVNAME
(
otherdev
),
strerror
(
errno
));
return
(
-
1
);
}
...
...
@@ -428,20 +431,20 @@ static int flash_io (int mode)
resid
=
DEVESIZE
(
otherdev
)
-
CFG_ENV_SIZE
;
if
(
resid
)
{
if
((
data
=
malloc
(
resid
))
==
NULL
)
{
fprintf
(
stderr
,
fprintf
(
stderr
,
"Cannot malloc %d bytes: %s
\n
"
,
resid
,
strerror
(
errno
));
return
(
-
1
);
}
if
(
lseek
(
fdr
,
DEVOFFSET
(
otherdev
)
+
CFG_ENV_SIZE
,
SEEK_SET
)
==
-
1
)
{
fprintf
(
stderr
,
"seek error on %s: %s
\n
"
,
"seek error on %s: %s
\n
"
,
DEVNAME
(
otherdev
),
strerror
(
errno
));
return
(
-
1
);
}
if
((
rc
=
read
(
fdr
,
data
,
resid
))
!=
resid
)
{
fprintf
(
stderr
,
"read error on %s: %s
\n
"
,
"read error on %s: %s
\n
"
,
DEVNAME
(
otherdev
),
strerror
(
errno
));
return
(
-
1
);
}
...
...
@@ -462,26 +465,26 @@ static int flash_io (int mode)
printf
(
"Writing environment to %s...
\n
"
,
DEVNAME
(
otherdev
));
if
(
lseek
(
fdr
,
DEVOFFSET
(
otherdev
),
SEEK_SET
)
==
-
1
)
{
fprintf
(
stderr
,
"seek error on %s: %s
\n
"
,
"seek error on %s: %s
\n
"
,
DEVNAME
(
otherdev
),
strerror
(
errno
));
return
(
-
1
);
}
if
(
write
(
fdr
,
&
environment
,
len
)
!=
len
)
{
fprintf
(
stderr
,
"CRC write error on %s: %s
\n
"
,
"CRC write error on %s: %s
\n
"
,
DEVNAME
(
otherdev
),
strerror
(
errno
));
return
(
-
1
);
}
if
(
write
(
fdr
,
environment
.
data
,
ENV_SIZE
)
!=
ENV_SIZE
)
{
fprintf
(
stderr
,
"Write error on %s: %s
\n
"
,
"Write error on %s: %s
\n
"
,
DEVNAME
(
otherdev
),
strerror
(
errno
));
return
(
-
1
);
}
if
(
resid
)
{
if
(
write
(
fdr
,
data
,
resid
)
!=
resid
)
{
fprintf
(
stderr
,
"write error on %s: %s
\n
"
,
"write error on %s: %s
\n
"
,
DEVNAME
(
curdev
),
strerror
(
errno
));
return
(
-
1
);
}
...
...
@@ -491,14 +494,14 @@ static int flash_io (int mode)
/* change flag on current active env partition */
if
(
lseek
(
fd
,
DEVOFFSET
(
curdev
)
+
sizeof
(
ulong
),
SEEK_SET
)
==
-
1
)
{
fprintf
(
stderr
,
"seek error on %s: %s
\n
"
,
"seek error on %s: %s
\n
"
,
DEVNAME
(
curdev
),
strerror
(
errno
));
return
(
-
1
);
}
if
(
write
(
fd
,
&
obsolete_flag
,
sizeof
(
obsolete_flag
))
!=
if
(
write
(
fd
,
&
obsolete_flag
,
sizeof
(
obsolete_flag
))
!=
sizeof
(
obsolete_flag
))
{
fprintf
(
stderr
,
"Write error on %s: %s
\n
"
,
"Write error on %s: %s
\n
"
,
DEVNAME
(
curdev
),
strerror
(
errno
));
return
(
-
1
);
}
...
...
@@ -514,7 +517,7 @@ static int flash_io (int mode)
ioctl
(
fd
,
MEMLOCK
,
&
erase
);
if
(
close
(
fdr
))
{
fprintf
(
stderr
,
"I/O error on %s: %s
\n
"
,
"I/O error on %s: %s
\n
"
,
DEVNAME
(
otherdev
),
strerror
(
errno
));
return
(
-
1
);
}
...
...
@@ -524,19 +527,19 @@ static int flash_io (int mode)
if
(
lseek
(
fd
,
DEVOFFSET
(
curdev
),
SEEK_SET
)
==
-
1
)
{
fprintf
(
stderr
,
"seek error on %s: %s
\n
"
,
"seek error on %s: %s
\n
"
,
DEVNAME
(
curdev
),
strerror
(
errno
));
return
(
-
1
);
}
if
(
read
(
fd
,
&
environment
,
len
)
!=
len
)
{
fprintf
(
stderr
,
"CRC read error on %s: %s
\n
"
,
"CRC read error on %s: %s
\n
"
,
DEVNAME
(
curdev
),
strerror
(
errno
));
return
(
-
1
);
}
if
((
rc
=
read
(
fd
,
environment
.
data
,
ENV_SIZE
))
!=
ENV_SIZE
)
{
fprintf
(
stderr
,
"Read error on %s: %s
\n
"
,
"Read error on %s: %s
\n
"
,
DEVNAME
(
curdev
),
strerror
(
errno
));
return
(
-
1
);
}
...
...
@@ -544,7 +547,7 @@ static int flash_io (int mode)
if
(
close
(
fd
))
{
fprintf
(
stderr
,
"I/O error on %s: %s
\n
"
,
"I/O error on %s: %s
\n
"
,
DEVNAME
(
curdev
),
strerror
(
errno
));
return
(
-
1
);
}
...
...
@@ -584,50 +587,50 @@ static int env_init(void)
if
(
parse_config
())
/* should fill envdevices */
return
1
;
if
((
addr1
=
calloc
(
1
,
ENV_SIZE
))
==
NULL
)
{
fprintf
(
stderr
,
fprintf
(
stderr
,
"Not enough memory for environment (%ld bytes)
\n
"
,
ENV_SIZE
);
return
(
errno
);
}
/* read environment from FLASH to local buffer */
environment
.
data
=
addr1
;
curdev
=
0
;
if
(
flash_io
(
O_RDONLY
))
{
return
(
errno
);
}
crc1_ok
=
((
crc1
=
crc32
(
0
,
environment
.
data
,
ENV_SIZE
))
crc1_ok
=
((
crc1
=
crc32
(
0
,
environment
.
data
,
ENV_SIZE
))
==
environment
.
crc
);
if
(
!
HaveRedundEnv
)
{
if
(
!
crc1_ok
)
{
fprintf
(
stderr
,
fprintf
(
stderr
,
"Warning: Bad CRC, using default environment
\n
"
);
environment
.
data
=
default_environment
;
free
(
addr1
);
}
}
else
{
flag1
=
environment
.
flags
;
curdev
=
1
;
if
((
addr2
=
calloc
(
1
,
ENV_SIZE
))
==
NULL
)
{
fprintf
(
stderr
,
fprintf
(
stderr
,
"Not enough memory for environment (%ld bytes)
\n
"
,
ENV_SIZE
);
return
(
errno
);
}
}
environment
.
data
=
addr2
;
if
(
flash_io
(
O_RDONLY
))
{
return
(
errno
);
}
crc2_ok
=
((
crc2
=
crc32
(
0
,
environment
.
data
,
ENV_SIZE
))
crc2_ok
=
((
crc2
=
crc32
(
0
,
environment
.
data
,
ENV_SIZE
))
==
environment
.
crc
);
flag2
=
environment
.
flags
;
if
(
crc1_ok
&&
!
crc2_ok
)
{
environment
.
data
=
addr1
;
environment
.
flags
=
flag1
;
...
...
@@ -643,7 +646,7 @@ static int env_init(void)
free
(
addr1
);
}
else
if
(
!
crc1_ok
&&
!
crc2_ok
)
{
fprintf
(
stderr
,
fprintf
(
stderr
,
"Warning: Bad CRC, using default environment
\n
"
);
environment
.
data
=
default_environment
;
curdev
=
0
;
...
...
@@ -717,15 +720,15 @@ static int parse_config()
#endif
#endif
if
(
stat
(
DEVNAME
(
0
),
&
st
))
{
fprintf
(
stderr
,
"Cannot access MTD device %s: %s
\n
"
,
fprintf
(
stderr
,
"Cannot access MTD device %s: %s
\n
"
,
DEVNAME
(
0
),
strerror
(
errno
));
return
1
;
}
if
(
HaveRedundEnv
&&
stat
(
DEVNAME
(
1
),
&
st
))
{
fprintf
(
stderr
,
"Cannot access MTD device %s: %s
\n
"
,
fprintf
(
stderr
,
"Cannot access MTD device %s: %s
\n
"
,
DEVNAME
(
2
),
strerror
(
errno
));
return
1
;
}
...
...
@@ -744,12 +747,12 @@ static int get_config (char *fname)
return
1
;
}
while
((
i
<
2
)
&&
while
((
i
<
2
)
&&
((
rc
=
fscanf
(
fp
,
"%s %lx %lx %lx"
,
DEVNAME
(
i
),
&
DEVOFFSET
(
i
),
&
ENVSIZE
(
i
),
&
DEVESIZE
(
i
)))
!=
EOF
))
{
/* Skip incomplete conversions and comment strings */
if
((
rc
<
3
)
||
(
*
DEVNAME
(
i
)
==
'#'
))
{
if
((
rc
<
3
)
||
(
*
DEVNAME
(
i
)
==
'#'
))
{
fgets
(
dump
,
sizeof
(
dump
),
fp
);
/* Consume till end */
continue
;
}
...
...
@@ -757,7 +760,7 @@ static int get_config (char *fname)
i
++
;
}
fclose
(
fp
);
HaveRedundEnv
=
i
-
1
;
if
(
!
i
)
{
/* No valid entries found */
errno
=
EINVAL
;
...
...
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