提交 ab05406e 编写于 作者: M Masahiro Yamada

clk: uniphier: add PXs3 clock data

Add basic clock data for Socionext's new SoC PXs3.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
上级 d6c7ee7d
......@@ -296,6 +296,10 @@ static const struct udevice_id uniphier_clk_match[] = {
.compatible = "socionext,uniphier-ld20-clock",
.data = (ulong)uniphier_ld20_sys_clk_data,
},
{
.compatible = "socionext,uniphier-pxs3-clock",
.data = (ulong)uniphier_pxs3_sys_clk_data,
},
/* Media I/O clock */
{
.compatible = "socionext,uniphier-ld4-mio-clock",
......@@ -325,6 +329,10 @@ static const struct udevice_id uniphier_clk_match[] = {
.compatible = "socionext,uniphier-ld20-sd-clock",
.data = (ulong)uniphier_mio_clk_data,
},
{
.compatible = "socionext,uniphier-pxs3-sd-clock",
.data = (ulong)uniphier_mio_clk_data,
},
{ /* sentinel */ }
};
......
......@@ -30,3 +30,17 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
{ /* sentinel */ }
#endif
};
const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 16), /* usb30-phy0 */
UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 18), /* usb30-phy1 */
UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20), /* usb30-phy2 */
UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17), /* usb31-phy0 */
UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19), /* usb31-phy1 */
{ /* sentinel */ }
#endif
};
......@@ -73,6 +73,7 @@ struct uniphier_clk_data {
extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
extern const struct uniphier_clk_data uniphier_mio_clk_data[];
#endif /* __CLK_UNIPHIER_H__ */
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