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体验新版 GitCode,发现更多精彩内容 >>
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aa5f75f2
编写于
8月 13, 2008
作者:
S
Scott Wood
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
at91: Update board NAND drivers to current API.
Signed-off-by:
N
Scott Wood
<
scottwood@freescale.com
>
上级
d438d508
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
90 addition
and
95 deletion
+90
-95
board/atmel/at91cap9adk/nand.c
board/atmel/at91cap9adk/nand.c
+18
-19
board/atmel/at91sam9260ek/nand.c
board/atmel/at91sam9260ek/nand.c
+18
-19
board/atmel/at91sam9261ek/nand.c
board/atmel/at91sam9261ek/nand.c
+18
-19
board/atmel/at91sam9263ek/nand.c
board/atmel/at91sam9263ek/nand.c
+18
-19
board/atmel/at91sam9rlek/nand.c
board/atmel/at91sam9rlek/nand.c
+18
-19
未找到文件。
board/atmel/at91cap9adk/nand.c
浏览文件 @
aa5f75f2
...
...
@@ -37,36 +37,35 @@
#define MASK_ALE (1 << 21)
/* our ALE is AD21 */
#define MASK_CLE (1 << 22)
/* our CLE is AD22 */
static
void
at91cap9adk_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
)
static
void
at91cap9adk_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
,
unsigned
int
ctrl
)
{
struct
nand_chip
*
this
=
mtd
->
priv
;
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
switch
(
cmd
)
{
case
NAND_CTL_SETCLE
:
IO_ADDR_W
|=
MASK_CLE
;
break
;
case
NAND_CTL_SETALE
:
IO_ADDR_W
|=
MASK_ALE
;
break
;
case
NAND_CTL_CLRNCE
:
at91_set_gpio_value
(
AT91_PIN_PD15
,
1
);
break
;
case
NAND_CTL_SETNCE
:
at91_set_gpio_value
(
AT91_PIN_PD15
,
0
);
break
;
if
(
ctrl
&
NAND_CTRL_CHANGE
)
{
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
if
(
ctrl
&
NAND_CLE
)
IO_ADDR_W
|=
MASK_CLE
;
if
(
ctrl
&
NAND_ALE
)
IO_ADDR_W
|=
MASK_ALE
;
at91_set_gpio_value
(
AT91_PIN_PD15
,
!
(
ctrl
&
NAND_NCE
));
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
}
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
if
(
cmd
!=
NAND_CMD_NONE
)
writeb
(
cmd
,
this
->
IO_ADDR_W
);
}
int
board_nand_init
(
struct
nand_chip
*
nand
)
{
nand
->
eccmode
=
NAND_ECC_SOFT
;
nand
->
ecc
.
mode
=
NAND_ECC_SOFT
;
#ifdef CFG_NAND_DBW_16
nand
->
options
=
NAND_BUSWIDTH_16
;
#endif
nand
->
hwcontro
l
=
at91cap9adk_nand_hwcontrol
;
nand
->
cmd_ctr
l
=
at91cap9adk_nand_hwcontrol
;
nand
->
chip_delay
=
20
;
return
0
;
...
...
board/atmel/at91sam9260ek/nand.c
浏览文件 @
aa5f75f2
...
...
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21)
/* our ALE is AD21 */
#define MASK_CLE (1 << 22)
/* our CLE is AD22 */
static
void
at91sam9260ek_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
)
static
void
at91sam9260ek_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
,
unsigned
int
ctrl
)
{
struct
nand_chip
*
this
=
mtd
->
priv
;
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
switch
(
cmd
)
{
case
NAND_CTL_SETCLE
:
IO_ADDR_W
|=
MASK_CLE
;
break
;
case
NAND_CTL_SETALE
:
IO_ADDR_W
|=
MASK_ALE
;
break
;
case
NAND_CTL_CLRNCE
:
at91_set_gpio_value
(
AT91_PIN_PC14
,
1
);
break
;
case
NAND_CTL_SETNCE
:
at91_set_gpio_value
(
AT91_PIN_PC14
,
0
);
break
;
if
(
ctrl
&
NAND_CTRL_CHANGE
)
{
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
if
(
ctrl
&
NAND_CLE
)
IO_ADDR_W
|=
MASK_CLE
;
if
(
ctrl
&
NAND_ALE
)
IO_ADDR_W
|=
MASK_ALE
;
at91_set_gpio_value
(
AT91_PIN_PC14
,
!
(
ctrl
&
NAND_NCE
));
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
}
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
if
(
cmd
!=
NAND_CMD_NONE
)
writeb
(
cmd
,
this
->
IO_ADDR_W
);
}
static
int
at91sam9260ek_nand_ready
(
struct
mtd_info
*
mtd
)
...
...
@@ -67,11 +66,11 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
int
board_nand_init
(
struct
nand_chip
*
nand
)
{
nand
->
eccmode
=
NAND_ECC_SOFT
;
nand
->
ecc
.
mode
=
NAND_ECC_SOFT
;
#ifdef CFG_NAND_DBW_16
nand
->
options
=
NAND_BUSWIDTH_16
;
#endif
nand
->
hwcontro
l
=
at91sam9260ek_nand_hwcontrol
;
nand
->
cmd_ctr
l
=
at91sam9260ek_nand_hwcontrol
;
nand
->
dev_ready
=
at91sam9260ek_nand_ready
;
nand
->
chip_delay
=
20
;
...
...
board/atmel/at91sam9261ek/nand.c
浏览文件 @
aa5f75f2
...
...
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 22)
/* our ALE is AD22 */
#define MASK_CLE (1 << 21)
/* our CLE is AD21 */
static
void
at91sam9261ek_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
)
static
void
at91sam9261ek_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
,
unsigned
int
ctrl
)
{
struct
nand_chip
*
this
=
mtd
->
priv
;
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
switch
(
cmd
)
{
case
NAND_CTL_SETCLE
:
IO_ADDR_W
|=
MASK_CLE
;
break
;
case
NAND_CTL_SETALE
:
IO_ADDR_W
|=
MASK_ALE
;
break
;
case
NAND_CTL_CLRNCE
:
at91_set_gpio_value
(
AT91_PIN_PC14
,
1
);
break
;
case
NAND_CTL_SETNCE
:
at91_set_gpio_value
(
AT91_PIN_PC14
,
0
);
break
;
if
(
ctrl
&
NAND_CTRL_CHANGE
)
{
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
if
(
ctrl
&
NAND_CLE
)
IO_ADDR_W
|=
MASK_CLE
;
if
(
ctrl
&
NAND_ALE
)
IO_ADDR_W
|=
MASK_ALE
;
at91_set_gpio_value
(
AT91_PIN_PC14
,
!
(
ctrl
&
NAND_NCE
));
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
}
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
if
(
cmd
!=
NAND_CMD_NONE
)
writeb
(
cmd
,
this
->
IO_ADDR_W
);
}
static
int
at91sam9261ek_nand_ready
(
struct
mtd_info
*
mtd
)
...
...
@@ -67,11 +66,11 @@ static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
int
board_nand_init
(
struct
nand_chip
*
nand
)
{
nand
->
eccmode
=
NAND_ECC_SOFT
;
nand
->
ecc
.
mode
=
NAND_ECC_SOFT
;
#ifdef CFG_NAND_DBW_16
nand
->
options
=
NAND_BUSWIDTH_16
;
#endif
nand
->
hwcontro
l
=
at91sam9261ek_nand_hwcontrol
;
nand
->
cmd_ctr
l
=
at91sam9261ek_nand_hwcontrol
;
nand
->
dev_ready
=
at91sam9261ek_nand_ready
;
nand
->
chip_delay
=
20
;
...
...
board/atmel/at91sam9263ek/nand.c
浏览文件 @
aa5f75f2
...
...
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21)
/* our ALE is AD21 */
#define MASK_CLE (1 << 22)
/* our CLE is AD22 */
static
void
at91sam9263ek_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
)
static
void
at91sam9263ek_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
,
unsigned
int
ctrl
)
{
struct
nand_chip
*
this
=
mtd
->
priv
;
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
switch
(
cmd
)
{
case
NAND_CTL_SETCLE
:
IO_ADDR_W
|=
MASK_CLE
;
break
;
case
NAND_CTL_SETALE
:
IO_ADDR_W
|=
MASK_ALE
;
break
;
case
NAND_CTL_CLRNCE
:
at91_set_gpio_value
(
AT91_PIN_PD15
,
1
);
break
;
case
NAND_CTL_SETNCE
:
at91_set_gpio_value
(
AT91_PIN_PD15
,
0
);
break
;
if
(
ctrl
&
NAND_CTRL_CHANGE
)
{
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
if
(
ctrl
&
NAND_CLE
)
IO_ADDR_W
|=
MASK_CLE
;
if
(
ctrl
&
NAND_ALE
)
IO_ADDR_W
|=
MASK_ALE
;
at91_set_gpio_value
(
AT91_PIN_PD15
,
!
(
ctrl
&
NAND_NCE
));
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
}
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
if
(
cmd
!=
NAND_CMD_NONE
)
writeb
(
cmd
,
this
->
IO_ADDR_W
);
}
static
int
at91sam9263ek_nand_ready
(
struct
mtd_info
*
mtd
)
...
...
@@ -67,11 +66,11 @@ static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
int
board_nand_init
(
struct
nand_chip
*
nand
)
{
nand
->
eccmode
=
NAND_ECC_SOFT
;
nand
->
ecc
.
mode
=
NAND_ECC_SOFT
;
#ifdef CFG_NAND_DBW_16
nand
->
options
=
NAND_BUSWIDTH_16
;
#endif
nand
->
hwcontro
l
=
at91sam9263ek_nand_hwcontrol
;
nand
->
cmd_ctr
l
=
at91sam9263ek_nand_hwcontrol
;
nand
->
dev_ready
=
at91sam9263ek_nand_ready
;
nand
->
chip_delay
=
20
;
...
...
board/atmel/at91sam9rlek/nand.c
浏览文件 @
aa5f75f2
...
...
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21)
/* our ALE is AD21 */
#define MASK_CLE (1 << 22)
/* our CLE is AD22 */
static
void
at91sam9rlek_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
)
static
void
at91sam9rlek_nand_hwcontrol
(
struct
mtd_info
*
mtd
,
int
cmd
,
unsigned
int
ctrl
)
{
struct
nand_chip
*
this
=
mtd
->
priv
;
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
switch
(
cmd
)
{
case
NAND_CTL_SETCLE
:
IO_ADDR_W
|=
MASK_CLE
;
break
;
case
NAND_CTL_SETALE
:
IO_ADDR_W
|=
MASK_ALE
;
break
;
case
NAND_CTL_CLRNCE
:
at91_set_gpio_value
(
AT91_PIN_PB6
,
1
);
break
;
case
NAND_CTL_SETNCE
:
at91_set_gpio_value
(
AT91_PIN_PB6
,
0
);
break
;
if
(
ctrl
&
NAND_CTRL_CHANGE
)
{
ulong
IO_ADDR_W
=
(
ulong
)
this
->
IO_ADDR_W
;
IO_ADDR_W
&=
~
(
MASK_ALE
|
MASK_CLE
);
if
(
ctrl
&
NAND_CLE
)
IO_ADDR_W
|=
MASK_CLE
;
if
(
ctrl
&
NAND_ALE
)
IO_ADDR_W
|=
MASK_ALE
;
at91_set_gpio_value
(
AT91_PIN_PB6
,
!
(
ctrl
&
NAND_NCE
));
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
}
this
->
IO_ADDR_W
=
(
void
*
)
IO_ADDR_W
;
if
(
cmd
!=
NAND_CMD_NONE
)
writeb
(
cmd
,
this
->
IO_ADDR_W
);
}
static
int
at91sam9rlek_nand_ready
(
struct
mtd_info
*
mtd
)
...
...
@@ -67,11 +66,11 @@ static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
int
board_nand_init
(
struct
nand_chip
*
nand
)
{
nand
->
eccmode
=
NAND_ECC_SOFT
;
nand
->
ecc
.
mode
=
NAND_ECC_SOFT
;
#ifdef CFG_NAND_DBW_16
nand
->
options
=
NAND_BUSWIDTH_16
;
#endif
nand
->
hwcontro
l
=
at91sam9rlek_nand_hwcontrol
;
nand
->
cmd_ctr
l
=
at91sam9rlek_nand_hwcontrol
;
nand
->
dev_ready
=
at91sam9rlek_nand_ready
;
nand
->
chip_delay
=
20
;
...
...
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