rockchip: rk322x: update MACRO for mmc clksel reg

The description for eMMC/SDIO/SDMMC src is not correct,
update the CRU_CLKSEL11_CON value definition according to TRM.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

arch/arm/include/asm/arch-rockchip/cru_rk322x.h

@@ -162,20 +162,17 @@ enum {
 	/* CRU_CLKSEL11_CON */
 	EMMC_PLL_SHIFT		= 12,
 	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
-	EMMC_SEL_APLL		= 0,
-	EMMC_SEL_DPLL,
+	EMMC_SEL_CPLL		= 0,
 	EMMC_SEL_GPLL,
 	EMMC_SEL_24M,
 	SDIO_PLL_SHIFT		= 10,
 	SDIO_PLL_MASK		= 3 << SDIO_PLL_SHIFT,
-	SDIO_SEL_APLL		= 0,
-	SDIO_SEL_DPLL,
+	SDIO_SEL_CPLL		= 0,
 	SDIO_SEL_GPLL,
 	SDIO_SEL_24M,
 	MMC0_PLL_SHIFT		= 8,
 	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
-	MMC0_SEL_APLL		= 0,
-	MMC0_SEL_DPLL,
+	MMC0_SEL_CPLL		= 0,
 	MMC0_SEL_GPLL,
 	MMC0_SEL_24M,
 	MMC0_DIV_SHIFT		= 0,