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提交 a732f621 编写于 作者: T Tom Rini
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m68k: Remove M54451EVB board 

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  As this is also the last in family remove the related
support as well.

Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
上级 5e770daa
展开全部 隐藏空白更改
内联 并排
Showing with 1 addition and 2254 deletion
arch/m68k/Kconfig
浏览文件 @ a732f621
......@@ -53,12 +53,6 @@ config MCF5441x
select DM_SERIAL
bool
config MCF5445x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF5227x
select OF_CONTROL
select DM
......@@ -119,10 +113,6 @@ config M54418
bool
select MCF5441x
config M54451
bool
select MCF5445x
config M52277
bool
select MCF5227x
......@@ -187,10 +177,6 @@ config TARGET_M5373EVB
bool "Support M5373EVB"
select M5373
config TARGET_M54451EVB
bool "Support M54451EVB"
select M54451
config TARGET_AMCORE
bool "Support AMCORE"
select M5307
......@@ -215,7 +201,6 @@ source "board/freescale/m5282evb/Kconfig"
source "board/freescale/m53017evb/Kconfig"
source "board/freescale/m5329evb/Kconfig"
source "board/freescale/m5373evb/Kconfig"
source "board/freescale/m54451evb/Kconfig"
source "board/sysam/amcore/Kconfig"
source "board/sysam/stmark2/Kconfig"
......
arch/m68k/Makefile
浏览文件 @ a732f621
......@@ -18,13 +18,11 @@ cpuflags-$(CONFIG_M5307) := -mcpu=5307
cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC
cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC
cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC
cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC
PLATFORM_CPPFLAGS += $(cpuflags-y)
ldflags-$(CONFIG_MCF5441x) := --got=single
ldflags-$(CONFIG_MCF5445x) := --got=single
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
......
arch/m68k/cpu/mcf5445x/cpu_init.c
浏览文件 @ a732f621
......@@ -73,13 +73,6 @@ void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
#ifdef CONFIG_MCF5445x
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN |
GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
#endif
#ifdef CONFIG_MCF5441x
pm_t *pm = (pm_t *)MMAP_PM;
......@@ -212,36 +205,6 @@ void cpu_init_f(void)
#endif
#endif /* CONFIG_MCF5441x */
#ifdef CONFIG_MCF5445x
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
out_be32(&scm1->mpr, 0x77777777);
out_be32(&scm1->pacra, 0);
out_be32(&scm1->pacrb, 0);
out_be32(&scm1->pacrc, 0);
out_be32(&scm1->pacrd, 0);
out_be32(&scm1->pacre, 0);
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
/* FlexBus */
out_8(&gpio->par_be,
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
out_8(&gpio->par_fbctl,
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#ifdef CONFIG_CF_SPI
cfspi_port_conf();
#endif
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
#endif /* CONFIG_MCF5445x */
/* FlexBus Chipselect */
init_fbcs();
......@@ -365,40 +328,6 @@ void uart_port_conf(int port)
GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
break;
#endif
#ifdef CONFIG_MCF5445x
case 0:
clrbits_8(&gpio->par_uart,
GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
setbits_8(&gpio->par_uart,
GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
#ifdef CONFIG_SYS_UART1_PRI_GPIO
clrbits_8(&gpio->par_uart,
GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
setbits_8(&gpio->par_uart,
GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
clrbits_be16(&gpio->par_ssi,
~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
setbits_be16(&gpio->par_ssi,
GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
#endif
break;
case 2:
#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
clrbits_8(&gpio->par_timer,
~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
setbits_8(&gpio->par_timer,
GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
clrbits_8(&gpio->par_timer,
~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
setbits_8(&gpio->par_timer,
GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
#endif
break;
#endif /* CONFIG_MCF5445x */
}
}
......@@ -411,46 +340,6 @@ int fecpin_setclear(fec_info_t *info, int setclear)
if (fec_get_base_addr(0, &fec0_base))
return -1;
#ifdef CONFIG_MCF5445x
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
if (info->iobase == fec0_base)
setbits_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC0_MDC0 |
GPIO_PAR_FECI2C_MDIO0_MDIO0);
else
setbits_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC1_MDC1 |
GPIO_PAR_FECI2C_MDIO1_MDIO1);
#else
setbits_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
#endif
if (info->iobase == fec0_base)
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
else
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
} else {
clrbits_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == fec0_base) {
#ifdef CONFIG_SYS_FEC_FULL_MII
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
#else
clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
#endif
} else {
#ifdef CONFIG_SYS_FEC_FULL_MII
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
#else
clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
#endif
}
}
#endif /* CONFIG_MCF5445x */
#ifdef CONFIG_MCF5441x
if (setclear) {
out_8(&gpio->par_fec, 0x03);
......
arch/m68k/cpu/mcf5445x/dspi.c
浏览文件 @ a732f621
......@@ -15,30 +15,6 @@ void dspi_chip_select(int cs)
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
break;
case 5:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
switch (cs) {
case 0:
......@@ -61,25 +37,6 @@ void dspi_chip_unselect(int cs)
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
break;
case 5:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
if (cs == 1)
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
......
arch/m68k/cpu/mcf5445x/speed.c
浏览文件 @ a732f621
......@@ -42,11 +42,6 @@ void clock_enter_limp(int lpdiv)
/* Round divider down to nearest power of two */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
#ifdef CONFIG_MCF5445x
/* Apply the divider to the system clock */
clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
#endif
/* Enable Limp Mode */
setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
}
......@@ -127,135 +122,12 @@ void setup_5441x_clocks(void)
}
#endif
#ifdef CONFIG_MCF5445x
void setup_5445x_clocks(void)
{
ccm_t *ccm = (ccm_t *)MMAP_CCM;
pll_t *pll = (pll_t *)MMAP_PLL;
int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
int pllmult_pci[] = { 12, 6, 16, 8 };
int vco = 0, temp, fbtemp, pcrvalue;
int *pPllmult = NULL;
u16 fbpll_mask;
#ifdef CONFIG_PCI
int bPci;
#endif
u8 bootmode;
/* To determine PCI is present or not */
if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
pPllmult = &pllmult_pci[0];
fbpll_mask = 3; /* 11b */
#ifdef CONFIG_PCI
bPci = 1;
#endif
} else {
pPllmult = &pllmult_nopci[0];
fbpll_mask = 7; /* 111b */
#ifdef CONFIG_PCI
gd->pci_clk = 0;
bPci = 0;
#endif
}
#ifdef CONFIG_M54451EVB
/* No external logic to read the bootmode, hard coded from built */
#ifdef CONFIG_CF_SBF
bootmode = 3;
#else
bootmode = 2;
/* default value is 16 mul, set to 20 mul */
pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
out_be32(&pll->pcr, pcrvalue);
while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
;
#endif
#endif
if (bootmode == 0) {
/* RCON mode */
vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* invaild range, re-set in PCR */
int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
int i, j, bus;
j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
for (i = j; i < 0xFF; i++) {
vco = i * CONFIG_SYS_INPUT_CLKSRC;
if (vco >= CLOCK_PLL_FVCO_MIN) {
bus = vco / temp;
if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
continue;
else
break;
}
}
pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
pcrvalue |= ((i << 24) | fbtemp);
out_be32(&pll->pcr, pcrvalue);
}
gd->arch.vco_clk = vco; /* Vco clock */
} else if (bootmode == 2) {
/* Normal mode */
vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* Default value */
pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
out_be32(&pll->pcr, pcrvalue);
vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
}
gd->arch.vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
gd->arch.vco_clk = vco; /* Vco clock */
}
if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
gd->bus_clk = vco / temp; /* bus clock */
temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
gd->arch.flb_clk = vco / temp; /* FlexBus clock */
#ifdef CONFIG_PCI
if (bPci) {
temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
gd->pci_clk = vco / temp; /* PCI clock */
}
#endif
}
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
}
#endif
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
#ifdef CONFIG_MCF5441x
setup_5441x_clocks();
#endif
#ifdef CONFIG_MCF5445x
setup_5445x_clocks();
#endif
#ifdef CONFIG_SYS_FSL_I2C
gd->arch.i2c1_clk = gd->bus_clk;
......
arch/m68k/cpu/mcf5445x/start.S
浏览文件 @ a732f621
......@@ -202,10 +202,6 @@ asm_dspi_init:
move.b #0x80, (%a2)
#endif
#ifdef CONFIG_MCF5445x
move.l #0xFC0A4063, %a0
move.b #0x7F, (%a0)
#endif
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
......@@ -214,9 +210,6 @@ asm_dspi_init:
#ifdef CONFIG_MCF5441x
move.l #0x3E000016, (%a0)
#endif
#ifdef CONFIG_MCF5445x
move.l #0x3E000011, (%a0)
#endif
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
......
arch/m68k/dts/M54451EVB.dts 已删除 100644 → 0
浏览文件 @ 5e770daa
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf5445x.dtsi"
/ {
model = "Freescale M54451EVB";
compatible = "fsl,M54451EVB";
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&dspi0 {
status = "okay";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
};
arch/m68k/dts/M54451EVB_stmicro.dts 已删除 100644 → 0
浏览文件 @ 5e770daa
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf5445x.dtsi"
/ {
model = "Freescale M54451EVB_stmicro";
compatible = "fsl,M54451EVB";
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&dspi0 {
status = "okay";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
};
arch/m68k/dts/Makefile
浏览文件 @ a732f621
......@@ -17,8 +17,6 @@ dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb
dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb
dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb
dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb
dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \
M54451EVB_stmicro.dtb
dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
......
arch/m68k/dts/mcf5445x.dtsi 已删除 100644 → 0
浏览文件 @ 5e770daa
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/ {
compatible = "fsl,mcf5445x";
aliases {
serial0 = &uart0;
spi0 = &dspi0;
fec0 = &fec0;
fec1 = &fec1;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
uart0: uart@fc060000 {
compatible = "fsl,mcf-uart";
reg = <0xfc060000 0x40>;
status = "disabled";
};
uart1: uart@fc064000 {
compatible = "fsl,mcf-uart";
reg = <0xfc064000 0x40>;
status = "disabled";
};
uart2: uart@fc068000 {
compatible = "fsl,mcf-uart";
reg = <0xfc068000 0x40>;
status = "disabled";
};
dspi0: dspi@fc05c000 {
compatible = "fsl,mcf-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfc05c000 0x100>;
spi-max-frequency = <50000000>;
num-cs = <4>;
spi-mode = <0>;
status = "disabled";
};
fec0: ethernet@fc030000 {
compatible = "fsl,mcf-fec";
reg = <0xfc030000 0x4000>;
mii-base = <0>;
max-speed = <100>;
timeout-loop = <50000>;
status = "disabled";
};
fec1: ethernet@fc034000 {
compatible = "fsl,mcf-fec";
reg = <0xfc034000 0x4000>;
mii-base = <1>;
max-speed = <100>;
timeout-loop = <50000>;
status = "disabled";
};
};
};
arch/m68k/include/asm/cache.h
浏览文件 @ a732f621
......@@ -19,9 +19,7 @@
#define CONFIG_CF_V3
#endif
#if defined(CONFIG_MCF5445x)
#define CONFIG_CF_V4
#elif defined(CONFIG_MCF5441x)
#if defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
#endif
......
arch/m68k/include/asm/immap.h
浏览文件 @ a732f621
......@@ -330,39 +330,6 @@
#endif /* CONFIG_M54418 */
#if defined(CONFIG_M54451)
#include <asm/immap_5445x.h>
#include <asm/m5445x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (6)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M54451 */
#ifdef CONFIG_M547x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
......
arch/m68k/include/asm/immap_5445x.h 已删除 100644 → 0
浏览文件 @ 5e770daa
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* MCF5445x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#ifndef __IMMAP_5445X__
#define __IMMAP_5445X__
/* Module Base Addresses */
#define MMAP_SCM1 0xFC000000
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_FEC0 0xFC030000
#define MMAP_FEC1 0xFC034000
#define MMAP_RTC 0xFC03C000
#define MMAP_SCM2 0xFC040000
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_IACK 0xFC054000
#define MMAP_I2C 0xFC058000
#define MMAP_DSPI 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_EPORT 0xFC094000
#define MMAP_WTM 0xFC098000
#define MMAP_SBF 0xFC0A0000
#define MMAP_RCM 0xFC0A0000
#define MMAP_CCM 0xFC0A0000
#define MMAP_GPIO 0xFC0A4000
#define MMAP_PCI 0xFC0A8000
#define MMAP_PCIARB 0xFC0AC000
#define MMAP_RNG 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C4000
#define MMAP_ATA 0x90000000
#define MMAP_USBHW 0xFC0B0000
#define MMAP_USBCAPS 0xFC0B0100
#define MMAP_USBEHCI 0xFC0B0140
#define MMAP_USBOTG 0xFC0B01A0
#include <asm/coldfire/ata.h>
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/ssi.h>
/* Watchdog Timer Modules (WTM) */
typedef struct wtm {
u16 wcr;
u16 wmr;
u16 wcntr;
u16 wsr;
} wtm_t;
/* Serial Boot Facility (SBF) */
typedef struct sbf {
u8 resv0[0x18];
u16 sbfsr; /* Serial Boot Facility Status Register */
u8 resv1[0x6];
u16 sbfcr; /* Serial Boot Facility Control Register */
} sbf_t;
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* Chip Configuration Module (CCM) */
typedef struct ccm {
u8 ccm_resv0[0x4];
u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
u8 resv1[0x2];
u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
u16 cir; /* Chip Identification Register (Read-only) */
u8 resv2[0x4];
u16 misccr; /* Miscellaneous Control Register */
u16 cdr; /* Clock Divider Register */
u16 uocsr; /* USB On-the-Go Controller Status Register */
} ccm_t;
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
u8 podr_fec0h; /* FEC0 High Port Output Data Register */
u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
u8 podr_ssi; /* SSI Port Output Data Register */
u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
u8 podr_dma; /* DMA Port Output Data Register */
u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
u8 resv0[0x1];
u8 podr_uart; /* UART Port Output Data Register */
u8 podr_dspi; /* DSPI Port Output Data Register */
u8 podr_timer; /* Timer Port Output Data Register */
u8 podr_pci; /* PCI Port Output Data Register */
u8 podr_usb; /* USB Port Output Data Register */
u8 podr_atah; /* ATA High Port Output Data Register */
u8 podr_atal; /* ATA Low Port Output Data Register */
u8 podr_fec1h; /* FEC1 High Port Output Data Register */
u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
u8 resv1[0x2];
u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
u8 pddr_ssi; /* SSI Port Data Direction Register */
u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
u8 pddr_dma; /* DMA Port Data Direction Register */
u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
u8 resv2[0x1];
u8 pddr_uart; /* UART Port Data Direction Register */
u8 pddr_dspi; /* DSPI Port Data Direction Register */
u8 pddr_timer; /* Timer Port Data Direction Register */
u8 pddr_pci; /* PCI Port Data Direction Register */
u8 pddr_usb; /* USB Port Data Direction Register */
u8 pddr_atah; /* ATA High Port Data Direction Register */
u8 pddr_atal; /* ATA Low Port Data Direction Register */
u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
u8 resv3[0x2];
u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
u8 resv4[0x1];
u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
u8 resv5[0x2];
u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
u8 pclrr_dma; /* DMA Port Clear Output Data Register */
u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
u8 resv6[0x1];
u8 pclrr_uart; /* UART Port Clear Output Data Register */
u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
u8 pclrr_timer; /* Timer Port Clear Output Data Register */
u8 pclrr_pci; /* PCI Port Clear Output Data Register */
u8 pclrr_usb; /* USB Port Clear Output Data Register */
u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
u8 resv7[0x2];
u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
u8 par_fec; /* FEC Pin Assignment Register */
u8 par_dma; /* DMA Pin Assignment Register */
u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
u8 par_dspi; /* DSPI Pin Assignment Register */
u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
u8 par_timer; /* Time Pin Assignment Register */
u8 par_usb; /* USB Pin Assignment Register */
u8 resv8[0x1];
u8 par_uart; /* UART Pin Assignment Register */
u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
u16 par_ssi; /* SSI Pin Assignment Register */
u16 par_ata; /* ATA Pin Assignment Register */
u8 par_irq; /* IRQ Pin Assignment Register */
u8 resv9[0x1];
u16 par_pci; /* PCI Pin Assignment Register */
u8 mscr_sdram; /* SDRAM Mode Select Control Register */
u8 mscr_pci; /* PCI Mode Select Control Register */
u8 resv10[0x2];
u8 dscr_i2c; /* I2C Drive Strength Control Register */
u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
u8 dscr_fec; /* FEC Drive Strength Control Register */
u8 dscr_uart; /* UART Drive Strength Control Register */
u8 dscr_dspi; /* DSPI Drive Strength Control Register */
u8 dscr_timer; /* TIMER Drive Strength Control Register */
u8 dscr_ssi; /* SSI Drive Strength Control Register */
u8 dscr_dma; /* DMA Drive Strength Control Register */
u8 dscr_debug; /* DEBUG Drive Strength Control Register */
u8 dscr_reset; /* RESET Drive Strength Control Register */
u8 dscr_irq; /* IRQ Drive Strength Control Register */
u8 dscr_usb; /* USB Drive Strength Control Register */
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */
u32 sdcr; /* SDRAM Control Register */
u32 sdcfg1; /* SDRAM Configuration Register 1 */
u32 sdcfg2; /* SDRAM Chip Select Register */
u8 resv0[0x100];
u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
} sdramc_t;
/* Phase Locked Loop (PLL) */
typedef struct pll {
u32 pcr; /* PLL Control Register */
u32 psr; /* PLL Status Register */
} pll_t;
typedef struct pci {
u32 idr; /* 0x00 Device Id / Vendor Id Register */
u32 scr; /* 0x04 Status / command Register */
u32 ccrir; /* 0x08 Class Code / Revision Id Register */
u32 cr1; /* 0x0c Configuration 1 Register */
u32 bar0; /* 0x10 Base address register 0 Register */
u32 bar1; /* 0x14 Base address register 1 Register */
u32 bar2; /* 0x18 Base address register 2 Register */
u32 bar3; /* 0x1c Base address register 3 Register */
u32 bar4; /* 0x20 Base address register 4 Register */
u32 bar5; /* 0x24 Base address register 5 Register */
u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
u32 erbar; /* 0x30 Expansion ROM Base Address Register */
u32 cpr; /* 0x34 Capabilities Pointer Register */
u32 rsvd1; /* 0x38 */
u32 cr2; /* 0x3c Configuration Register 2 */
u32 rsvd2[8]; /* 0x40 - 0x5f */
/* General control / status registers */
u32 gscr; /* 0x60 Global Status / Control Register */
u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
u32 tcr1; /* 0x6c Target Control 1 Register */
u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
u32 rsvd3; /* 0x7c */
u32 iwcr; /* 0x80 Initiator Window Configuration Register */
u32 icr; /* 0x84 Initiator Control Register */
u32 isr; /* 0x88 Initiator Status Register */
u32 tcr2; /* 0x8c Target Control 2 Register */
u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
u32 intr; /* 0xa8 Interrupt Register */
u32 rsvd4[19]; /* 0xac - 0xf7 */
u32 car; /* 0xf8 Configuration Address Register */
} pci_t;
typedef struct pci_arbiter {
/* Pci Arbiter Registers */
union {
u32 acr; /* Arbiter Control Register */
u32 asr; /* Arbiter Status Register */
};
} pciarb_t;
/* Register read/write struct */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege Register */
u32 rsvd1[7];
u32 pacra; /* 0x20 Peripheral Access Control Register A */
u32 pacrb; /* 0x24 Peripheral Access Control Register B */
u32 pacrc; /* 0x28 Peripheral Access Control Register C */
u32 pacrd; /* 0x2C Peripheral Access Control Register D */
u32 rsvd2[4];
u32 pacre; /* 0x40 Peripheral Access Control Register E */
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
} scm1_t;
typedef struct scm2 {
u8 rsvd1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 */
u16 rsvd2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 */
u8 rsvd3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B */
u8 rsvd4[3]; /* 0x1C - 0x1E */
u8 scmisr; /* 0x1F */
u32 rsvd5; /* 0x20 - 0x23 */
u8 bcr; /* 0x24 */
u8 rsvd6[74]; /* 0x25 - 0x6F */
u32 cfadr; /* 0x70 */
u8 rsvd7; /* 0x74 */
u8 cfier; /* 0x75 */
u8 cfloc; /* 0x76 */
u8 cfatr; /* 0x77 */
u32 rsvd8; /* 0x78 - 0x7B */
u32 cfdtr; /* 0x7C */
} scm2_t;
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5445X__ */
arch/m68k/include/asm/m5445x.h 已删除 100644 → 0
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此差异已折叠。
board/freescale/m54451evb/Kconfig 已删除 100644 → 0
浏览文件 @ 5e770daa
if TARGET_M54451EVB
config SYS_CPU
default "mcf5445x"
config SYS_BOARD
default "m54451evb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "M54451EVB"
endif
board/freescale/m54451evb/MAINTAINERS 已删除 100644 → 0
浏览文件 @ 5e770daa
M54451EVB BOARD
#M: -
S: Maintained
F: board/freescale/m54451evb/
F: include/configs/M54451EVB.h
F: configs/M54451EVB_defconfig
F: configs/M54451EVB_stmicro_defconfig
board/freescale/m54451evb/Makefile 已删除 100644 → 0
浏览文件 @ 5e770daa
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y = m54451evb.o
extra-y += sbf_dram_init.o
board/freescale/m54451evb/m54451evb.c 已删除 100644 → 0
浏览文件 @ 5e770daa
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <init.h>
#include <spi.h>
#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
/*
* need to to:
* Check serial flash size. if 2mb evb, else 8mb demo
*/
puts("Board: ");
puts("Freescale M54451 EVB\n");
return 0;
};
int dram_init(void)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
/*
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
(in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
return dramsize;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(200);
/* Issue PALL */
out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Perform two refresh cycles */
out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
/* Issue LEMR */
out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
out_be32(&sdram->sdcr,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
udelay(100);
#endif
gd->ram_size = dramsize;
return 0;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}
board/freescale/m54451evb/sbf_dram_init.S 已删除 100644 → 0
浏览文件 @ 5e770daa
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Board-specific sbf ddr/sdram init.
*
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
*/
#include <config.h>
.global sbf_dram_init
.text
sbf_dram_init:
/* Dram Initialization a1, a2, and d0 */
/* mscr sdram */
move.l #0xFC0A4074, %a1
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
nop
/* SDRAM Chip 0 and 1 */
move.l #0xFC0B8110, %a1
move.l #0xFC0B8114, %a2
/* calculate the size */
move.l #0x13, %d1
move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
#ifdef CONFIG_SYS_SDRAM_BASE1
lsr.l #1, %d2
#endif
dramsz_loop:
lsr.l #1, %d2
add.l #1, %d1
cmp.l #1, %d2
bne dramsz_loop
#ifdef CONFIG_SYS_NAND_BOOT
beq asm_nand_chk_status
#endif
/* SDRAM Chip 0 and 1 */
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
or.l %d1, (%a1)
#ifdef CONFIG_SYS_SDRAM_BASE1
move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
or.l %d1, (%a2)
#endif
nop
/* dram cfg1 and cfg2 */
move.l #0xFC0B8008, %a1
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
nop
move.l #0xFC0B800C, %a2
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
nop
move.l #0xFC0B8000, %a1 /* Mode */
move.l #0xFC0B8004, %a2 /* Ctrl */
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
move.l #1000, %d1
bsr asm_delay
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
/* Perform two refresh cycles */
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
nop
move.l %d0, (%a2)
move.l %d0, (%a2)
nop
/* Issue LEMR */
move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
nop
move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
move.l #500, %d1
bsr asm_delay
move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
and.l #0x7FFFFFFF, %d1
or.l #0x10000C00, %d1
move.l %d1, (%a2)
nop
move.l #2000, %d1
bsr asm_delay
rts
configs/M54451EVB_defconfig 已删除 100644 → 0
浏览文件 @ 5e770daa
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="M54451EVB"
CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x40000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
configs/M54451EVB_stmicro_defconfig 已删除 100644 → 0
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CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x20000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro"
CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
drivers/net/mcffec.c
浏览文件 @ a732f621
......@@ -105,17 +105,11 @@ static void set_fec_duplex_speed(volatile fec_t *fecp, int dup_spd)
}
if ((dup_spd & 0xFFFF) == _100BASET) {
#ifdef CONFIG_MCF5445x
fecp->rcr &= ~0x200; /* disabled 10T base */
#endif
#ifdef MII_DEBUG
printf("100Mbps\n");
#endif
bd->bi_ethspeed = 100;
} else {
#ifdef CONFIG_MCF5445x
fecp->rcr |= 0x200; /* enabled 10T base */
#endif
#ifdef MII_DEBUG
printf("10Mbps\n");
#endif
......
include/configs/M54451EVB.h 已删除 100644 → 0
浏览文件 @ 5e770daa
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Freescale MCF54451 EVB board.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M54451EVB_H
#define _M54451EVB_H
#include <linux/stringify.h>
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_M54451EVB /* M54451EVB board */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
#undef CONFIG_WATCHDOG
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
/* Network configuration */
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_ETHPRIME "FEC0"
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
#define CONFIG_HOSTNAME "M54451EVB"
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_SYS_LOAD_ADDR2 0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"sbfhdr=sbfhdr.bin\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${sbfhdr};" \
"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
"upd=run load; run prog\0" \
"prog=sf probe 0:1 1000000 3;" \
"sf erase 0 30000;" \
"sf write ${loadaddr} 0 30000;" \
"save\0" \
""
#else
#define CONFIG_SYS_UBOOT_END 0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#endif
/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
/* Timer */
#define CONFIG_MCFTMR
/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE 0x7
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CONFIG_PRAM 2048 /* 2048 KB */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
#define CONFIG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
#define CONFIG_SYS_SDRAM_CFG2 0x57670000
#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
#define CONFIG_SYS_SDRAM_EMOD 0x80810000
#define CONFIG_SYS_SDRAM_MODE 0x008D0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
#ifdef CONFIG_CF_SBF
# define CONFIG_SERIAL_BOOT
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
#else
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment
* Environment is not embedded in u-boot. First time runing may have env
* crc error warning if there is no correct environment on the flash.
*/
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_CHECKSUM
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
#endif
/*
* This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#ifdef CONFIG_CMD_JFFS2
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE 0x01000000
# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
CF_CACR_DEC | CF_CACR_DDCM_P | \
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/*
* CS0 - NOR Flash 16MB
* CS1 - Available
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
/* Flash */
#define CONFIG_SYS_CS0_BASE 0x00000000
#define CONFIG_SYS_CS0_MASK 0x00FF0001
#define CONFIG_SYS_CS0_CTRL 0x00004D80
#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
#endif /* _M54451EVB_H */
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