mpc512x: Adjust the DRAM init sequence to the datasheet spec
Do maintain a 200 usecs period of stable power and clock before
asserting the CKE signal and sending commands, have at least 200
DRAM clock cycles pass after initialization before data access.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Showing
想要评论请 注册 或 登录