pcnet: align rx buffers for cache invalidation
The RX buffers are invalidated when a packet is received, however they
were not suitably cache-line aligned. Allocate them seperately to the
pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure
suitable alignment for the cache invalidation, preventing anything else
being placed in the same lines & lost.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Showing
想要评论请 注册 或 登录