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体验新版 GitCode,发现更多精彩内容 >>
提交
9dbdc6eb
编写于
4月 10, 2016
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-socfpga
上级
7e8f2702
f6060ce4
变更
20
隐藏空白更改
内联
并排
Showing
20 changed file
with
129 addition
and
105 deletion
+129
-105
arch/arm/mach-socfpga/include/mach/dwmmc.h
arch/arm/mach-socfpga/include/mach/dwmmc.h
+0
-12
arch/arm/mach-socfpga/misc.c
arch/arm/mach-socfpga/misc.c
+36
-4
board/terasic/sockit/qts/iocsr_config.h
board/terasic/sockit/qts/iocsr_config.h
+58
-58
board/terasic/sockit/qts/pll_config.h
board/terasic/sockit/qts/pll_config.h
+7
-7
board/terasic/sockit/qts/sdram_config.h
board/terasic/sockit/qts/sdram_config.h
+15
-15
configs/socfpga_arria5_defconfig
configs/socfpga_arria5_defconfig
+1
-0
configs/socfpga_cyclone5_defconfig
configs/socfpga_cyclone5_defconfig
+1
-0
configs/socfpga_de0_nano_soc_defconfig
configs/socfpga_de0_nano_soc_defconfig
+1
-0
configs/socfpga_mcvevk_defconfig
configs/socfpga_mcvevk_defconfig
+1
-0
configs/socfpga_sockit_defconfig
configs/socfpga_sockit_defconfig
+1
-0
configs/socfpga_socrates_defconfig
configs/socfpga_socrates_defconfig
+1
-0
configs/socfpga_sr1500_defconfig
configs/socfpga_sr1500_defconfig
+1
-0
drivers/mmc/socfpga_dw_mmc.c
drivers/mmc/socfpga_dw_mmc.c
+0
-1
include/configs/socfpga_arria5_socdk.h
include/configs/socfpga_arria5_socdk.h
+1
-1
include/configs/socfpga_common.h
include/configs/socfpga_common.h
+0
-2
include/configs/socfpga_cyclone5_socdk.h
include/configs/socfpga_cyclone5_socdk.h
+1
-1
include/configs/socfpga_de0_nano_soc.h
include/configs/socfpga_de0_nano_soc.h
+1
-1
include/configs/socfpga_sockit.h
include/configs/socfpga_sockit.h
+1
-1
include/configs/socfpga_socrates.h
include/configs/socfpga_socrates.h
+1
-1
include/configs/socfpga_sr1500.h
include/configs/socfpga_sr1500.h
+1
-1
未找到文件。
arch/arm/mach-socfpga/include/mach/dwmmc.h
已删除
100644 → 0
浏览文件 @
7e8f2702
/*
* (C) Copyright 2013 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SOCFPGA_DWMMC_H_
#define _SOCFPGA_DWMMC_H_
int
socfpga_dwmmc_init
(
const
void
*
blob
);
#endif
/* _SOCFPGA_SDMMC_H_ */
arch/arm/mach-socfpga/misc.c
浏览文件 @
9dbdc6eb
...
...
@@ -16,7 +16,6 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/scan_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/nic301.h>
#include <asm/arch/scu.h>
#include <asm/pl310.h>
...
...
@@ -77,7 +76,8 @@ void v7_outer_cache_disable(void)
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
static
void
dwmac_deassert_reset
(
const
unsigned
int
of_reset_id
)
static
void
dwmac_deassert_reset
(
const
unsigned
int
of_reset_id
,
const
u32
phymode
)
{
u32
physhift
,
reset
;
...
...
@@ -98,16 +98,41 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id)
/* configure to PHY interface select choosed */
setbits_le32
(
&
sysmgr_regs
->
emacgrp_ctrl
,
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII
<<
physhift
);
phymode
<<
physhift
);
/* Release the EMAC controller from reset */
socfpga_per_reset
(
reset
,
0
);
}
static
u32
dwmac_phymode_to_modereg
(
const
char
*
phymode
,
u32
*
modereg
)
{
if
(
!
phymode
)
return
-
EINVAL
;
if
(
!
strcmp
(
phymode
,
"mii"
)
||
!
strcmp
(
phymode
,
"gmii"
))
{
*
modereg
=
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII
;
return
0
;
}
if
(
!
strcmp
(
phymode
,
"rgmii"
))
{
*
modereg
=
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII
;
return
0
;
}
if
(
!
strcmp
(
phymode
,
"rmii"
))
{
*
modereg
=
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII
;
return
0
;
}
return
-
EINVAL
;
}
static
int
socfpga_eth_reset
(
void
)
{
const
void
*
fdt
=
gd
->
fdt_blob
;
struct
fdtdec_phandle_args
args
;
const
char
*
phy_mode
;
u32
phy_modereg
;
int
nodes
[
2
];
/* Max. two GMACs */
int
ret
,
count
;
int
i
,
node
;
...
...
@@ -132,7 +157,14 @@ static int socfpga_eth_reset(void)
continue
;
}
dwmac_deassert_reset
(
args
.
args
[
0
]);
phy_mode
=
fdt_getprop
(
fdt
,
node
,
"phy-mode"
,
NULL
);
ret
=
dwmac_phymode_to_modereg
(
phy_mode
,
&
phy_modereg
);
if
(
ret
)
{
debug
(
"GMAC%i: Failed to parse DT 'phy-mode'!
\n
"
,
i
);
continue
;
}
dwmac_deassert_reset
(
args
.
args
[
0
],
phy_modereg
);
}
return
0
;
...
...
board/terasic/sockit/qts/iocsr_config.h
浏览文件 @
9dbdc6eb
...
...
@@ -181,17 +181,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00001000
,
0xA0000034
,
0x0D000001
,
0x
40680208
,
0x
41034051
,
0x1
248
1A00
,
0x80
208
0D0
,
0x340
514
06
,
0x01A0
2490
,
0x
08
0D0000
,
0x
51406802
,
0x0
2490
340
,
0x
E0680B2C
,
0x
20834038
,
0x1
144
1A00
,
0x80
B2C
0D0
,
0x340
38E
06
,
0x01A0
0208
,
0x
2C
0D0000
,
0x
38E0680B
,
0x0
0208
340
,
0xD000001A
,
0x0680
A28
0
,
0x0680
B2C
0
,
0x10040000
,
0x00200000
,
0x10040000
,
...
...
@@ -255,17 +255,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00001000
,
0xA0000034
,
0x0D000001
,
0x
40680208
,
0x
49034051
,
0x1
2481A02
,
0x80
A28
0D0
,
0x3403
0C
06
,
0x
E0680B2C
,
0x
20834038
,
0x1
1441A00
,
0x80
B2C
0D0
,
0x3403
8E
06
,
0x01A00040
,
0x2
8
0D0002
,
0x
5140680A
,
0x0
2490
340
,
0xD0
1248
1A
,
0x0680
A28
0
,
0x2
C
0D0002
,
0x
38E0680B
,
0x0
0208
340
,
0xD0
0104
1A
,
0x0680
B2C
0
,
0x10040000
,
0x00200000
,
0x10040000
,
...
...
@@ -330,18 +330,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D
,
0x1A041414
,
0x00D00000
,
0x
04
864000
,
0x
59647A01
,
0x
D32CA3DE
,
0xF
55145
1E
,
0x03
4CD34
8
,
0x
18
864000
,
0x
49247A06
,
0x
ABCF23D7
,
0xF
7DE79
1E
,
0x03
56E38
8
,
0x821A0000
,
0x0000D000
,
0x05
14
0680
,
0xD
669A
47A
,
0x1E
D32CA
3
,
0x
48F55
E79
,
0x0003
4C92
,
0x05
96
0680
,
0xD
7492
47A
,
0x1E
ABCF2
3
,
0x
88F7D
E79
,
0x0003
56E3
,
0x00080200
,
0x00001000
,
0x00080200
,
...
...
@@ -404,18 +404,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D
,
0x1A041414
,
0x00D00000
,
0x1
4
864000
,
0x
59647A05
,
0x
9228A3DE
,
0xF
65
E791E
,
0x03
4CD34
8
,
0x821A01
86
,
0x1
8
864000
,
0x
49247A06
,
0x
ABCF23D7
,
0xF
7D
E791E
,
0x03
56E38
8
,
0x821A01
C7
,
0x0000D000
,
0x00000680
,
0xD
669A
47A
,
0x1E
9228A
3
,
0x
48F65
E79
,
0x0003
4CD
3
,
0xD
7492
47A
,
0x1E
ABCF2
3
,
0x
88F7D
E79
,
0x0003
56E
3
,
0x00080200
,
0x00001000
,
0x00080200
,
...
...
@@ -478,18 +478,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D
,
0x1A041414
,
0x00D00000
,
0x
0C
864000
,
0x
79E47A03
,
0x
B2AAA3D1
,
0xF
55145
1E
,
0x035
CD34
8
,
0x
18
864000
,
0x
49247A06
,
0x
ABCF23D7
,
0xF
7DE79
1E
,
0x035
6E38
8
,
0x821A0000
,
0x0000D000
,
0x00000680
,
0xD
1596
47A
,
0x1E
D32CA
3
,
0x
48F55145
,
0x00035
CD
3
,
0xD
7492
47A
,
0x1E
ABCF2
3
,
0x
88F7DE79
,
0x00035
6E
3
,
0x00080200
,
0x00001000
,
0x00080200
,
...
...
@@ -552,18 +552,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F1690D
,
0x1A041414
,
0x00D00000
,
0x
04
864000
,
0x
69A47A01
,
0x
9228A3D6
,
0xF
65
E791E
,
0x03
4C924
8
,
0x
18
864000
,
0x
49247A06
,
0x
ABCF23D7
,
0xF
7D
E791E
,
0x03
56E38
8
,
0x821A0000
,
0x0000D000
,
0x00000680
,
0xD
E596
47A
,
0x1E
D32CA
3
,
0x
48F55
E79
,
0x0003
4CD
3
,
0xD
7492
47A
,
0x1E
ABCF2
3
,
0x
88F7D
E79
,
0x0003
56E
3
,
0x00080200
,
0x00001000
,
0x00080200
,
...
...
board/terasic/sockit/qts/pll_config.h
浏览文件 @
9dbdc6eb
...
...
@@ -10,13 +10,13 @@
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER
7
3
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER
6
3
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
4
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 1
4
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 1
5
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
...
...
@@ -61,7 +61,7 @@
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ 1
85
0000000
#define CONFIG_HPS_CLK_MAINVCO_HZ 1
60
0000000
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
...
...
@@ -69,7 +69,7 @@
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
#define CONFIG_HPS_CLK_NAND_HZ 50000000
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
#define CONFIG_HPS_CLK_QSPI_HZ
37
0000000
#define CONFIG_HPS_CLK_QSPI_HZ
40
0000000
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
#define CONFIG_HPS_CLK_CAN0_HZ 12500000
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
...
...
@@ -78,8 +78,8 @@
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
#define CONFIG_HPS_ALTERAGRP_MAINCLK
4
#define CONFIG_HPS_ALTERAGRP_DBGATCLK
4
#define CONFIG_HPS_ALTERAGRP_MAINCLK
3
#define CONFIG_HPS_ALTERAGRP_DBGATCLK
3
#endif
/* __SOCFPGA_PLL_CONFIG_H__ */
board/terasic/sockit/qts/sdram_config.h
浏览文件 @
9dbdc6eb
...
...
@@ -32,11 +32,11 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
7
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
11
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
...
...
@@ -46,7 +46,7 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
...
...
@@ -127,8 +127,8 @@
/* Sequencer defines configuration */
#define AFI_RATE_RATIO 1
#define CALIB_LFIFO_OFFSET
8
#define CALIB_VFIFO_OFFSET
6
#define CALIB_LFIFO_OFFSET
12
#define CALIB_VFIFO_OFFSET
10
#define ENABLE_SUPER_QUICK_CALIBRATION 0
#define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
...
...
@@ -147,7 +147,7 @@
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
#define MAX_LATENCY_COUNT_WIDTH 5
#define READ_VALID_FIFO_SIZE 16
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048
d
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048
c
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
#define RW_MGR_MEM_DATA_WIDTH 32
...
...
@@ -171,16 +171,16 @@
const
u32
ac_rom_init
[]
=
{
0x20700000
,
0x20780000
,
0x100804
3
1
,
0x100805
3
0
,
0x100900
44
,
0x100a0
00
8
,
0x100804
7
1
,
0x100805
7
0
,
0x100900
06
,
0x100a0
21
8
,
0x100b0000
,
0x10380400
,
0x100804
4
9
,
0x100804
c
8
,
0x100a00
24
,
0x10090
010
,
0x100804
6
9
,
0x100804
e
8
,
0x100a00
06
,
0x10090
218
,
0x100b0000
,
0x30780000
,
0x38780000
,
...
...
configs/socfpga_arria5_defconfig
浏览文件 @
9dbdc6eb
...
...
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
...
...
configs/socfpga_cyclone5_defconfig
浏览文件 @
9dbdc6eb
...
...
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
...
...
configs/socfpga_de0_nano_soc_defconfig
浏览文件 @
9dbdc6eb
...
...
@@ -19,6 +19,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
configs/socfpga_mcvevk_defconfig
浏览文件 @
9dbdc6eb
...
...
@@ -19,6 +19,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
configs/socfpga_sockit_defconfig
浏览文件 @
9dbdc6eb
...
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@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
...
...
configs/socfpga_socrates_defconfig
浏览文件 @
9dbdc6eb
...
...
@@ -23,6 +23,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
configs/socfpga_sr1500_defconfig
浏览文件 @
9dbdc6eb
...
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@@ -17,6 +17,7 @@ CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
...
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drivers/mmc/socfpga_dw_mmc.c
浏览文件 @
9dbdc6eb
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@@ -6,7 +6,6 @@
#include <common.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/system_manager.h>
#include <dm.h>
#include <dwmmc.h>
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include/configs/socfpga_arria5_socdk.h
浏览文件 @
9dbdc6eb
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@@ -56,7 +56,7 @@
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr=
" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
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...
include/configs/socfpga_common.h
浏览文件 @
9dbdc6eb
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@@ -93,7 +93,6 @@
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH_BAR
/*
* The base address is configurable in QSys, each board must specify the
* base address based on it's particular FPGA configuration. Please note
...
...
@@ -219,7 +218,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_BAR
/*
* Designware SPI support
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include/configs/socfpga_cyclone5_socdk.h
浏览文件 @
9dbdc6eb
...
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@@ -56,7 +56,7 @@
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr=
" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
...
...
include/configs/socfpga_de0_nano_soc.h
浏览文件 @
9dbdc6eb
...
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@@ -51,7 +51,7 @@
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=
" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
...
...
include/configs/socfpga_sockit.h
浏览文件 @
9dbdc6eb
...
...
@@ -52,7 +52,7 @@
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr=
" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
...
...
include/configs/socfpga_socrates.h
浏览文件 @
9dbdc6eb
...
...
@@ -52,7 +52,7 @@
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr=
" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
...
...
include/configs/socfpga_sr1500.h
浏览文件 @
9dbdc6eb
...
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@@ -55,7 +55,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr=
" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
...
...
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