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9bd4e591
编写于
8月 26, 2008
作者:
K
Kumar Gala
提交者:
Wolfgang Denk
8月 27, 2008
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差异文件
FSL DDR: Convert SBC8641D to new DDR code.
Signed-off-by:
N
Kumar Gala
<
galak@kernel.crashing.org
>
上级
39aa1a73
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
99 addition
and
8 deletion
+99
-8
board/sbc8641d/Makefile
board/sbc8641d/Makefile
+5
-3
board/sbc8641d/ddr.c
board/sbc8641d/ddr.c
+88
-0
board/sbc8641d/sbc8641d.c
board/sbc8641d/sbc8641d.c
+2
-3
include/configs/sbc8641d.h
include/configs/sbc8641d.h
+4
-2
未找到文件。
board/sbc8641d/Makefile
浏览文件 @
9bd4e591
...
...
@@ -25,10 +25,12 @@ include $(TOPDIR)/config.mk
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
:=
$(BOARD)
.o law.o
COBJS-y
+=
$(BOARD)
.o
COBJS-y
+=
law.o
COBJS-$(CONFIG_FSL_DDR2)
+=
ddr.o
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
SRCS
:=
$(SOBJS:.o=.S)
$
(
COBJS
-y
:.o
=
.c
)
OBJS
:=
$(
addprefix
$(obj)
,
$
(
COBJS
-y
))
SOBJS
:=
$(
addprefix
$(obj)
,
$(SOBJS)
)
$(LIB)
:
$(obj).depend $(OBJS) $(SOBJS)
...
...
board/sbc8641d/ddr.c
0 → 100644
浏览文件 @
9bd4e591
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
static
void
get_spd
(
ddr2_spd_eeprom_t
*
spd
,
unsigned
char
i2c_address
)
{
i2c_read
(
i2c_address
,
0
,
1
,
(
uchar
*
)
spd
,
sizeof
(
ddr2_spd_eeprom_t
));
}
unsigned
int
fsl_ddr_get_mem_data_rate
(
void
)
{
return
get_bus_freq
(
0
);
}
void
fsl_ddr_get_spd
(
ddr2_spd_eeprom_t
*
ctrl_dimms_spd
,
unsigned
int
ctrl_num
)
{
unsigned
int
i
;
unsigned
int
i2c_address
=
0
;
for
(
i
=
0
;
i
<
CONFIG_DIMM_SLOTS_PER_CTLR
;
i
++
)
{
if
(
ctrl_num
==
0
&&
i
==
0
)
{
i2c_address
=
SPD_EEPROM_ADDRESS1
;
}
if
(
ctrl_num
==
0
&&
i
==
1
)
{
i2c_address
=
SPD_EEPROM_ADDRESS2
;
}
if
(
ctrl_num
==
1
&&
i
==
0
)
{
i2c_address
=
SPD_EEPROM_ADDRESS3
;
}
if
(
ctrl_num
==
1
&&
i
==
1
)
{
i2c_address
=
SPD_EEPROM_ADDRESS4
;
}
get_spd
(
&
(
ctrl_dimms_spd
[
i
]),
i2c_address
);
}
}
void
fsl_ddr_board_options
(
memctl_options_t
*
popts
,
unsigned
int
ctrl_num
)
{
/*
* Factors to consider for clock adjust:
* - number of chips on bus
* - position of slot
* - DDR1 vs. DDR2?
* - ???
*
* This needs to be determined on a board-by-board basis.
* 0110 3/4 cycle late
* 0111 7/8 cycle late
*/
popts
->
clk_adjust
=
7
;
/*
* Factors to consider for CPO:
* - frequency
* - ddr1 vs. ddr2
*/
popts
->
cpo_override
=
10
;
/*
* Factors to consider for write data delay:
* - number of DIMMs
*
* 1 = 1/4 clock delay
* 2 = 1/2 clock delay
* 3 = 3/4 clock delay
* 4 = 1 clock delay
* 5 = 5/4 clock delay
* 6 = 3/2 clock delay
*/
popts
->
write_data_delay
=
3
;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts
->
half_strength_driver_enable
=
0
;
}
board/sbc8641d/sbc8641d.c
浏览文件 @
9bd4e591
...
...
@@ -34,7 +34,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/immap_fsl_pci.h>
#include <
spd
_sdram.h>
#include <
asm/fsl_ddr
_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
...
...
@@ -42,7 +42,6 @@
extern
void
ddr_enable_ecc
(
unsigned
int
dram_size
);
#endif
void
sdram_init
(
void
);
long
int
fixed_sdram
(
void
);
int
board_early_init_f
(
void
)
...
...
@@ -62,7 +61,7 @@ phys_size_t initdram (int board_type)
long
dram_size
=
0
;
#if defined(CONFIG_SPD_EEPROM)
dram_size
=
spd_sdram
();
dram_size
=
fsl_ddr_sdram
();
#else
dram_size
=
fixed_sdram
();
#endif
...
...
include/configs/sbc8641d.h
浏览文件 @
9bd4e591
...
...
@@ -61,8 +61,6 @@
#define CONFIG_HIGH_BATS 1
/* High BATs supported and enabled */
#undef CONFIG_SPD_EEPROM
/* Do not use SPD EEPROM for DDR setup*/
#undef CONFIG_DDR_DLL
/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING
/* Sets the 2T timing bit */
#undef CONFIG_DDR_ECC
/* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
...
...
@@ -114,6 +112,10 @@
#define MPC86xx_DDR_SDRAM_CLK_CNTL
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
...
...
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