arm: am33xx: Avoid writing into reserved DPLL divider
DPLL DRR doesn't have an M4 divider. But the clock driver is trying to configure M4 divider as 4(writing into a reserved register). Fixing it by making M4 divider as -1. Reported-by: NSteve Kipisz <s-kipisz2@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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