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提交 9b7993bb 编写于 作者: T Tom Rini
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m68k: Remove M5475x boards 

These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them.  As this is the last of the mcf547x_8x family of boards,
remove that support as well.

Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
上级 eb83d10b
隐藏空白更改
内联 并排
Showing with 4 addition and 2654 deletion
arch/m68k/Kconfig
浏览文件 @ 9b7993bb
......@@ -65,12 +65,6 @@ config MCF5227x
select DM_SERIAL
bool
config MCF547x_8x
select OF_CONTROL
select DM
select DM_SERIAL
bool
# processor type
config M5208
bool
......@@ -137,10 +131,6 @@ config M52277
bool
select MCF5227x
config M547x
bool
select MCF547x_8x
choice
prompt "Target select"
optional
......@@ -213,10 +203,6 @@ config TARGET_M54455EVB
bool "Support M54455EVB"
select M54455
config TARGET_M5475EVB
bool "Support M5475EVB"
select M547x
config TARGET_AMCORE
bool "Support AMCORE"
select M5307
......@@ -244,7 +230,6 @@ source "board/freescale/m5373evb/Kconfig"
source "board/freescale/m54418twr/Kconfig"
source "board/freescale/m54451evb/Kconfig"
source "board/freescale/m54455evb/Kconfig"
source "board/freescale/m547xevb/Kconfig"
source "board/sysam/amcore/Kconfig"
source "board/sysam/stmark2/Kconfig"
......
arch/m68k/Makefile
浏览文件 @ 9b7993bb
......@@ -19,14 +19,12 @@ cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC
cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC
cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC
cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC
cpuflags-$(CONFIG_MCF547x_8x) := -mcpu=5485 -fPIC
PLATFORM_CPPFLAGS += $(cpuflags-y)
ldflags-$(CONFIG_MCF5441x) := --got=single
ldflags-$(CONFIG_MCF5445x) := --got=single
ldflags-$(CONFIG_MCF547x_8x) := --got=single
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
......
arch/m68k/cpu/mcf547x_8x/Makefile 已删除 100644 → 0
浏览文件 @ eb83d10b
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o
arch/m68k/cpu/mcf547x_8x/cpu.c 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
#include <watchdog.h>
#include <command.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
out_be16(&gptmr->pre, 10);
out_be16(&gptmr->cnt, 1);
/* enable watchdog, set timeout to 0 and wait */
out_8(&gptmr->mode, GPT_TMS_SGPIO);
out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
/* we don't return! */
return 1;
};
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
siu_t *siu = (siu_t *) MMAP_SIU;
u16 id = 0;
puts("CPU: ");
switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
case 0x0C:
id = 5485;
break;
case 0x0D:
id = 5484;
break;
case 0x0E:
id = 5483;
break;
case 0x0F:
id = 5482;
break;
case 0x10:
id = 5481;
break;
case 0x11:
id = 5480;
break;
case 0x12:
id = 5475;
break;
case 0x13:
id = 5474;
break;
case 0x14:
id = 5473;
break;
case 0x15:
id = 5472;
break;
case 0x16:
id = 5471;
break;
case 0x17:
id = 5470;
break;
}
if (id) {
char buf1[32], buf2[32];
printf("Freescale MCF%d\n", id);
printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
strmhz(buf1, gd->cpu_clk),
strmhz(buf2, gd->bus_clk));
}
return 0;
};
#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_HW_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void hw_watchdog_reset(void)
{
gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
out_8(&gptmr->ocpw, 0xa5);
}
int watchdog_disable(void)
{
gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
out_8(&gptmr->mode, 0);
out_8(&gptmr->ctrl, 0);
puts("WATCHDOG:disabled\n");
return (0);
}
int watchdog_init(void)
{
gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
out_8(&gptmr->mode, GPT_TMS_SGPIO);
out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
puts("WATCHDOG:enabled\n");
return (0);
}
#endif /* CONFIG_HW_WATCHDOG */
#if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
* int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FSLDMAFEC)
mcdmafec_initialize(bis);
#endif
#if defined(CONFIG_MCFFEC)
mcffec_initialize(bis);
#endif
return 0;
}
#endif
arch/m68k/cpu/mcf547x_8x/cpu_init.c 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <MCD_dma.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/immap.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#include <asm/fsl_mcdmafec.h>
#endif
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
out_be32(&xlbarb->adrto, 0x2000);
out_be32(&xlbarb->datto, 0x2500);
out_be32(&xlbarb->busto, 0x3000);
out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
/* Master Priority Enable */
out_be32(&xlbarb->prien, 0xff);
out_be32(&xlbarb->pri, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_SYS_I2C_FSL
out_be16(&gpio->par_feci2cirq,
GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
#endif
icache_enable();
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r(void)
{
#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
MCD_RELOC_TASKS);
#endif
return (0);
}
void uart_port_conf(int port)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
/* Setup Ports: */
switch (port) {
case 0:
out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
break;
case 1:
out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
break;
case 2:
out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
break;
case 3:
out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
break;
}
clrbits_8(pscsicr, 0x07);
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u32 fec0_base;
if (fec_get_base_addr(0, &fec0_base))
return -1;
if (setclear) {
if (info->iobase == fec0_base)
setbits_be16(&gpio->par_feci2cirq, 0xf000);
else
setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
} else {
if (info->iobase == fec0_base)
clrbits_be16(&gpio->par_feci2cirq, 0xf000);
else
clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
}
return 0;
}
#endif
arch/m68k/cpu/mcf547x_8x/interrupts.c 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
/* CPU specific interrupt routine */
#include <common.h>
#include <irq_func.h>
#include <asm/immap.h>
#include <asm/io.h>
int interrupt_init(void)
{
int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
setbits_be32(&intp->imrh0, 0xffffffff);
setbits_be32(&intp->imrl0, 0xffffffff);
enable_interrupts();
return 0;
}
#if defined(CONFIG_SLTTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
}
#endif
arch/m68k/cpu/mcf547x_8x/pci.c 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
/*
* PCI Configuration space access support
*/
#include <common.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/immap.h>
#include <linux/delay.h>
#if defined(CONFIG_PCI)
/* System RAM mapped over PCI */
#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#define cfg_read(val, addr, type, op) *val = op((type)(addr));
#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
#define PCI_OP(rw, size, type, op, mask) \
int pci_##rw##_cfg_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
u32 addr = 0; \
u16 cfg_type = 0; \
addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
out_be32(hose->cfg_addr, addr); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
__asm__ __volatile__("nop"); \
__asm__ __volatile__("nop"); \
out_be32(hose->cfg_addr, addr & 0x7fffffff); \
return 0; \
}
PCI_OP(read, byte, u8 *, in_8, 3)
PCI_OP(read, word, u16 *, in_le16, 2)
PCI_OP(write, byte, u8, out_8, 3)
PCI_OP(write, word, u16, out_le16, 2)
PCI_OP(write, dword, u32, out_le32, 0)
int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
int offset, u32 * val)
{
u32 addr;
u32 tmpv;
u32 mask = 2; /* word access */
/* Read lower 16 bits */
addr = ((offset & 0xfc) | (dev) | 0x80000000);
out_be32(hose->cfg_addr, addr);
*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
__asm__ __volatile__("nop");
out_be32(hose->cfg_addr, addr & 0x7fffffff);
/* Read upper 16 bits */
offset += 2;
addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
out_be32(hose->cfg_addr, addr);
tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
__asm__ __volatile__("nop");
out_be32(hose->cfg_addr, addr & 0x7fffffff);
/* combine results into dword value */
*val = (tmpv << 16) | *val;
return 0;
}
void pci_mcf547x_8x_init(struct pci_controller *hose)
{
pci_t *pci = (pci_t *) MMAP_PCI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Port configuration */
out_be16(&gpio->par_pcibg,
GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
GPIO_PAR_PCIBG_PCIBG4(3));
out_be16(&gpio->par_pcibr,
GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
GPIO_PAR_PCIBR_PCIBR4(3));
/* Assert reset bit */
setbits_be32(&pci->gscr, PCI_GSCR_PR);
out_be32(&pci->tcr1, PCI_TCR1_P);
/* Initiator windows */
out_be32(&pci->iw0btar,
CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
out_be32(&pci->iw1btar,
CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
out_be32(&pci->iw2btar,
CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
out_be32(&pci->iwcr,
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
out_be32(&pci->icr, 0);
/* Enable bus master and mem access */
out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
/* Cache line size and master latency */
out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
out_be32(&pci->cr2, 0);
#ifdef CONFIG_SYS_PCI_BAR0
out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
#endif
#ifdef CONFIG_SYS_PCI_BAR1
out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
#endif
/* Deassert reset bit */
clrbits_be32(&pci->gscr, PCI_GSCR_PR);
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI */
arch/m68k/cpu/mcf547x_8x/slicetimer.c 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <init.h>
#include <irq_func.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/timer.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
static ulong timestamp;
#if defined(CONFIG_SLTTMR)
#ifndef CONFIG_SYS_UDELAY_BASE
# error "uDelay base not defined!"
#endif
#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
#endif
extern void dtimer_intr_setup(void);
void __udelay(unsigned long usec)
{
slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
u32 now, freq;
/* 1 us period */
freq = CONFIG_SYS_TIMER_PRESCALER;
/* Disable */
out_be32(&timerp->cr, 0);
out_be32(&timerp->tcnt, usec * freq);
out_be32(&timerp->cr, SLT_CR_TEN);
now = in_be32(&timerp->cnt);
while (now != 0)
now = in_be32(&timerp->cnt);
setbits_be32(&timerp->sr, SLT_SR_ST);
out_be32(&timerp->cr, 0);
}
void dtimer_interrupt(void *not_used)
{
slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
/* check for timer interrupt asserted */
if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
setbits_be32(&timerp->sr, SLT_SR_ST);
timestamp++;
return;
}
}
int timer_init(void)
{
slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
timestamp = 0;
/* disable timer */
out_be32(&timerp->cr, 0);
out_be32(&timerp->tcnt, 0);
/* clear status */
out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
/* initialize and enable timer interrupt */
irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
/* Interrupt every ms */
out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
dtimer_intr_setup();
/* set a period of 1us, set timer mode to restart and
enable timer and interrupt */
out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
return 0;
}
ulong get_timer(ulong base)
{
return (timestamp - base);
}
#endif /* CONFIG_SLTTMR */
arch/m68k/cpu/mcf547x_8x/speed.c 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
int get_clocks(void)
{
gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
return (0);
}
arch/m68k/cpu/mcf547x_8x/start.S 已删除 100644 → 0
浏览文件 @ eb83d10b
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include "version.h"
#include <asm/cache.h>
#define _START _start
#define _FAULT _fault
#define SAVE_ALL \
move.w #0x2700,%sr; /* disable intrs */ \
subl #60,%sp; /* space for 15 regs */ \
moveml %d0-%d7/%a0-%a6,%sp@;
#define RESTORE_ALL \
moveml %sp@,%d0-%d7/%a0-%a6; \
addl #60,%sp; /* space for 15 regs */ \
rte;
.text
/*
* Vector table. This is used for initial platform startup.
* These vectors are to catch any un-intended traps.
*/
_vectors:
INITSP: .long 0x00000000 /* Initial SP */
INITPC: .long _START /* Initial PC */
vector02_0F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector10_17:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector18_1F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector30_3F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector64_127:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector128_191:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.text
.globl _start
_start:
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR0
move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
movec %d0, %RAMBAR1
move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */
move.c %d0, %MBAR
/* invalidate and disable cache */
move.l #0x01040100, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
movec %d0, %ACR2
movec %d0, %ACR3
/* initialize general use internal ram */
move.l #0, %d0
move.l #(ICACHE_STATUS), %a1 /* icache */
move.l #(DCACHE_STATUS), %a2 /* icache */
move.l %d0, (%a1)
move.l %d0, (%a2)
/* put relocation table address to a5 */
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
* then (and always) gd struct space will be reserved
*/
move.l %sp, -(%sp)
move.l #board_init_f_alloc_reserve, %a1
jsr (%a1)
/* update stack and frame-pointers */
move.l %d0, %sp
move.l %sp, %fp
/* initialize reserved area */
move.l %d0, -(%sp)
move.l #board_init_f_init_reserve, %a1
jsr (%a1)
/* run low-level CPU init code (from flash) */
jbsr cpu_init_f
/* run low-level board init code (from flash) */
clr.l %sp@-
jbsr board_init_f
/* board_init_f() does not return */
/******************************************************************************/
/*
* void relocate_code(addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
link.w %a6,#0
move.l 8(%a6), %sp /* set new stack pointer */
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
cmp.l %a1,%a2
bgt.s 1b
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
bgt.s 6b
/*
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
sub.l #_start,%d1
add.l %a0,%d1
move.l %d1,(%a1)+
cmp.l %a2, %a1
bne 7b
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
jsr (%a1)
/******************************************************************************/
/* exception code */
.globl _fault
_fault:
bra _fault
.globl _exc_handler
_exc_handler:
SAVE_ALL
movel %sp,%sp@-
bsr exc_handler
addql #4,%sp
RESTORE_ALL
.globl _int_handler
_int_handler:
SAVE_ALL
movel %sp,%sp@-
bsr int_handler
addql #4,%sp
RESTORE_ALL
/******************************************************************************/
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
arch/m68k/dts/M5475AFE.dts 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475AFE";
compatible = "fsl,M5475AFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475BFE.dts 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475BFE";
compatible = "fsl,M5475BFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475CFE.dts 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475CFE";
compatible = "fsl,M5475CFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475DFE.dts 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475DFE";
compatible = "fsl,M5475DFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475EFE.dts 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475EFE";
compatible = "fsl,M5475EFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475FFE.dts 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475FFE";
compatible = "fsl,M5475FFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475GFE.dts 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475GFE";
compatible = "fsl,M5475GFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/Makefile
浏览文件 @ 9b7993bb
......@@ -32,13 +32,6 @@ dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
M54455EVB_i66.dtb
dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
M5475BFE.dtb \
M5475CFE.dtb \
M5475DFE.dtb \
M5475EFE.dtb \
M5475FFE.dtb \
M5475GFE.dtb
targets += $(dtb-y)
......
arch/m68k/include/asm/cache.h
浏览文件 @ 9b7993bb
......@@ -19,7 +19,7 @@
#define CONFIG_CF_V3
#endif
#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
#if defined(CONFIG_MCF5445x)
#define CONFIG_CF_V4
#elif defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
......
arch/m68k/include/asm/coldfire/dspi.h
浏览文件 @ 9b7993bb
......@@ -20,14 +20,8 @@ typedef struct dspi {
u32 tfr; /* 0x34 - PUSHR */
u16 resv1; /* 0x38 */
u16 rfr; /* 0x3A - POPR */
#ifdef CONFIG_MCF547x_8x
u32 tfdr[4]; /* 0x3C */
u8 resv2[0x30]; /* 0x40 */
u32 rfdr[4]; /* 0x7C */
#else
u32 tfdr[16]; /* 0x3C */
u32 rfdr[16]; /* 0x7C */
#endif
} dspi_t;
/* Module configuration */
......
arch/m68k/include/asm/coldfire/eport.h
浏览文件 @ 9b7993bb
......@@ -11,18 +11,6 @@
/* Edge Port Module (EPORT) */
typedef struct eport {
#ifdef CONFIG_MCF547x_8x
u16 par; /* 0x00 */
u16 res0; /* 0x02 */
u8 ddr; /* 0x04 */
u8 ier; /* 0x05 */
u16 res1; /* 0x06 */
u8 dr; /* 0x08 */
u8 pdr; /* 0x09 */
u16 res2; /* 0x0A */
u8 fr; /* 0x0C */
u8 res3[3]; /* 0x0D */
#else
u16 par; /* 0x00 Pin Assignment */
u8 ddr; /* 0x02 Data Direction */
u8 ier; /* 0x03 Interrupt Enable */
......@@ -30,7 +18,6 @@ typedef struct eport {
u8 pdr; /* 0x05 Pin Data */
u8 fr; /* 0x06 Flag */
u8 res0;
#endif
} eport_t;
/* EPPAR */
......
arch/m68k/include/asm/fec.h
浏览文件 @ 9b7993bb
......@@ -337,13 +337,8 @@ typedef struct fec {
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
#ifdef CONFIG_MCF547x_8x
typedef struct fec_info_dma fec_info_t;
#define FEC_T fecdma_t
#else
typedef struct fec_info_s fec_info_t;
#define FEC_T fec_t
#endif
int fecpin_setclear(fec_info_t *info, int setclear);
int mii_discover_phy(fec_info_t *info);
......
arch/m68k/include/asm/immap_547x_8x.h 已删除 100644 → 0
浏览文件 @ eb83d10b
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* MCF547x_8x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#ifndef __IMMAP_547x_8x__
#define __IMMAP_547x_8x__
#define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700)
#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800)
#define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900)
#define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00)
#define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00)
#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00)
#define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00)
#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00)
#define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00)
#define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000)
#define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800)
#define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900)
#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00)
#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000)
#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800)
#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000)
#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800)
#define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000)
#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000)
#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00)
#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000)
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
typedef struct siu {
u32 mbar; /* 0x00 */
u32 drv; /* 0x04 */
u32 rsvd1[2]; /* 0x08 - 0x1F */
u32 sbcr; /* 0x10 */
u32 rsvd2[3]; /* 0x14 - 0x1F */
u32 cs0cfg; /* 0x20 */
u32 cs1cfg; /* 0x24 */
u32 cs2cfg; /* 0x28 */
u32 cs3cfg; /* 0x2C */
u32 rsvd3[2]; /* 0x30 - 0x37 */
u32 secsacr; /* 0x38 */
u32 rsvd4[2]; /* 0x3C - 0x43 */
u32 rsr; /* 0x44 */
u32 rsvd5[2]; /* 0x48 - 0x4F */
u32 jtagid; /* 0x50 */
} siu_t;
typedef struct sdram {
u32 mode; /* 0x00 */
u32 ctrl; /* 0x04 */
u32 cfg1; /* 0x08 */
u32 cfg2; /* 0x0c */
} sdram_t;
typedef struct xlb_arb {
u32 cfg; /* 0x240 */
u32 ver; /* 0x244 */
u32 sr; /* 0x248 */
u32 imr; /* 0x24c */
u32 adrcap; /* 0x250 */
u32 sigcap; /* 0x254 */
u32 adrto; /* 0x258 */
u32 datto; /* 0x25c */
u32 busto; /* 0x260 */
u32 prien; /* 0x264 */
u32 pri; /* 0x268 */
} xlbarb_t;
typedef struct gptmr {
u8 ocpw;
u8 octict;
u8 ctrl;
u8 mode;
u16 pre; /* Prescale */
u16 cnt;
u16 pwmwidth;
u8 pwmop; /* Output Polarity */
u8 pwmld; /* Immediate Update */
u16 cap; /* Capture internal counter */
u8 ovfpin; /* Ovf and Pin */
u8 intr; /* Interrupts */
} gptmr_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
typedef struct slt {
u32 tcnt; /* 0x00 */
u32 cr; /* 0x04 */
u32 cnt; /* 0x08 */
u32 sr; /* 0x0C */
} slt_t;
typedef struct gpio {
/* Port Output Data Registers */
u8 podr_fbctl; /*0x00 */
u8 podr_fbcs; /*0x01 */
u8 podr_dma; /*0x02 */
u8 rsvd1; /*0x03 */
u8 podr_fec0h; /*0x04 */
u8 podr_fec0l; /*0x05 */
u8 podr_fec1h; /*0x06 */
u8 podr_fec1l; /*0x07 */
u8 podr_feci2c; /*0x08 */
u8 podr_pcibg; /*0x09 */
u8 podr_pcibr; /*0x0A */
u8 rsvd2; /*0x0B */
u8 podr_psc3psc2; /*0x0C */
u8 podr_psc1psc0; /*0x0D */
u8 podr_dspi; /*0x0E */
u8 rsvd3; /*0x0F */
/* Port Data Direction Registers */
u8 pddr_fbctl; /*0x10 */
u8 pddr_fbcs; /*0x11 */
u8 pddr_dma; /*0x12 */
u8 rsvd4; /*0x13 */
u8 pddr_fec0h; /*0x14 */
u8 pddr_fec0l; /*0x15 */
u8 pddr_fec1h; /*0x16 */
u8 pddr_fec1l; /*0x17 */
u8 pddr_feci2c; /*0x18 */
u8 pddr_pcibg; /*0x19 */
u8 pddr_pcibr; /*0x1A */
u8 rsvd5; /*0x1B */
u8 pddr_psc3psc2; /*0x1C */
u8 pddr_psc1psc0; /*0x1D */
u8 pddr_dspi; /*0x1E */
u8 rsvd6; /*0x1F */
/* Port Pin Data/Set Data Registers */
u8 ppdsdr_fbctl; /*0x20 */
u8 ppdsdr_fbcs; /*0x21 */
u8 ppdsdr_dma; /*0x22 */
u8 rsvd7; /*0x23 */
u8 ppdsdr_fec0h; /*0x24 */
u8 ppdsdr_fec0l; /*0x25 */
u8 ppdsdr_fec1h; /*0x26 */
u8 ppdsdr_fec1l; /*0x27 */
u8 ppdsdr_feci2c; /*0x28 */
u8 ppdsdr_pcibg; /*0x29 */
u8 ppdsdr_pcibr; /*0x2A */
u8 rsvd8; /*0x2B */
u8 ppdsdr_psc3psc2; /*0x2C */
u8 ppdsdr_psc1psc0; /*0x2D */
u8 ppdsdr_dspi; /*0x2E */
u8 rsvd9; /*0x2F */
/* Port Clear Output Data Registers */
u8 pclrr_fbctl; /*0x30 */
u8 pclrr_fbcs; /*0x31 */
u8 pclrr_dma; /*0x32 */
u8 rsvd10; /*0x33 */
u8 pclrr_fec0h; /*0x34 */
u8 pclrr_fec0l; /*0x35 */
u8 pclrr_fec1h; /*0x36 */
u8 pclrr_fec1l; /*0x37 */
u8 pclrr_feci2c; /*0x38 */
u8 pclrr_pcibg; /*0x39 */
u8 pclrr_pcibr; /*0x3A */
u8 rsvd11; /*0x3B */
u8 pclrr_psc3psc2; /*0x3C */
u8 pclrr_psc1psc0; /*0x3D */
u8 pclrr_dspi; /*0x3E */
u8 rsvd12; /*0x3F */
/* Pin Assignment Registers */
u16 par_fbctl; /*0x40 */
u8 par_fbcs; /*0x42 */
u8 par_dma; /*0x43 */
u16 par_feci2cirq; /*0x44 */
u16 rsvd13; /*0x46 */
u16 par_pcibg; /*0x48 */
u16 par_pcibr; /*0x4A */
u8 par_psc3; /*0x4C */
u8 par_psc2; /*0x4D */
u8 par_psc1; /*0x4E */
u8 par_psc0; /*0x4F */
u16 par_dspi; /*0x50 */
u8 par_timer; /*0x52 */
u8 rsvd14; /*0x53 */
} gpio_t;
typedef struct pci {
u32 idr; /* 0x00 Device Id / Vendor Id */
u32 scr; /* 0x04 Status / command */
u32 ccrir; /* 0x08 Class Code / Revision Id */
u32 cr1; /* 0x0c Configuration 1 */
u32 bar0; /* 0x10 Base address register 0 */
u32 bar1; /* 0x14 Base address register 1 */
u32 bar2; /* 0x18 NA */
u32 bar3; /* 0x1c NA */
u32 bar4; /* 0x20 NA */
u32 bar5; /* 0x24 NA */
u32 ccpr; /* 0x28 Cardbus CIS Pointer */
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */
u32 erbar; /* 0x30 Expansion ROM Base Address */
u32 cpr; /* 0x34 Capabilities Pointer */
u32 rsvd1; /* 0x38 */
u32 cr2; /* 0x3c Configuration 2 */
u32 rsvd2[8]; /* 0x40 - 0x5f */
/* General control / status registers */
u32 gscr; /* 0x60 Global Status / Control */
u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */
u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */
u32 tcr1; /* 0x6c Target Control 1 Register */
u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */
u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */
u32 iw2btar; /* 0x78 NA */
u32 rsvd3; /* 0x7c */
u32 iwcr; /* 0x80 Initiator Window Configuration */
u32 icr; /* 0x84 Initiator Control */
u32 isr; /* 0x88 Initiator Status */
u32 tcr2; /* 0x8c NA */
u32 tbatr0; /* 0x90 NA */
u32 tbatr1; /* 0x94 NA */
u32 tbatr2; /* 0x98 NA */
u32 tbatr3; /* 0x9c NA */
u32 tbatr4; /* 0xa0 NA */
u32 tbatr5; /* 0xa4 NA */
u32 intr; /* 0xa8 NA */
u32 rsvd4[19]; /* 0xac - 0xf7 */
u32 car; /* 0xf8 Configuration Address */
} pci_t;
typedef struct pci_arbiter {
/* Pci Arbiter Registers */
union {
u32 acr; /* Arbiter Control */
u32 asr; /* Arbiter Status */
};
} pciarb_t;
#endif /* __IMMAP_547x_8x__ */
arch/m68k/include/asm/m547x_8x.h 已删除 100644 → 0
浏览文件 @ eb83d10b
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#ifndef mcf547x_8x_h
#define mcf547x_8x_h
/*********************************************************************
* XLB Arbiter (XLB)
*********************************************************************/
/* Bit definitions and macros for XARB_CFG */
#define XARB_CFG_AT (0x00000002)
#define XARB_CFG_DT (0x00000004)
#define XARB_CFG_BA (0x00000008)
#define XARB_CFG_PM(x) (((x)&0x00000003)<<5)
#define XARB_CFG_SP(x) (((x)&0x00000007)<<8)
#define XARB_CFG_PLDIS (0x80000000)
/* Bit definitions and macros for XARB_SR */
#define XARB_SR_AT (0x00000001)
#define XARB_SR_DT (0x00000002)
#define XARB_SR_BA (0x00000004)
#define XARB_SR_TTM (0x00000008)
#define XARB_SR_ECW (0x00000010)
#define XARB_SR_TTR (0x00000020)
#define XARB_SR_TTA (0x00000040)
#define XARB_SR_MM (0x00000080)
#define XARB_SR_SEA (0x00000100)
/* Bit definitions and macros for XARB_IMR */
#define XARB_IMR_ATE (0x00000001)
#define XARB_IMR_DTE (0x00000002)
#define XARB_IMR_BAE (0x00000004)
#define XARB_IMR_TTME (0x00000008)
#define XARB_IMR_ECWE (0x00000010)
#define XARB_IMR_TTRE (0x00000020)
#define XARB_IMR_TTAE (0x00000040)
#define XARB_IMR_MME (0x00000080)
#define XARB_IMR_SEAE (0x00000100)
/* Bit definitions and macros for XARB_SIGCAP */
#define XARB_SIGCAP_TT(x) ((x)&0x0000001F)
#define XARB_SIGCAP_TBST (0x00000020)
#define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7)
/* Bit definitions and macros for XARB_PRIEN */
#define XARB_PRIEN_M0 (0x00000001)
#define XARB_PRIEN_M2 (0x00000004)
#define XARB_PRIEN_M3 (0x00000008)
/* Bit definitions and macros for XARB_PRI */
#define XARB_PRI_M0P(x) (((x)&0x00000007)<<0)
#define XARB_PRI_M2P(x) (((x)&0x00000007)<<8)
#define XARB_PRI_M3P(x) (((x)&0x00000007)<<12)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
/* Bit definitions and macros for GPIO_PAR_FBCTL */
#define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0)
#define GPIO_PAR_FBCTL_TA (0x0004)
#define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4)
#define GPIO_PAR_FBCTL_OE (0x0040)
#define GPIO_PAR_FBCTL_BWE0 (0x0100)
#define GPIO_PAR_FBCTL_BWE1 (0x0400)
#define GPIO_PAR_FBCTL_BWE2 (0x1000)
#define GPIO_PAR_FBCTL_BWE3 (0x4000)
#define GPIO_PAR_FBCTL_TS_GPIO (0)
#define GPIO_PAR_FBCTL_TS_TBST (2)
#define GPIO_PAR_FBCTL_TS_TS (3)
#define GPIO_PAR_FBCTL_RWB_GPIO (0x0000)
#define GPIO_PAR_FBCTL_RWB_TBST (0x0020)
#define GPIO_PAR_FBCTL_RWB_RWB (0x0030)
/* Bit definitions and macros for GPIO_PAR_FBCS */
#define GPIO_PAR_FBCS_CS1 (0x02)
#define GPIO_PAR_FBCS_CS2 (0x04)
#define GPIO_PAR_FBCS_CS3 (0x08)
#define GPIO_PAR_FBCS_CS4 (0x10)
#define GPIO_PAR_FBCS_CS5 (0x20)
/* Bit definitions and macros for GPIO_PAR_DMA */
#define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0)
#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2)
#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4)
#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
#define GPIO_PAR_DMA_DACKx_GPIO (0)
#define GPIO_PAR_DMA_DACKx_TOUT (2)
#define GPIO_PAR_DMA_DACKx_DACK (3)
#define GPIO_PAR_DMA_DREQx_GPIO (0)
#define GPIO_PAR_DMA_DREQx_TIN (2)
#define GPIO_PAR_DMA_DREQx_DREQ (3)
/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
#define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001)
#define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002)
#define GPIO_PAR_FECI2CIRQ_SCL (0x0004)
#define GPIO_PAR_FECI2CIRQ_SDA (0x0008)
#define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6)
#define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8)
#define GPIO_PAR_FECI2CIRQ_E1MII (0x0400)
#define GPIO_PAR_FECI2CIRQ_E17 (0x0800)
#define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000)
#define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000)
#define GPIO_PAR_FECI2CIRQ_E0MII (0x4000)
#define GPIO_PAR_FECI2CIRQ_E07 (0x8000)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300)
#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000)
#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080)
#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0)
/* Bit definitions and macros for GPIO_PAR_PCIBG */
#define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0)
#define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2)
#define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4)
#define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6)
#define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for GPIO_PAR_PCIBR */
#define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0)
#define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2)
#define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4)
#define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6)
#define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for GPIO_PAR_PSC3 */
#define GPIO_PAR_PSC3_TXD3 (0x04)
#define GPIO_PAR_PSC3_RXD3 (0x08)
#define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC3_CTS3_GPIO (0x00)
#define GPIO_PAR_PSC3_CTS3_BCLK (0x80)
#define GPIO_PAR_PSC3_CTS3_CTS (0xC0)
#define GPIO_PAR_PSC3_RTS3_GPIO (0x00)
#define GPIO_PAR_PSC3_RTS3_FSYNC (0x20)
#define GPIO_PAR_PSC3_RTS3_RTS (0x30)
#define GPIO_PAR_PSC3_CTS2_CANRX (0x40)
/* Bit definitions and macros for GPIO_PAR_PSC2 */
#define GPIO_PAR_PSC2_TXD2 (0x04)
#define GPIO_PAR_PSC2_RXD2 (0x08)
#define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC2_CTS2_GPIO (0x00)
#define GPIO_PAR_PSC2_CTS2_BCLK (0x80)
#define GPIO_PAR_PSC2_CTS2_CTS (0xC0)
#define GPIO_PAR_PSC2_RTS2_GPIO (0x00)
#define GPIO_PAR_PSC2_RTS2_CANTX (0x10)
#define GPIO_PAR_PSC2_RTS2_FSYNC (0x20)
#define GPIO_PAR_PSC2_RTS2_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_PSC1 */
#define GPIO_PAR_PSC1_TXD1 (0x04)
#define GPIO_PAR_PSC1_RXD1 (0x08)
#define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC1_CTS1_GPIO (0x00)
#define GPIO_PAR_PSC1_CTS1_BCLK (0x80)
#define GPIO_PAR_PSC1_CTS1_CTS (0xC0)
#define GPIO_PAR_PSC1_RTS1_GPIO (0x00)
#define GPIO_PAR_PSC1_RTS1_FSYNC (0x20)
#define GPIO_PAR_PSC1_RTS1_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_PSC0 */
#define GPIO_PAR_PSC0_TXD0 (0x04)
#define GPIO_PAR_PSC0_RXD0 (0x08)
#define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC0_CTS0_GPIO (0x00)
#define GPIO_PAR_PSC0_CTS0_BCLK (0x80)
#define GPIO_PAR_PSC0_CTS0_CTS (0xC0)
#define GPIO_PAR_PSC0_RTS0_GPIO (0x00)
#define GPIO_PAR_PSC0_RTS0_FSYNC (0x20)
#define GPIO_PAR_PSC0_RTS0_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_DSPI */
#define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0)
#define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2)
#define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4)
#define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6)
#define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8)
#define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10)
#define GPIO_PAR_DSPI_CS5 (0x1000)
#define GPIO_PAR_DSPI_CS3_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS3_CANTX (0x0400)
#define GPIO_PAR_DSPI_CS3_TOUT (0x0800)
#define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00)
#define GPIO_PAR_DSPI_CS2_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS2_CANTX (0x0100)
#define GPIO_PAR_DSPI_CS2_TOUT (0x0200)
#define GPIO_PAR_DSPI_CS2_DSPICS (0x0300)
#define GPIO_PAR_DSPI_CS0_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS0_FSYNC (0x0040)
#define GPIO_PAR_DSPI_CS0_RTS (0x0080)
#define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0)
#define GPIO_PAR_DSPI_SCK_GPIO (0x0000)
#define GPIO_PAR_DSPI_SCK_BCLK (0x0010)
#define GPIO_PAR_DSPI_SCK_CTS (0x0020)
#define GPIO_PAR_DSPI_SCK_SCK (0x0030)
#define GPIO_PAR_DSPI_SIN_GPIO (0x0000)
#define GPIO_PAR_DSPI_SIN_RXD (0x0008)
#define GPIO_PAR_DSPI_SIN_SIN (0x000C)
#define GPIO_PAR_DSPI_SOUT_GPIO (0x0000)
#define GPIO_PAR_DSPI_SOUT_TXD (0x0002)
#define GPIO_PAR_DSPI_SOUT_SOUT (0x0003)
/* Bit definitions and macros for GPIO_PAR_TIMER */
#define GPIO_PAR_TIMER_TOUT2 (0x01)
#define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1)
#define GPIO_PAR_TIMER_TOUT3 (0x08)
#define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4)
#define GPIO_PAR_TIMER_TIN3_CANRX (0x00)
#define GPIO_PAR_TIMER_TIN3_IRQ (0x20)
#define GPIO_PAR_TIMER_TIN3_TIN (0x30)
#define GPIO_PAR_TIMER_TIN2_CANRX (0x00)
#define GPIO_PAR_TIMER_TIN2_IRQ (0x04)
#define GPIO_PAR_TIMER_TIN2_TIN (0x06)
/*********************************************************************
* Slice Timer (SLT)
*********************************************************************/
#define SLT_CR_RUN (0x04000000)
#define SLT_CR_IEN (0x02000000)
#define SLT_CR_TEN (0x01000000)
#define SLT_SR_BE (0x02000000)
#define SLT_SR_ST (0x01000000)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EP0ISR (15)
#define INT0_LO_EP1ISR (16)
#define INT0_LO_EP2ISR (17)
#define INT0_LO_EP3ISR (18)
#define INT0_LO_EP4ISR (19)
#define INT0_LO_EP5ISR (20)
#define INT0_LO_EP6ISR (21)
#define INT0_LO_USBISR (22)
#define INT0_LO_USBAISR (23)
#define INT0_LO_USB (24)
#define INT1_LO_DSPI_RFOF_TFUF (25)
#define INT1_LO_DSPI_RFOF (26)
#define INT1_LO_DSPI_RFDF (27)
#define INT1_LO_DSPI_TFUF (28)
#define INT1_LO_DSPI_TCF (29)
#define INT1_LO_DSPI_TFFF (30)
#define INT1_LO_DSPI_EOQF (31)
#define INT0_HI_UART3 (32)
#define INT0_HI_UART2 (33)
#define INT0_HI_UART1 (34)
#define INT0_HI_UART0 (35)
#define INT0_HI_COMMTIM_TC (36)
#define INT0_HI_SEC (37)
#define INT0_HI_FEC1 (38)
#define INT0_HI_FEC0 (39)
#define INT0_HI_I2C (40)
#define INT0_HI_PCIARB (41)
#define INT0_HI_CBPCI (42)
#define INT0_HI_XLBPCI (43)
#define INT0_HI_XLBARB (47)
#define INT0_HI_DMA (48)
#define INT0_HI_CAN0_ERROR (49)
#define INT0_HI_CAN0_BUSOFF (50)
#define INT0_HI_CAN0_MBOR (51)
#define INT0_HI_SLT1 (53)
#define INT0_HI_SLT0 (54)
#define INT0_HI_CAN1_ERROR (55)
#define INT0_HI_CAN1_BUSOFF (56)
#define INT0_HI_CAN1_MBOR (57)
#define INT0_HI_GPT3 (59)
#define INT0_HI_GPT2 (60)
#define INT0_HI_GPT1 (61)
#define INT0_HI_GPT0 (62)
/*********************************************************************
* General Purpose Timers (GPTMR)
*********************************************************************/
/* Enable and Mode Select */
#define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */
#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
#define GPT_CTRL_CE 0x10 /* Counter Enable */
#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
#define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */
#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
#define GPT_PWM_WIDTH(x) (x & 0xffff)
/* Status */
#define GPT_STA_CAPTURE(x) (x & 0xffff)
#define GPT_OVFPIN_OVF(x) (x & 0x70)
#define GPT_OVFPIN_PIN 0x01
#define GPT_INT_TEXP 0x08
#define GPT_INT_PWMP 0x04
#define GPT_INT_COMP 0x02
#define GPT_INT_CAPT 0x01
/*********************************************************************
* PCI
*********************************************************************/
/* Bit definitions and macros for SCR */
#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
#define PCI_SCR_SE (0x40000000) /* System error signalled */
#define PCI_SCR_MA (0x20000000) /* Master aboart received */
#define PCI_SCR_TR (0x10000000) /* Target abort received */
#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
#define PCI_SCR_DP (0x01000000) /* Master data parity err */
#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
#define PCI_SCR_R (0x00400000) /* Reserved */
#define PCI_SCR_66M (0x00200000) /* 66Mhz */
#define PCI_SCR_C (0x00100000) /* Capabilities list */
#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
#define PCI_SCR_S (0x00000100) /* SERR enable */
#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
#define PCI_SCR_PER (0x00000040) /* Parity error response */
#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
#define PCI_SCR_B (0x00000004) /* Bus master enable */
#define PCI_SCR_M (0x00000002) /* Memory access control */
#define PCI_SCR_IO (0x00000001) /* I/O access control */
#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
#define PCI_BAR_BAR1(x) (x & 0xC0000000)
#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
#define PCI_GSCR_SE (0x10000000) /* SERR detected */
#define PCI_GSCR_ER (0x08000000) /* Error response detected */
#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
#define PCI_GSCR_PR (0x00000001) /* PCI reset */
#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
#define PCI_TCR1_B5E (0x00002000) /* */
#define PCI_TCR1_B4E (0x00001000) /* */
#define PCI_TCR1_B3E (0x00000800) /* */
#define PCI_TCR1_B2E (0x00000400) /* */
#define PCI_TCR1_B1E (0x00000200) /* */
#define PCI_TCR1_B0E (0x00000100) /* */
#define PCI_TCR1_CR (0x00000001) /* */
#define PCI_TBATR_BAT0(x) (x & 0xFFFC0000)
#define PCI_TBATR_BAT1(x) (x & 0xC0000000)
#define PCI_TBATR_EN (0x00000001) /* Enable */
#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
#define PCI_ICR_REE (0x04000000) /* Retry error enable */
#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
#define PCIARB_ACR_DS (0x80000000)
#define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17)
#define PCIARB_ARC_INTMINTEN (0x00010000)
#define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1)
#define PCIARB_ARC_INTMPRI (0x00000001)
#endif /* mcf547x_8x_h */
arch/m68k/lib/cache.c
浏览文件 @ 9b7993bb
......@@ -80,7 +80,7 @@ void icache_invalid(void)
}
/*
* data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
* data cache only for ColdFire V4 such as MCF5445x
* the dcache will be dummy in ColdFire V2 and V3
*/
void dcache_enable(void)
......
board/freescale/m547xevb/Kconfig 已删除 100644 → 0
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if TARGET_M5475EVB
config SYS_CPU
default "mcf547x_8x"
config SYS_BOARD
default "m547xevb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "M5475EVB"
endif
board/freescale/m547xevb/MAINTAINERS 已删除 100644 → 0
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M547XEVB BOARD
M: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
S: Maintained
F: board/freescale/m547xevb/
F: include/configs/M5475EVB.h
F: configs/M5475AFE_defconfig
F: configs/M5475BFE_defconfig
F: configs/M5475CFE_defconfig
F: configs/M5475DFE_defconfig
F: configs/M5475EFE_defconfig
F: configs/M5475FFE_defconfig
F: configs/M5475GFE_defconfig
board/freescale/m547xevb/Makefile 已删除 100644 → 0
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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y = m547xevb.o
board/freescale/m547xevb/README 已删除 100644 → 0
浏览文件 @ eb83d10b
Freescale MCF5475EVB ColdFire Development Board
================================================
TsiChung Liew(Tsi-Chung.Liew@freescale.com)
Created Jan 08, 2008
===========================================
Changed files:
==============
- board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
- board/freescale/m547xevb/mii.c MII init
- board/freescale/m547xevb/Makefile Makefile
- board/freescale/m547xevb/config.mk config make
- board/freescale/m547xevb/u-boot.lds Linker description
- arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
- arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
- arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
- arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
- arch/m68k/cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock
- arch/m68k/cpu/mcf547x_8x/Makefile Makefile
- arch/m68k/cpu/mcf547x_8x/config.mk config make
- arch/m68k/cpu/mcf547x_8x/start.S start up assembly code
- board/freescale/m547xevb/README This readme file
- drivers/dma/MCD_dmaApi.c DMA API functions
- drivers/dma/MCD_tasks.c DMA Tasks
- drivers/dma/MCD_tasksInit.c DMA Tasks Init
- drivers/net/fsl_mcdmafec.c ColdFire common DMA FEC driver
- drivers/serial/mcfuart.c ColdFire common UART driver
- include/MCD_dma.h DMA header file
- include/MCD_progCheck.h DMA header file
- include/MCD_tasksInit.h DMA header file
- include/asm-m68k/bitops.h Bit operation function export
- include/asm-m68k/byteorder.h Byte order functions
- include/asm-m68k/errno.h Error Number definition
- include/asm-m68k/fec.h FEC structure and definition
- include/asm-m68k/fsl_i2c.h I2C structure and definition
- include/asm-m68k/fsl_mcddmafec.h DMA FEC structure and definition
- include/asm-m68k/global_data.h Global data structure
- include/asm-m68k/immap.h ColdFire specific header file and driver macros
- include/asm-m68k/immap_547x_8x.h mcf547x_8x specific header file
- include/asm-m68k/io.h io functions
- include/asm-m68k/m547x_8x.h mcf547x_8x specific header file
- include/asm-m68k/posix_types.h Posix
- include/asm-m68k/processor.h header file
- include/asm-m68k/ptrace.h Exception structure
- include/asm-m68k/rtc.h Realtime clock header file
- include/asm-m68k/string.h String function export
- include/asm-m68k/timer.h Timer structure and definition
- include/asm-m68k/types.h Data types definition
- include/asm-m68k/uart.h Uart structure and definition
- include/asm-m68k/u-boot.h U-Boot structure
- include/configs/M5475EVB.h Board specific configuration file
- arch/m68k/lib/board.c board init function
- arch/m68k/lib/cache.c
- arch/m68k/lib/interrupts Coldfire common interrupt functions
- arch/m68k/lib/m68k_linux.c
- arch/m68k/lib/traps.c Exception init code
1 MCF547x specific Options/Settings
====================================
1.1 pre-loader is no longer suppoer in thie coldfire family
1.2 Configuration settings for M5475EVB Development Board
CONFIG_MCF547x_8x -- define for all MCF547x_8x CPUs
CONFIG_M547x -- define for all Freescale MCF547x CPUs
CONFIG_M5475 -- define for M5475EVB board
CONFIG_MCFUART -- define to use common CF Uart driver
CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
CONFIG_BAUDRATE -- define UART baudrate
CONFIG_FSLDMAFEC -- define to use common dma FEC driver
CONFIG_MII -- enable to use MII driver
CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_HAS_ETH1 -- define to enable second FEC in U-Boot
CONFIG_CMD_USB -- enable USB commands
CONFIG_USB_OHCI_NEW -- enable USB OHCI driver
CONFIG_USB_STORAGE -- enable USB Storage device
CONFIG_DOS_PARTITION -- enable DOS read/write
CONFIG_SLTTMR -- define to use SLT timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
CONFIG_SYS_IMMR -- define for MBAR offset
CONFIG_PCI -- define for PCI support
CONFIG_PCI_PNP -- define for Plug n play support
CONFIG_SKIPPCI_HOSTBRIDGE -- SKIP PCI Host bridge
CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset
CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset
CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size
CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset
CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset
CONFIG_SYS_PCI_IO_SIZE -- PCI IO size
CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset
CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset
CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size
CONFIG_SYS_MBAR -- define MBAR offset
CONFIG_MONITOR_IS_IN_RAM -- Not support
CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF547x internal SRAM
CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
2.1. System memory map:
Flash: 0xFF800000-0xFFFFFFFF (8MB)
DDR: 0x00000000-0x3FFFFFFF (1024MB)
SRAM: 0xF2000000-0xF2000FFF (4KB)
PCI: 0x70000000-0x8FFFFFFF (512MB)
IP: 0xF0000000-0xFFFFFFFF (256MB)
3. COMPILATION
==============
3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux
version) from codesourcery.com was used. Download it from:
http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
3.2 Compilation
export CROSS_COMPILE=cross-compile-prefix
cd u-boot-1.x.x
make distclean
make M5475AFE_config, or - boot 2MB, RAM 64MB
make M5475BFE_config, or - boot 2MB, code 16MB, RAM 64MB
make M5475CFE_config, or - boot 2MB, code 16MB, Video, USB, RAM 64MB
make M5475DFE_config, or - boot 2MB, USB, RAM 64MB
make M5475EFE_config, or - boot 2MB, Video, USB, RAM 64MB
make M5475FFE_config, or - boot 2MB, code 32MB, Video, USB, RAM 128MB
make M5475GFE_config, or - boot 2MB, RAM 64MB
make
5. SCREEN DUMP
==============
5.1
U-Boot 1.3.1 (Jan 8 2008 - 12:47:44)
CPU: Freescale MCF5475
CPU CLK 266 Mhz BUS CLK 133 Mhz
Board: Freescale FireEngine 5475 EVB
I2C: ready
DRAM: 64 MB
FLASH: 18 MB
In: serial
Out: serial
Err: serial
Net: FEC0, FEC1
-> pri
bootdelay=1
baudrate=115200
ethaddr=00:e0:0c:bc:e5:60
eth1addr=00:e0:0c:bc:e5:61
ipaddr=192.162.1.2
serverip=192.162.1.1
gatewayip=192.162.1.1
netmask=255.255.255.0
hostname=M547xEVB
netdev=eth0
loadaddr=10000
u-boot=u-boot.bin
load=tftp ${loadaddr) ${u-boot}
upd=run load; run prog
prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save
stdin=serial
stdout=serial
stderr=serial
ethact=FEC0
mem=65024k
Environment size: 433/8188 bytes
-> bdin
memstart = 0x00000000
memsize = 0x04000000
flashstart = 0xFF800000
flashsize = 0x01200000
flashoffset = 0x00000000
sramstart = 0xF2000000
sramsize = 0x00001000
mbar = 0xF0000000
busfreq = 133.333 MHz
pcifreq = 0 MHz
ethaddr = 00:E0:0C:BC:E5:60
eth1addr = 00:E0:0C:BC:E5:61
ip_addr = 192.162.1.2
baudrate = 115200 bps
-> ?
? - alias for 'help'
base - print or set address offset
bdinfo - print Board Info structure
boot - boot default, i.e., run 'bootcmd'
bootd - boot default, i.e., run 'bootcmd'
bootelf - Boot from an ELF image in memory
bootm - boot application image from memory
bootp - boot image via network using BootP/TFTP protocol
bootvx - Boot vxWorks from an ELF image
cmp - memory compare
coninfo - print console devices and information
cp - memory copy
crc32 - checksum calculation
dcache - enable or disable data cache
echo - echo args to console
erase - erase FLASH memory
flinfo - print FLASH memory information
go - start application at address 'addr'
help - print online help
i2c - I2C sub-system
icache - enable or disable instruction cache
iminfo - print header information for application image
imls - list all images found in flash
itest - return true/false on integer compare
loadb - load binary file over serial line (kermit mode)
loads - load S-Record file over serial line
loady - load binary file over serial line (ymodem mode)
loop - infinite loop on address range
md - memory display
mii - MII utility commands
mm - memory modify (auto-incrementing)
mtest - simple RAM test
mw - memory write (fill)
nfs - boot image via network using NFS protocol
nm - memory modify (constant address)
pci - list and access PCI Configuration Space
ping - send ICMP ECHO_REQUEST to network host
printenv- print environment variables
protect - enable or disable FLASH write protection
rarpboot- boot image via network using RARP/TFTP protocol
reset - Perform RESET of the CPU
run - run commands in an environment variable
saveenv - save environment variables to persistent storage
setenv - set environment variables
sleep - delay execution for some time
source - run script from memory
tftpboot- boot image via network using TFTP protocol
usb - USB sub-system
usbboot - boot from USB device
version - print monitor version
-> usb start
(Re)start USB...
USB: OHCI pci controller (1131, 1561) found @(0:17:0)
OHCI regs address 0x80000000
scanning bus for devices... 2 USB Device(s) found
scanning bus for storage devices... 1 Storage Device(s) found
->
board/freescale/m547xevb/m547xevb.c 已删除 100644 → 0
浏览文件 @ eb83d10b
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <config.h>
#include <common.h>
#include <init.h>
#include <pci.h>
#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale FireEngine 5475 EVB\n");
return 0;
};
int dram_init(void)
{
siu_t *siu = (siu_t *) (MMAP_SIU);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
u32 temp;
#endif
out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (temp == (1 << i))
break;
}
i--;
dramsize += temp;
out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
gd->ram_size = dramsize;
return 0;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}
#if defined(CONFIG_PCI)
/*
* Initialize PCI devices, report devices found.
*/
static struct pci_controller hose;
extern void pci_mcf547x_8x_init(struct pci_controller *hose);
void pci_init_board(void)
{
pci_mcf547x_8x_init(&hose);
}
#endif /* CONFIG_PCI */
configs/M5475AFE_defconfig 已删除 100644 → 0
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CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5475AFE"
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
configs/M5475BFE_defconfig 已删除 100644 → 0
浏览文件 @ eb83d10b
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5475BFE"
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
configs/M5475CFE_defconfig 已删除 100644 → 0
浏览文件 @ eb83d10b
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5475CFE"
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
configs/M5475DFE_defconfig 已删除 100644 → 0
浏览文件 @ eb83d10b
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5475DFE"
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
configs/M5475EFE_defconfig 已删除 100644 → 0
浏览文件 @ eb83d10b
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5475EFE"
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
configs/M5475FFE_defconfig 已删除 100644 → 0
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CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5475FFE"
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
configs/M5475GFE_defconfig 已删除 100644 → 0
浏览文件 @ eb83d10b
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5475GFE"
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
doc/arch/m68k.rst
浏览文件 @ 9b7993bb
......@@ -72,7 +72,7 @@ A bash script similar to the one below may be used:
export CROSS_COMPILE=/opt/toolchains/m68k/gcc-4.9.0-nolibc/bin/m68k-linux-
board=M5475DFE
board=M5249EVB
make distclean
make ${board}_defconfig
......
drivers/net/mcfmii.c
浏览文件 @ 9b7993bb
......@@ -11,11 +11,7 @@
#include <asm/global_data.h>
#include <linux/delay.h>
#ifdef CONFIG_MCF547x_8x
#include <asm/fsl_mcdmafec.h>
#else
#include <asm/fec.h>
#endif
#include <asm/immap.h>
#include <linux/mii.h>
......
env/Kconfig
浏览文件 @ 9b7993bb
......@@ -82,7 +82,7 @@ config ENV_IS_IN_FLASH
depends on !CHAIN_OF_TRUST
default y if ARCH_CINTEGRATOR
default y if ARCH_INTEGRATOR_CP
default y if M548x || M547x || M5282 || MCF547x_8x
default y if M548x || M547x || M5282
default y if MCF532x || MCF52x2
default y if MPC86xx || MPC83xx
default y if ARCH_MPC8572 || ARCH_MPC8548 || ARCH_MPC8641
......
include/configs/M5475EVB.h 已删除 100644 → 0
浏览文件 @ eb83d10b
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Freescale MCF5475 board.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5475EVB_H
#define _M5475EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
#define CONFIG_SLTTMR
#ifdef CONFIG_FSLDMAFEC
# define CONFIG_MII_INIT 1
# define CONFIG_HAS_ETH1
# define CONFIG_SYS_DMA_USE_INTSRAM 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 32
# define CONFIG_SYS_TX_ETH_BUFFER 48
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif
#ifdef CONFIG_CMD_USB
# define CONFIG_USB_OHCI_NEW
# define CONFIG_PCI_OHCI
# undef CONFIG_SYS_USB_OHCI_BOARD_INIT
# undef CONFIG_SYS_USB_OHCI_CPU_INIT
# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#endif
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCI_IO_BUS 0x71000000
#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
#endif
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME "M547xEVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off bank 1;" \
"era ff800000 ff83ffff;" \
"cp.b ${loadaddr} ff800000 ${filesize};"\
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
#define CONFIG_SYS_INTSRAMSZ 0x8000
/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_CFG1 0x73711630
#define CONFIG_SYS_SDRAM_CFG2 0x46770000
#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
#ifdef CONFIG_SYS_DRAMSZ1
# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
#else
# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
#endif
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
#ifdef CONFIG_SYS_NOR1SZ
# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#else
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
#endif
#endif
/* Configuration for environment
* Environment is not embedded in u-boot but at offset 0x40000 on the flash.
* First time runing may have env crc error warning if there is
* no correct environment on the flash.
*/
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
CF_CACR_IEC | CF_CACR_ICINVA)
#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
CF_CACR_DEC | CF_CACR_DDCM_P | \
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - NOR Flash
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0xFF800000
#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS0_CTRL 0x00101980
#ifdef CONFIG_SYS_NOR1SZ
#define CONFIG_SYS_CS1_BASE 0xE0000000
#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS1_CTRL 0x00101D80
#endif
#endif /* _M5475EVB_H */
include/fsl_dspi.h
浏览文件 @ 9b7993bb
......@@ -21,14 +21,8 @@ struct dspi {
u32 irsr; /* 0x30 */
u32 tfr; /* 0x34 - PUSHR */
u32 rfr; /* 0x38 - POPR */
#ifdef CONFIG_MCF547x_8x
u32 tfdr[4]; /* 0x3C */
u8 resv2[0x30]; /* 0x40 */
u32 rfdr[4]; /* 0x7C */
#else
u32 tfdr[16]; /* 0x3C */
u32 rfdr[16]; /* 0x7C */
#endif
};
/* Module configuration */
......
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