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体验新版 GitCode,发现更多精彩内容 >>
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96e48cf6
编写于
8月 05, 2003
作者:
W
wdenk
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电子邮件补丁
差异文件
* Fix PCI support for MPC5200 / IceCube Board
上级
bdccc4fe
变更
6
隐藏空白更改
内联
并排
Showing
6 changed file
with
261 addition
and
9 deletion
+261
-9
CHANGELOG
CHANGELOG
+2
-0
board/icecube/icecube.c
board/icecube/icecube.c
+12
-0
cpu/mpc5xxx/Makefile
cpu/mpc5xxx/Makefile
+1
-1
cpu/mpc5xxx/pci_mpc5200.c
cpu/mpc5xxx/pci_mpc5200.c
+175
-0
include/configs/IceCube.h
include/configs/IceCube.h
+39
-8
include/mpc5xxx.h
include/mpc5xxx.h
+32
-0
未找到文件。
CHANGELOG
浏览文件 @
96e48cf6
...
...
@@ -2,6 +2,8 @@
Changes for U-Boot 0.4.5:
======================================================================
* Fix PCI support for MPC5200 / IceCube Board
* Map ISP1362 USB OTG controller for NSCU board
* Patch by Brad Parker, 02 Aug 2003:
...
...
board/icecube/icecube.c
浏览文件 @
96e48cf6
...
...
@@ -23,6 +23,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
long
int
initdram
(
int
board_type
)
{
...
...
@@ -114,3 +115,14 @@ void flash_preinit(void)
#endif
*
(
vu_long
*
)
MPC5XXX_BOOTCS_CFG
&=
~
0x1
;
/* clear RO */
}
#ifdef CONFIG_PCI
static
struct
pci_controller
hose
;
extern
void
pci_mpc5xxx_init
(
struct
pci_controller
*
);
void
pci_init_board
(
void
)
{
pci_mpc5xxx_init
(
&
hose
);
}
#endif
cpu/mpc5xxx/Makefile
浏览文件 @
96e48cf6
...
...
@@ -28,7 +28,7 @@ LIB = lib$(CPU).a
START
=
start.o
ASOBJS
=
io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
OBJS
=
traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o
\
loadtask.o fec.o
loadtask.o fec.o
pci_mpc5200.o
all
:
.depend $(START) $(ASOBJS) $(LIB)
...
...
cpu/mpc5xxx/pci_mpc5200.c
0 → 100644
浏览文件 @
96e48cf6
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <mpc5xxx.h>
/* System RAM mapped over PCI */
#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
/* PCIIWCR bit fields */
#define IWCR_MEM (0 << 3)
#define IWCR_IO (1 << 3)
#define IWCR_READ (0 << 1)
#define IWCR_READLINE (1 << 1)
#define IWCR_READMULT (2 << 1)
#define IWCR_EN (1 << 0)
static
int
mpc5200_read_config_dword
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
,
int
offset
,
u32
*
value
)
{
*
(
volatile
u32
*
)
MPC5XXX_PCI_CAR
=
(
1
<<
31
)
|
dev
|
offset
;
eieio
();
*
value
=
in_le32
((
volatile
u32
*
)
CONFIG_PCI_IO_PHYS
);
eieio
();
*
(
volatile
u32
*
)
MPC5XXX_PCI_CAR
=
0
;
/* skip MPC5200 */
if
(
offset
==
0
&&
*
value
==
0x58031057
)
*
value
=
0xffffffff
;
return
0
;
}
static
int
mpc5200_write_config_dword
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
,
int
offset
,
u32
value
)
{
*
(
volatile
u32
*
)
MPC5XXX_PCI_CAR
=
(
1
<<
31
)
|
dev
|
offset
;
eieio
();
out_le32
((
volatile
u32
*
)
CONFIG_PCI_IO_PHYS
,
value
);
eieio
();
*
(
volatile
u32
*
)
MPC5XXX_PCI_CAR
=
0
;
return
0
;
}
void
pci_mpc5xxx_init
(
struct
pci_controller
*
hose
)
{
hose
->
first_busno
=
0
;
hose
->
last_busno
=
0xff
;
/* System space */
pci_set_region
(
hose
->
regions
+
0
,
CONFIG_PCI_MEMORY_BUS
,
CONFIG_PCI_MEMORY_PHYS
,
CONFIG_PCI_MEMORY_SIZE
,
PCI_REGION_MEM
|
PCI_REGION_MEMORY
);
/* PCI memory space */
pci_set_region
(
hose
->
regions
+
1
,
CONFIG_PCI_MEM_BUS
,
CONFIG_PCI_MEM_PHYS
,
CONFIG_PCI_MEM_SIZE
,
PCI_REGION_MEM
);
/* PCI IO space */
pci_set_region
(
hose
->
regions
+
2
,
CONFIG_PCI_IO_BUS
,
CONFIG_PCI_IO_PHYS
,
CONFIG_PCI_IO_SIZE
,
PCI_REGION_IO
);
hose
->
region_count
=
3
;
pci_register_hose
(
hose
);
/* GPIO Multiplexing - enable PCI */
*
(
vu_long
*
)
MPC5XXX_GPS_PORT_CONFIG
&=
~
(
1
<<
15
);
/* Set host bridge as pci master and enable memory decoding */
*
(
vu_long
*
)
MPC5XXX_PCI_CMD
|=
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
;
/* Set maximum latency timer */
*
(
vu_long
*
)
MPC5XXX_PCI_CFG
|=
(
0xf800
);
/* Set cache line size */
*
(
vu_long
*
)
MPC5XXX_PCI_CFG
=
(
*
(
vu_long
*
)
MPC5XXX_PCI_CFG
&
~
0xff
)
|
(
CFG_CACHELINE_SIZE
/
4
);
/* Map MBAR to PCI space */
*
(
vu_long
*
)
MPC5XXX_PCI_BAR0
=
CFG_MBAR
;
*
(
vu_long
*
)
MPC5XXX_PCI_TBATR1
=
CFG_MBAR
|
1
;
/* Map RAM to PCI space */
*
(
vu_long
*
)
MPC5XXX_PCI_BAR1
=
CONFIG_PCI_MEMORY_BUS
|
(
1
<<
3
);
*
(
vu_long
*
)
MPC5XXX_PCI_TBATR1
=
CONFIG_PCI_MEMORY_PHYS
|
1
;
/* Enable snooping for RAM */
*
(
vu_long
*
)(
MPC5XXX_XLBARB
+
0x40
)
|=
(
1
<<
15
);
*
(
vu_long
*
)(
MPC5XXX_XLBARB
+
0x70
)
=
CONFIG_PCI_MEMORY_PHYS
|
0x1d
;
/* Park XLB on PCI */
*
(
vu_long
*
)(
MPC5XXX_XLBARB
+
0x40
)
&=
~
((
7
<<
8
)
|
(
3
<<
5
));
*
(
vu_long
*
)(
MPC5XXX_XLBARB
+
0x40
)
|=
(
3
<<
8
)
|
(
3
<<
5
);
/* Enable piplining */
*
(
vu_long
*
)(
MPC5XXX_XLBARB
+
0x40
)
&=
~
(
1
<<
31
);
/* Disable interrupts from PCI controller */
*
(
vu_long
*
)
MPC5XXX_PCI_GSCR
&=
~
(
7
<<
12
);
*
(
vu_long
*
)
MPC5XXX_PCI_ICR
&=
~
(
7
<<
24
);
/* Disable initiator windows */
*
(
vu_long
*
)
MPC5XXX_PCI_IWCR
=
0
;
/* Map PCI memory to physical space */
*
(
vu_long
*
)
MPC5XXX_PCI_IW0BTAR
=
CONFIG_PCI_MEM_PHYS
|
(((
CONFIG_PCI_MEM_SIZE
-
1
)
>>
8
)
&
0x00ff0000
)
|
(
CONFIG_PCI_MEM_BUS
>>
16
);
*
(
vu_long
*
)
MPC5XXX_PCI_IWCR
|=
(
IWCR_MEM
|
IWCR_READ
|
IWCR_EN
)
<<
24
;
/* Map PCI I/O to physical space */
*
(
vu_long
*
)
MPC5XXX_PCI_IW1BTAR
=
CONFIG_PCI_IO_PHYS
|
(((
CONFIG_PCI_IO_SIZE
-
1
)
>>
8
)
&
0x00ff0000
)
|
(
CONFIG_PCI_IO_BUS
>>
16
);
*
(
vu_long
*
)
MPC5XXX_PCI_IWCR
|=
(
IWCR_IO
|
IWCR_READ
|
IWCR_EN
)
<<
16
;
/* Reset the PCI bus */
*
(
vu_long
*
)
MPC5XXX_PCI_GSCR
|=
1
;
udelay
(
1000
);
*
(
vu_long
*
)
MPC5XXX_PCI_GSCR
&=
~
1
;
udelay
(
1000
);
pci_set_ops
(
hose
,
pci_hose_read_config_byte_via_dword
,
pci_hose_read_config_word_via_dword
,
mpc5200_read_config_dword
,
pci_hose_write_config_byte_via_dword
,
pci_hose_write_config_word_via_dword
,
mpc5200_write_config_dword
);
udelay
(
1000
);
#ifdef CONFIG_PCI_SCAN_SHOW
printf
(
"PCI: Bus Dev VenId DevId Class Int
\n
"
);
#endif
hose
->
last_busno
=
pci_hose_scan
(
hose
);
}
#endif
/* CONFIG_PCI && CONFIG_MPC5200 */
include/configs/IceCube.h
浏览文件 @
96e48cf6
...
...
@@ -37,7 +37,7 @@
#define BOOTFLAG_COLD 0x01
/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02
/* Software reboot */
#define CFG_CACHELINE_SIZE 32
/* For MPC
8260 CPU
*/
#define CFG_CACHELINE_SIZE 32
/* For MPC
5xxx CPUs
*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5
/* log base 2 of the above value */
#endif
...
...
@@ -49,10 +49,41 @@
#define CONFIG_BAUDRATE 115200
/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifdef CONFIG_MPC5200
/* MPC5100 PCI is not supported yet. */
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8
/* use 8 rx buffer on eepro100 */
#define ADD_PCI_CMD CFG_CMD_PCI
#else
/* MPC5100 */
#define ADD_PCI_CMD 0
/* no CFG_CMD_PCI */
#endif
/*
* Supported commands
*/
#define CONFIG_COMMANDS
CONFIG_CMD_DFL
#define CONFIG_COMMANDS
(CONFIG_CMD_DFL | ADD_PCI_CMD)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
...
...
@@ -83,17 +114,17 @@
#define CFG_FLASH_ERASE_TOUT 240000
/* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500
/* Flash Write Timeout (in ms) */
#undef CONFIG_FLASH_16BIT
/* Flash is 8-bit */
#undef CONFIG_FLASH_16BIT
/* Flash is 8-bit */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH
1
#define CFG_ENV_IS_IN_FLASH
1
#define CFG_ENV_SIZE 0x10000
#define CFG_ENV_ADDR
(CFG_FLASH_BASE + 0x740000)
#define CFG_ENV_SECT_SIZE
0x10000
#define CFG_ENV_ADDR
(CFG_FLASH_BASE + 0x740000)
#define CFG_ENV_SECT_SIZE
0x10000
#define CONFIG_ENV_OVERWRITE 1
/*
* Memory map
...
...
@@ -112,7 +143,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT
1
# define CFG_RAMBOOT
1
#endif
#define CFG_MONITOR_LEN (256 << 10)
/* Reserve 256 kB for Monitor */
...
...
include/mpc5xxx.h
浏览文件 @
96e48cf6
...
...
@@ -61,6 +61,10 @@
#if defined(CONFIG_MGT5100)
#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
#elif defined(CONFIG_MPC5200)
#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
...
...
@@ -75,6 +79,7 @@
#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
...
...
@@ -136,6 +141,33 @@
/* GPIO registers */
#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
/* PCI registers */
#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
#if defined(CONFIG_MGT5100)
#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
#elif defined(CONFIG_MPC5200)
#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
#endif
/* Interrupt Controller registers */
#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
...
...
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