Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OS
U-Boot.Mirror
提交
9658bec2
U
U-Boot.Mirror
项目概览
OS
/
U-Boot.Mirror
通知
1
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
U
U-Boot.Mirror
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
9658bec2
编写于
8月 26, 2008
作者:
K
Kumar Gala
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
FSL DDR: Convert MPC8540EVAL to new DDR code.
Signed-off-by:
N
Kumar Gala
<
galak@kernel.crashing.org
>
上级
6bfa8f72
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
102 addition
and
12 deletion
+102
-12
board/mpc8540eval/Makefile
board/mpc8540eval/Makefile
+8
-4
board/mpc8540eval/ddr.c
board/mpc8540eval/ddr.c
+70
-0
board/mpc8540eval/mpc8540eval.c
board/mpc8540eval/mpc8540eval.c
+5
-1
include/configs/MPC8540EVAL.h
include/configs/MPC8540EVAL.h
+19
-7
未找到文件。
board/mpc8540eval/Makefile
浏览文件 @
9658bec2
...
...
@@ -25,10 +25,14 @@ include $(TOPDIR)/config.mk
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
:=
$(BOARD)
.o flash.o law.o tlb.o
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
COBJS-y
+=
$(BOARD)
.o
COBJS-y
+=
law.o
COBJS-y
+=
tlb.o
COBJS-y
+=
flash.o
COBJS-$(CONFIG_FSL_DDR1)
+=
ddr.o
SRCS
:=
$(SOBJS:.o=.S)
$
(
COBJS-y:.o
=
.c
)
OBJS
:=
$(
addprefix
$(obj)
,
$
(
COBJS-y
))
SOBJS
:=
$(
addprefix
$(obj)
,
$(SOBJS)
)
$(LIB)
:
$(obj).depend $(OBJS) $(SOBJS)
...
...
board/mpc8540eval/ddr.c
0 → 100644
浏览文件 @
9658bec2
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
static
void
get_spd
(
ddr1_spd_eeprom_t
*
spd
,
unsigned
char
i2c_address
)
{
i2c_read
(
i2c_address
,
0
,
1
,
(
uchar
*
)
spd
,
sizeof
(
ddr1_spd_eeprom_t
));
}
unsigned
int
fsl_ddr_get_mem_data_rate
(
void
)
{
return
get_ddr_freq
(
0
);
}
void
fsl_ddr_get_spd
(
ddr1_spd_eeprom_t
*
ctrl_dimms_spd
,
unsigned
int
ctrl_num
)
{
unsigned
int
i
;
unsigned
int
i2c_address
=
0
;
for
(
i
=
0
;
i
<
CONFIG_DIMM_SLOTS_PER_CTLR
;
i
++
)
{
if
(
ctrl_num
==
0
&&
i
==
0
)
{
i2c_address
=
SPD_EEPROM_ADDRESS
;
}
get_spd
(
&
(
ctrl_dimms_spd
[
i
]),
i2c_address
);
}
}
void
fsl_ddr_board_options
(
memctl_options_t
*
popts
,
unsigned
int
ctrl_num
)
{
/*
* Factors to consider for CPO:
* - frequency
* - ddr1 vs. ddr2
*/
popts
->
cpo_override
=
0
;
/*
* Factors to consider for write data delay:
* - number of DIMMs
*
* 1 = 1/4 clock delay
* 2 = 1/2 clock delay
* 3 = 3/4 clock delay
* 4 = 1 clock delay
* 5 = 5/4 clock delay
* 6 = 3/2 clock delay
*/
popts
->
write_data_delay
=
3
;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts
->
half_strength_driver_enable
=
0
;
}
board/mpc8540eval/mpc8540eval.c
浏览文件 @
9658bec2
...
...
@@ -25,7 +25,9 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <spd_sdram.h>
long
int
fixed_sdram
(
void
);
...
...
@@ -84,7 +86,9 @@ phys_size_t initdram (int board_type)
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size
=
spd_sdram
();
dram_size
=
fsl_ddr_sdram
();
dram_size
=
setup_ddr_tlbs
(
dram_size
/
0x100000
);
dram_size
*=
0x100000
;
#else
dram_size
=
fixed_sdram
();
#endif
...
...
include/configs/MPC8540EVAL.h
浏览文件 @
9658bec2
...
...
@@ -39,9 +39,6 @@
#undef CONFIG_PCI
/* pci ethernet support */
#define CONFIG_TSEC_ENET
/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM
/* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC
/* only for ECC DDR module */
#define CONFIG_DDR_DLL
/* possible DLL fix needed */
#define CONFIG_FSL_LAW 1
/* Use common FSL init code */
...
...
@@ -86,8 +83,6 @@
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR
/* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR
/* PQII uses CFG_IMMR */
#define CFG_DDR_SDRAM_BASE 0x00000000
/* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CFG_SDRAM_SIZE 256
/* DDR is now 256MB */
#if defined(CONFIG_RAM_AS_FLASH)
...
...
@@ -121,10 +116,27 @@
#undef CFG_RAMBOOT
#endif
#define SPD_EEPROM_ADDRESS 0x51
/* DDR DIMM */
/* DDR Setup */
#define CONFIG_FSL_DDR1
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM
/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_DDR_DLL
/* possible DLL fix needed */
#undef CONFIG_DDR_ECC
/* only for ECC DDR module */
#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CFG_DDR_SDRAM_BASE 0x00000000
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
/* Here some DDR setting should be added */
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51
/* CTLR 0 DIMM 0 */
#undef CONFIG_CLOCKS_IN_MHZ
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录