x86: apl: Allow reading hostbridge base addresses

Add a few functions to permit reading of various useful base addresses
provided by the hostbridge.
Signed-off-by: NSimon Glass <sjg@chromium.org>

arch/x86/cpu/apollolake/hostbridge.c

@@ -40,7 +40,9 @@ enum {
 
 	PCIEXBAR_PCIEXBAREN	= 1 << 0,
 
+	BGSM			= 0xb4,  /* Base GTT Stolen Memory */
 	TSEG			= 0xb8,  /* TSEG base */
+	TOLUD			= 0xbc,
 };
 
 static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
@@ -165,6 +167,31 @@ static int apl_hostbridge_probe(struct udevice *dev)
 	return 0;
 }
 
+static ulong sa_read_reg(struct udevice *dev, int reg)
+{
+	u32 val;
+
+	/* All regions concerned for have 1 MiB alignment */
+	dm_pci_read_config32(dev, BGSM, &val);
+
+	return ALIGN_DOWN(val, 1 << 20);
+}
+
+ulong sa_get_tolud_base(struct udevice *dev)
+{
+	return sa_read_reg(dev, TOLUD);
+}
+
+ulong sa_get_gsm_base(struct udevice *dev)
+{
+	return sa_read_reg(dev, BGSM);
+}
+
+ulong sa_get_tseg_base(struct udevice *dev)
+{
+	return sa_read_reg(dev, TSEG);
+}
+
 static const struct udevice_id apl_hostbridge_ids[] = {
 	{ .compatible = "intel,apl-hostbridge" },
 	{ }

arch/x86/include/asm/arch-apollolake/systemagent.h

@@ -35,4 +35,35 @@
  */
 void enable_bios_reset_cpl(void);
 
+/**
+ * sa_get_tolud_base() - Get the TOLUD base address
+ *
+ * This returns the Top Of Low Useable DRAM, marking the top of usable DRAM
+ * below 4GB
+ *
+ * @dev: hostbridge device
+ * @return TOLUD address
+ */
+ulong sa_get_tolud_base(struct udevice *dev);
+
+/**
+ * sa_get_gsm_base() - Get the GSM base address
+ *
+ * This returns the base of GTT Stolen Memory, marking the start of memory used
+ * for Graphics Translation Tables.
+ *
+ * @dev: hostbridge device
+ * @return GSM address
+ */
+ulong sa_get_gsm_base(struct udevice *dev);
+
+/**
+ * sa_get_tseg_base() - Get the TSEG base address
+ *
+ * This returns the top address of DRAM available below 4GB
+ *
+ * @return TSEG base
+ */
+ulong sa_get_tseg_base(struct udevice *dev);
+
 #endif