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体验新版 GitCode,发现更多精彩内容 >>
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8ed44d91
编写于
10月 19, 2008
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
Cleanup: fix "MHz" spelling
Signed-off-by:
N
Wolfgang Denk
<
wd@denx.de
>
上级
08ef89ec
变更
44
隐藏空白更改
内联
并排
Showing
44 changed file
with
98 addition
and
98 deletion
+98
-98
board/Marvell/db64360/pci.c
board/Marvell/db64360/pci.c
+3
-3
board/Marvell/db64460/pci.c
board/Marvell/db64460/pci.c
+3
-3
board/amcc/katmai/cmd_katmai.c
board/amcc/katmai/cmd_katmai.c
+9
-9
board/amcc/yucca/cmd_yucca.c
board/amcc/yucca/cmd_yucca.c
+11
-11
board/bf537-stamp/post-memory.c
board/bf537-stamp/post-memory.c
+12
-12
board/cray/L1/L1.c
board/cray/L1/L1.c
+4
-4
board/eltec/bab7xx/misc.c
board/eltec/bab7xx/misc.c
+1
-1
board/esd/cpci750/pci.c
board/esd/cpci750/pci.c
+3
-3
board/esd/pci405/pci405.c
board/esd/pci405/pci405.c
+1
-1
board/fads/fads.c
board/fads/fads.c
+5
-5
board/freescale/mpc8540ads/mpc8540ads.c
board/freescale/mpc8540ads/mpc8540ads.c
+2
-2
board/freescale/mpc8541cds/mpc8541cds.c
board/freescale/mpc8541cds/mpc8541cds.c
+2
-2
board/freescale/mpc8555cds/mpc8555cds.c
board/freescale/mpc8555cds/mpc8555cds.c
+2
-2
board/freescale/mpc8560ads/mpc8560ads.c
board/freescale/mpc8560ads/mpc8560ads.c
+2
-2
board/gen860t/beeper.c
board/gen860t/beeper.c
+1
-1
board/idmr/idmr.c
board/idmr/idmr.c
+1
-1
board/motionpro/motionpro.c
board/motionpro/motionpro.c
+1
-1
board/mpc8540eval/mpc8540eval.c
board/mpc8540eval/mpc8540eval.c
+1
-1
board/mpl/pip405/pip405.c
board/mpl/pip405/pip405.c
+1
-1
board/pm854/pm854.c
board/pm854/pm854.c
+2
-2
board/pm856/pm856.c
board/pm856/pm856.c
+2
-2
board/prodrive/p3mx/pci.c
board/prodrive/p3mx/pci.c
+3
-3
board/sbc8560/sbc8560.c
board/sbc8560/sbc8560.c
+1
-1
board/siemens/IAD210/IAD210.c
board/siemens/IAD210/IAD210.c
+1
-1
board/siemens/IAD210/atm.c
board/siemens/IAD210/atm.c
+1
-1
board/tqc/tqm85xx/tqm85xx.c
board/tqc/tqm85xx/tqm85xx.c
+2
-2
cpu/ixp/npe/miiphy.c
cpu/ixp/npe/miiphy.c
+1
-1
cpu/mips/incaip_clock.c
cpu/mips/incaip_clock.c
+2
-2
cpu/mpc8220/i2cCore.c
cpu/mpc8220/i2cCore.c
+1
-1
cpu/mpc83xx/spd_sdram.c
cpu/mpc83xx/spd_sdram.c
+2
-2
cpu/mpc8xx/fec.c
cpu/mpc8xx/fec.c
+1
-1
cpu/mpc8xx/serial.c
cpu/mpc8xx/serial.c
+1
-1
cpu/ppc4xx/4xx_pci.c
cpu/ppc4xx/4xx_pci.c
+1
-1
cpu/ppc4xx/miiphy.c
cpu/ppc4xx/miiphy.c
+1
-1
cpu/ppc4xx/speed.c
cpu/ppc4xx/speed.c
+1
-1
cpu/s3c44b0/cpu.c
cpu/s3c44b0/cpu.c
+1
-1
drivers/block/sym53c8xx.c
drivers/block/sym53c8xx.c
+2
-2
drivers/i2c/omap1510_i2c.c
drivers/i2c/omap1510_i2c.c
+1
-1
drivers/i2c/omap24xx_i2c.c
drivers/i2c/omap24xx_i2c.c
+1
-1
drivers/net/natsemi.c
drivers/net/natsemi.c
+1
-1
drivers/net/ns8382x.c
drivers/net/ns8382x.c
+1
-1
drivers/net/rtl8139.c
drivers/net/rtl8139.c
+1
-1
drivers/net/tigon3.c
drivers/net/tigon3.c
+1
-1
drivers/usb/usbdcore_mpc8xx.c
drivers/usb/usbdcore_mpc8xx.c
+1
-1
未找到文件。
board/Marvell/db64360/pci.c
浏览文件 @
8ed44d91
...
...
@@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host)
printf
(
"PCI %d bus mode: Conventional PCI
\n
"
,
host
);
break
;
case
1
:
printf
(
"PCI %d bus mode: 66 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 66 M
H
z PCIX
\n
"
,
host
);
break
;
case
2
:
printf
(
"PCI %d bus mode: 100 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 100 M
H
z PCIX
\n
"
,
host
);
break
;
case
3
:
printf
(
"PCI %d bus mode: 133 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 133 M
H
z PCIX
\n
"
,
host
);
break
;
default:
printf
(
"Unknown BUS %d
\n
"
,
mode
);
...
...
board/Marvell/db64460/pci.c
浏览文件 @
8ed44d91
...
...
@@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host)
printf
(
"PCI %d bus mode: Conventional PCI
\n
"
,
host
);
break
;
case
1
:
printf
(
"PCI %d bus mode: 66 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 66 M
H
z PCIX
\n
"
,
host
);
break
;
case
2
:
printf
(
"PCI %d bus mode: 100 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 100 M
H
z PCIX
\n
"
,
host
);
break
;
case
3
:
printf
(
"PCI %d bus mode: 133 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 133 M
H
z PCIX
\n
"
,
host
);
break
;
default:
printf
(
"Unknown BUS %d
\n
"
,
mode
);
...
...
board/amcc/katmai/cmd_katmai.c
浏览文件 @
8ed44d91
...
...
@@ -57,9 +57,9 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
do
{
#ifdef CONFIG_STRESS
printf
(
"enter cpu clock frequency 400, 500, 533, 667 M
h
z or quit to abort
\n
"
);
printf
(
"enter cpu clock frequency 400, 500, 533, 667 M
H
z or quit to abort
\n
"
);
#else
printf
(
"enter cpu clock frequency 400, 500, 533 M
h
z or quit to abort
\n
"
);
printf
(
"enter cpu clock frequency 400, 500, 533 M
H
z or quit to abort
\n
"
);
#endif
nbytes
=
readline
(
" ? "
);
...
...
@@ -87,11 +87,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
else
{
do
{
if
(
strcmp
(
cpuClock
,
"400"
)
==
0
)
printf
(
"enter plb clock frequency 100, 133 M
h
z or quit to abort
\n
"
);
printf
(
"enter plb clock frequency 100, 133 M
H
z or quit to abort
\n
"
);
#ifdef CONFIG_STRESS
if
(
strcmp
(
cpuClock
,
"667"
)
==
0
)
printf
(
"enter plb clock frequency 133, 166 M
h
z or quit to abort
\n
"
);
printf
(
"enter plb clock frequency 133, 166 M
H
z or quit to abort
\n
"
);
#endif
nbytes
=
readline
(
" ? "
);
...
...
@@ -117,7 +117,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
do
{
printf
(
"enter Pci-X clock frequency 33, 66, 100 or 133 M
h
z or quit to abort
\n
"
);
printf
(
"enter Pci-X clock frequency 33, 66, 100 or 133 M
H
z or quit to abort
\n
"
);
nbytes
=
readline
(
" ? "
);
if
(
strcmp
(
console_buffer
,
"quit"
)
==
0
)
...
...
@@ -133,10 +133,10 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
while
(
nbytes
==
0
);
printf
(
"
\n
sys clk = %s
Mh
z
\n
"
,
sysClock
);
printf
(
"cpu clk = %s
Mh
z
\n
"
,
cpuClock
);
printf
(
"plb clk = %s
Mh
z
\n
"
,
plbClock
);
printf
(
"Pci-X clk = %s
Mh
z
\n
"
,
pcixClock
);
printf
(
"
\n
sys clk = %s
MH
z
\n
"
,
sysClock
);
printf
(
"cpu clk = %s
MH
z
\n
"
,
cpuClock
);
printf
(
"plb clk = %s
MH
z
\n
"
,
plbClock
);
printf
(
"Pci-X clk = %s
MH
z
\n
"
,
pcixClock
);
do
{
printf
(
"
\n
press [y] to write I2C bootstrap
\n
"
);
...
...
board/amcc/yucca/cmd_yucca.c
浏览文件 @
8ed44d91
...
...
@@ -69,7 +69,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
chip
=
IIC0_ALT_BOOTPROM_ADDR
;
do
{
printf
(
"enter sys clock frequency 33 or 66 M
h
z or quit to abort
\n
"
);
printf
(
"enter sys clock frequency 33 or 66 M
H
z or quit to abort
\n
"
);
nbytes
=
readline
(
" ? "
);
if
(
strcmp
(
console_buffer
,
"quit"
)
==
0
)
...
...
@@ -85,12 +85,12 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
do
{
if
(
strcmp
(
sysClock
,
"66"
)
==
0
)
{
printf
(
"enter cpu clock frequency 400, 533 M
h
z or quit to abort
\n
"
);
printf
(
"enter cpu clock frequency 400, 533 M
H
z or quit to abort
\n
"
);
}
else
{
#ifdef CONFIG_STRESS
printf
(
"enter cpu clock frequency 400, 500, 533, 667 M
h
z or quit to abort
\n
"
);
printf
(
"enter cpu clock frequency 400, 500, 533, 667 M
H
z or quit to abort
\n
"
);
#else
printf
(
"enter cpu clock frequency 400, 500, 533 M
h
z or quit to abort
\n
"
);
printf
(
"enter cpu clock frequency 400, 500, 533 M
H
z or quit to abort
\n
"
);
#endif
}
nbytes
=
readline
(
" ? "
);
...
...
@@ -130,11 +130,11 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
}
else
{
do
{
if
(
strcmp
(
cpuClock
,
"400"
)
==
0
)
printf
(
"enter plb clock frequency 100, 133 M
h
z or quit to abort
\n
"
);
printf
(
"enter plb clock frequency 100, 133 M
H
z or quit to abort
\n
"
);
#ifdef CONFIG_STRESS
if
(
strcmp
(
cpuClock
,
"667"
)
==
0
)
printf
(
"enter plb clock frequency 133, 166 M
h
z or quit to abort
\n
"
);
printf
(
"enter plb clock frequency 133, 166 M
H
z or quit to abort
\n
"
);
#endif
nbytes
=
readline
(
" ? "
);
...
...
@@ -160,7 +160,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
}
do
{
printf
(
"enter Pci-X clock frequency 33, 66, 100 or 133 M
h
z or quit to abort
\n
"
);
printf
(
"enter Pci-X clock frequency 33, 66, 100 or 133 M
H
z or quit to abort
\n
"
);
nbytes
=
readline
(
" ? "
);
if
(
strcmp
(
console_buffer
,
"quit"
)
==
0
)
...
...
@@ -176,10 +176,10 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
}
while
(
nbytes
==
0
);
printf
(
"
\n
sys clk = %s
Mh
z
\n
"
,
sysClock
);
printf
(
"cpu clk = %s
Mh
z
\n
"
,
cpuClock
);
printf
(
"plb clk = %s
Mh
z
\n
"
,
plbClock
);
printf
(
"Pci-X clk = %s
Mh
z
\n
"
,
pcixClock
);
printf
(
"
\n
sys clk = %s
MH
z
\n
"
,
sysClock
);
printf
(
"cpu clk = %s
MH
z
\n
"
,
cpuClock
);
printf
(
"plb clk = %s
MH
z
\n
"
,
plbClock
);
printf
(
"Pci-X clk = %s
MH
z
\n
"
,
pcixClock
);
do
{
printf
(
"
\n
press [y] to write I2C bootstrap
\n
"
);
...
...
board/bf537-stamp/post-memory.c
浏览文件 @
8ed44d91
...
...
@@ -27,18 +27,18 @@ const int pll[CCLK_NUM][SCLK_NUM][2] = {
{{
4
,
1
},
{
4
,
2
},
{
4
,
4
}}
/* CCLK = 100M */
};
const
char
*
const
log
[
CCLK_NUM
][
SCLK_NUM
]
=
{
{
"CCLK-500M
hz SCLK-125Mh
z: Writing...
\0
"
,
"CCLK-500M
hz SCLK-100Mh
z: Writing...
\0
"
,
"CCLK-500M
hz SCLK- 50Mh
z: Writing...
\0
"
,},
{
"CCLK-400M
hz SCLK-100Mh
z: Writing...
\0
"
,
"CCLK-400M
hz SCLK- 80Mh
z: Writing...
\0
"
,
"CCLK-400M
hz SCLK- 50Mh
z: Writing...
\0
"
,},
{
"CCLK-200M
hz SCLK-100Mh
z: Writing...
\0
"
,
"CCLK-200M
hz SCLK- 50Mh
z: Writing...
\0
"
,
"CCLK-200M
hz SCLK- 40Mh
z: Writing...
\0
"
,},
{
"CCLK-100M
hz SCLK-100Mh
z: Writing...
\0
"
,
"CCLK-100M
hz SCLK- 50Mh
z: Writing...
\0
"
,
"CCLK-100M
hz SCLK- 25Mh
z: Writing...
\0
"
,},
{
"CCLK-500M
Hz SCLK-125MH
z: Writing...
\0
"
,
"CCLK-500M
Hz SCLK-100MH
z: Writing...
\0
"
,
"CCLK-500M
Hz SCLK- 50MH
z: Writing...
\0
"
,},
{
"CCLK-400M
Hz SCLK-100MH
z: Writing...
\0
"
,
"CCLK-400M
Hz SCLK- 80MH
z: Writing...
\0
"
,
"CCLK-400M
Hz SCLK- 50MH
z: Writing...
\0
"
,},
{
"CCLK-200M
Hz SCLK-100MH
z: Writing...
\0
"
,
"CCLK-200M
Hz SCLK- 50MH
z: Writing...
\0
"
,
"CCLK-200M
Hz SCLK- 40MH
z: Writing...
\0
"
,},
{
"CCLK-100M
Hz SCLK-100MH
z: Writing...
\0
"
,
"CCLK-100M
Hz SCLK- 50MH
z: Writing...
\0
"
,
"CCLK-100M
Hz SCLK- 25MH
z: Writing...
\0
"
,},
};
int
memory_post_test
(
int
flags
)
...
...
board/cray/L1/L1.c
浏览文件 @
8ed44d91
...
...
@@ -205,13 +205,13 @@ static void init_sdram (void)
/* To set the appropriate timings, we need to know the SDRAM speed. */
/* We can use the PLB speed since the SDRAM speed is the same as */
/* the PLB speed. The PLB speed is the FBK divider times the */
/* 405GP reference clock, which on the L1 is 25M
h
z. */
/* Thus, if FBK div is 2, SDRAM is 50M
h
z; if FBK div is 3, SDRAM is */
/* 150M
hz; if FBK is 3, SDRAM is 150Mh
z. */
/* 405GP reference clock, which on the L1 is 25M
H
z. */
/* Thus, if FBK div is 2, SDRAM is 50M
H
z; if FBK div is 3, SDRAM is */
/* 150M
Hz; if FBK is 3, SDRAM is 150MH
z. */
/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
/* write SDRAM timing for 100M
h
z. */
/* write SDRAM timing for 100M
H
z. */
mtdcr
(
memcfga
,
mem_sdtr1
);
mtdcr
(
memcfgd
,
0x0086400D
);
...
...
board/eltec/bab7xx/misc.c
浏览文件 @
8ed44d91
...
...
@@ -377,7 +377,7 @@ int misc_init_r (void)
{
if
(
pci_find_device
(
PCI_VENDOR_ID_NCR
,
PCI_DEVICE_ID_NCR_53C860
,
0
)
>
0
)
{
/* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 M
h
z */
/* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 M
H
z */
scsi_dev_id
=
PCI_DEVICE_ID_NCR_53C860
;
scsi_max_scsi_id
=
7
;
scsi_sym53c8xx_ccf
=
0x15
;
...
...
board/esd/cpci750/pci.c
浏览文件 @
8ed44d91
...
...
@@ -66,13 +66,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host)
printf
(
"PCI %d bus mode: Conventional PCI
\n
"
,
host
);
break
;
case
1
:
printf
(
"PCI %d bus mode: 66 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 66 M
H
z PCIX
\n
"
,
host
);
break
;
case
2
:
printf
(
"PCI %d bus mode: 100 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 100 M
H
z PCIX
\n
"
,
host
);
break
;
case
3
:
printf
(
"PCI %d bus mode: 133 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 133 M
H
z PCIX
\n
"
,
host
);
break
;
default:
printf
(
"Unknown BUS %d
\n
"
,
mode
);
...
...
board/esd/pci405/pci405.c
浏览文件 @
8ed44d91
...
...
@@ -347,7 +347,7 @@ int checkboard (void)
if
(
value
)
{
puts
(
", 33 MHz PCI"
);
}
else
{
puts
(
", 66 M
h
z PCI"
);
puts
(
", 66 M
H
z PCI"
);
}
}
...
...
board/fads/fads.c
浏览文件 @
8ed44d91
...
...
@@ -449,19 +449,19 @@ static int _initsdram(uint base, uint noMbytes)
/* Now run the precharge/nop/mrs commands.
*/
memctl
->
memc_mcr
=
0x80808111
;
/* run umpb cs4 1 count 1, addr 0x11 ??? (50M
h
z) */
/* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100M
h
z) */
memctl
->
memc_mcr
=
0x80808111
;
/* run umpb cs4 1 count 1, addr 0x11 ??? (50M
H
z) */
/* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100M
H
z) */
udelay
(
200
);
/* Run 8 refresh cycles */
memctl
->
memc_mcr
=
SDRAM_MCRVALUE0
;
/* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 M
h
z)*/
memctl
->
memc_mcr
=
SDRAM_MCRVALUE0
;
/* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 M
H
z)*/
/* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */
udelay
(
200
);
memctl
->
memc_mbmr
=
SDRAM_MBMRVALUE1
;
/* TLF 4 (100 M
h
z) or TLF 8 (50MHz) */
memctl
->
memc_mcr
=
SDRAM_MCRVALUE1
;
/* run upmb cs4 loop 1 addr 0x30 refr (50 M
h
z) */
memctl
->
memc_mbmr
=
SDRAM_MBMRVALUE1
;
/* TLF 4 (100 M
H
z) or TLF 8 (50MHz) */
memctl
->
memc_mcr
=
SDRAM_MCRVALUE1
;
/* run upmb cs4 loop 1 addr 0x30 refr (50 M
H
z) */
/* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */
udelay
(
200
);
...
...
board/freescale/mpc8540ads/mpc8540ads.c
浏览文件 @
8ed44d91
...
...
@@ -127,8 +127,8 @@ local_bus_init(void)
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66M
h
z, DLL bypass mode must be used.
* If localbus freq is > 133M
h
z, DLL can be safely enabled.
* If localbus freq is < 66M
H
z, DLL bypass mode must be used.
* If localbus freq is > 133M
H
z, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
...
...
board/freescale/mpc8541cds/mpc8541cds.c
浏览文件 @
8ed44d91
...
...
@@ -302,8 +302,8 @@ local_bus_init(void)
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66M
h
z, DLL bypass mode must be used.
* If localbus freq is > 133M
h
z, DLL can be safely enabled.
* If localbus freq is < 66M
H
z, DLL bypass mode must be used.
* If localbus freq is > 133M
H
z, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
...
...
board/freescale/mpc8555cds/mpc8555cds.c
浏览文件 @
8ed44d91
...
...
@@ -302,8 +302,8 @@ local_bus_init(void)
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66M
h
z, DLL bypass mode must be used.
* If localbus freq is > 133M
h
z, DLL can be safely enabled.
* If localbus freq is < 66M
H
z, DLL bypass mode must be used.
* If localbus freq is > 133M
H
z, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
...
...
board/freescale/mpc8560ads/mpc8560ads.c
浏览文件 @
8ed44d91
...
...
@@ -331,8 +331,8 @@ local_bus_init(void)
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66M
h
z, DLL bypass mode must be used.
* If localbus freq is > 133M
h
z, DLL can be safely enabled.
* If localbus freq is < 66M
H
z, DLL bypass mode must be used.
* If localbus freq is > 133M
H
z, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
...
...
board/gen860t/beeper.c
浏览文件 @
8ed44d91
...
...
@@ -36,7 +36,7 @@
/*
* Initialize beeper-related hardware. Initialize timer 1 for use with
* the beeper. Use 66 M
h
z internal clock with prescale of 33 to get
* the beeper. Use 66 M
H
z internal clock with prescale of 33 to get
* 1 uS period per count.
* FIXME: we should really compute the prescale based on the reported
* core clock frequency.
...
...
board/idmr/idmr.c
浏览文件 @
8ed44d91
...
...
@@ -78,7 +78,7 @@ phys_size_t initdram (int board_type) {
MCF_GPIO_SDRAM_SDCS_01
);
/*
* Wait 100us. We run the bus at 50M
h
z, one cycle is 20ns. So 5
* Wait 100us. We run the bus at 50M
H
z, one cycle is 20ns. So 5
* iterations will do, but we do 10 just to be safe.
*/
for
(
i
=
0
;
i
<
10
;
++
i
)
...
...
board/motionpro/motionpro.c
浏览文件 @
8ed44d91
...
...
@@ -5,7 +5,7 @@
* modified for Promess PRO - by Andy Joseph, andy@promessdev.com
* modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
* modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
* Also changed the refresh for 100M
h
z operation
* Also changed the refresh for 100M
H
z operation
*
* See file CREDITS for list of people who contributed to this
* project.
...
...
board/mpc8540eval/mpc8540eval.c
浏览文件 @
8ed44d91
...
...
@@ -100,7 +100,7 @@ phys_size_t initdram (int board_type)
#if !defined(CONFIG_RAM_AS_FLASH)
/* LocalBus is not emulating flash */
get_sys_info
(
&
sysinfo
);
/* if localbus freq is less than 66M
h
z,we use bypass mode,otherwise use DLL */
/* if localbus freq is less than 66M
H
z,we use bypass mode,otherwise use DLL */
if
(
sysinfo
.
freqSystemBus
/
(
CONFIG_SYS_LBC_LCRR
&
0x0f
)
<
66000000
)
{
lbc
->
lcrr
=
(
CONFIG_SYS_LBC_LCRR
&
0x0fffffff
)
|
0x80000000
;
}
else
{
...
...
board/mpl/pip405/pip405.c
浏览文件 @
8ed44d91
...
...
@@ -252,7 +252,7 @@ int board_early_init_f (void)
(
datain
[
2
]
!=
0x04
)
||
/* if not SDRAM */
(
!
((
datain
[
6
]
==
0x40
)
||
(
datain
[
6
]
==
0x48
)))
||
/* or not (64 Bit or 72 Bit) */
(
datain
[
7
]
!=
0x00
)
||
(
datain
[
8
]
!=
0x01
)
||
/* or not LVTTL signal levels */
(
datain
[
126
]
==
0x66
))
/* or a 66M
h
z modules */
(
datain
[
126
]
==
0x66
))
/* or a 66M
H
z modules */
SDRAM_err
(
"unsupported SDRAM"
);
#ifdef SDRAM_DEBUG
serial_puts
(
"SDRAM sanity ok
\n
"
);
...
...
board/pm854/pm854.c
浏览文件 @
8ed44d91
...
...
@@ -144,8 +144,8 @@ local_bus_init(void)
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66M
h
z, DLL bypass mode must be used.
* If localbus freq is > 133M
h
z, DLL can be safely enabled.
* If localbus freq is < 66M
H
z, DLL bypass mode must be used.
* If localbus freq is > 133M
H
z, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
...
...
board/pm856/pm856.c
浏览文件 @
8ed44d91
...
...
@@ -300,8 +300,8 @@ local_bus_init(void)
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66M
h
z, DLL bypass mode must be used.
* If localbus freq is > 133M
h
z, DLL can be safely enabled.
* If localbus freq is < 66M
H
z, DLL bypass mode must be used.
* If localbus freq is > 133M
H
z, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
...
...
board/prodrive/p3mx/pci.c
浏览文件 @
8ed44d91
...
...
@@ -66,13 +66,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host)
printf
(
"PCI %d bus mode: Conventional PCI
\n
"
,
host
);
break
;
case
1
:
printf
(
"PCI %d bus mode: 66 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 66 M
H
z PCIX
\n
"
,
host
);
break
;
case
2
:
printf
(
"PCI %d bus mode: 100 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 100 M
H
z PCIX
\n
"
,
host
);
break
;
case
3
:
printf
(
"PCI %d bus mode: 133 M
h
z PCIX
\n
"
,
host
);
printf
(
"PCI %d bus mode: 133 M
H
z PCIX
\n
"
,
host
);
break
;
default:
printf
(
"Unknown BUS %d
\n
"
,
mode
);
...
...
board/sbc8560/sbc8560.c
浏览文件 @
8ed44d91
...
...
@@ -297,7 +297,7 @@ phys_size_t initdram (int board_type)
#if 0
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66M
h
z,we use bypass mode,otherwise use DLL */
/* if localbus freq is less than 66M
H
z,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
...
...
board/siemens/IAD210/IAD210.c
浏览文件 @
8ed44d91
...
...
@@ -240,7 +240,7 @@ int board_early_init_f (void)
iop
->
iop_padir
=
0x0800
;
/* start timer 2 for the 4hz LED blink rate */
timers
->
cpmt_tmr2
=
0xff2c
;
/* 4
hz for 64mh
z */
timers
->
cpmt_tmr2
=
0xff2c
;
/* 4
HZ for 64MH
z */
timers
->
cpmt_trr2
=
0x000003d0
;
/* clk/16 , prescale=256 */
timers
->
cpmt_tgcr
=
0x00000810
;
/* run timer 2 */
...
...
board/siemens/IAD210/atm.c
浏览文件 @
8ed44d91
...
...
@@ -579,7 +579,7 @@ void atmUtpInit()
/* 11 = divide by 7 */
/* */
/* Note that the UTOPIA clock must be programmed as to operate */
/* within the range SYSCLK/10 .. 50M
h
z. */
/* within the range SYSCLK/10 .. 50M
H
z. */
/*-----------------------------------------------------------------*/
car
->
car_sccr
&=
0xFFFFFFE0
;
car
->
car_sccr
|=
0x00000008
;
/* UTPCLK = SYSCLK / 4 */
...
...
board/tqc/tqm85xx/tqm85xx.c
浏览文件 @
8ed44d91
...
...
@@ -458,8 +458,8 @@ void local_bus_init (void)
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66M
h
z, DLL bypass mode must be used.
* If localbus freq is > 133M
h
z, DLL can be safely enabled.
* If localbus freq is < 66M
H
z, DLL bypass mode must be used.
* If localbus freq is > 133M
H
z, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
...
...
cpu/ixp/npe/miiphy.c
浏览文件 @
8ed44d91
...
...
@@ -32,7 +32,7 @@
| Date Description of Change BY
| --------- --------------------- ---
| 05-May-99 Created MKW
| 01-Jul-99 Changed clock setting of sta_reg from 66M
hz to 50Mh
z to
| 01-Jul-99 Changed clock setting of sta_reg from 66M
Hz to 50MH
z to
| better match OPB speed. Also modified delay times. JWB
| 29-Jul-99 Added Full duplex support MKW
| 24-Aug-99 Removed printf from dp83843_duplex() JWB
...
...
cpu/mips/incaip_clock.c
浏览文件 @
8ed44d91
...
...
@@ -33,8 +33,8 @@
*
* RETURNS:
* 150.000.000 for 150 MHz
* 133.333.333 for 133 M
h
z (= 400MHz/3)
* 100.000.000 for 100 M
h
z (= 400MHz/4)
* 133.333.333 for 133 M
H
z (= 400MHz/3)
* 100.000.000 for 100 M
H
z (= 400MHz/4)
* NOTE:
* This functions should be used by the hardware driver to get the correct
* frequency of the CPU. Don't use the macros, which are set to init the CPU
...
...
cpu/mpc8220/i2cCore.c
浏览文件 @
8ed44d91
...
...
@@ -440,7 +440,7 @@ STATUS i2c_write2byte (SI2C * pi2c, UINT16 * writeb)
return
OK
;
}
/* FDR table base on 33M
h
z - more detail please refer to Odini2c_dividers.xls
/* FDR table base on 33M
H
z - more detail please refer to Odini2c_dividers.xls
FDR FDR scl sda scl2tap2
510 432 tap tap tap tap scl_per sda_hold I2C Freq 0 1 2 3 4 5
000 000 9 3 4 1 28 Clocks 9 Clocks 1190 KHz 0 0 0 0 0 0
...
...
cpu/mpc83xx/spd_sdram.c
浏览文件 @
8ed44d91
...
...
@@ -314,7 +314,7 @@ long int spd_sdram()
+
(
spd
.
clk_cycle
&
0x0f
));
max_data_rate
=
max_bus_clk
*
2
;
debug
(
"DDR:Module maximum data rate is: %d
Mh
z
\n
"
,
max_data_rate
);
debug
(
"DDR:Module maximum data rate is: %d
MH
z
\n
"
,
max_data_rate
);
ddrc_clk
=
gd
->
mem_clk
/
1000000
;
effective_data_rate
=
0
;
...
...
@@ -401,7 +401,7 @@ long int spd_sdram()
}
}
debug
(
"DDR:Effective data rate is: %dM
h
z
\n
"
,
effective_data_rate
);
debug
(
"DDR:Effective data rate is: %dM
H
z
\n
"
,
effective_data_rate
);
debug
(
"DDR:The MSB 1 of CAS Latency is: %d
\n
"
,
caslat
);
/*
...
...
cpu/mpc8xx/fec.c
浏览文件 @
8ed44d91
...
...
@@ -398,7 +398,7 @@ static void fec_pin_init(int fecidx)
* * the MII management interface clock must be less than or equal
* * to 2.5 MHz.
* * This MDC frequency is equal to system clock / (2 * MII_SPEED).
* * Then MII_SPEED = system_clock / 2 * 2,5 M
h
z.
* * Then MII_SPEED = system_clock / 2 * 2,5 M
H
z.
*
* All MII configuration is done via FEC1 registers:
*/
...
...
cpu/mpc8xx/serial.c
浏览文件 @
8ed44d91
...
...
@@ -70,7 +70,7 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
int
divisor
=
(
gd
->
cpu_clk
+
8
*
gd
->
baudrate
)
/
16
/
gd
->
baudrate
;
if
(
divisor
/
16
>
0x1000
)
{
/* bad divisor, assume 50M
h
z clock and 9600 baud */
/* bad divisor, assume 50M
H
z clock and 9600 baud */
divisor
=
(
50
*
1000
*
1000
+
8
*
9600
)
/
16
/
9600
;
}
...
...
cpu/ppc4xx/4xx_pci.c
浏览文件 @
8ed44d91
...
...
@@ -286,7 +286,7 @@ void pci_405gp_init(struct pci_controller *hose)
#endif
/* CONFIG_SYS_PCI_CLASSCODE */
/*--------------------------------------------------------------------------+
* If PCI speed = 66M
hz, set 66Mh
z capable bit.
* If PCI speed = 66M
Hz, set 66MH
z capable bit.
*--------------------------------------------------------------------------*/
if
(
bd
->
bi_pci_busfreq
>=
66000000
)
{
pci_read_config_word
(
PCIDEVID_405GP
,
PCI_STATUS
,
&
temp_short
);
...
...
cpu/ppc4xx/miiphy.c
浏览文件 @
8ed44d91
...
...
@@ -301,7 +301,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
sta_reg
=
reg
;
/* reg address */
/* set clock (50M
h
z) and read flags */
/* set clock (50M
H
z) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
...
...
cpu/ppc4xx/speed.c
浏览文件 @
8ed44d91
...
...
@@ -148,7 +148,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
* is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
* to make sure it is within the proper range.
* spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
* Note freqVCO is calculated in M
h
z to avoid errors introduced by rounding.
* Note freqVCO is calculated in M
H
z to avoid errors introduced by rounding.
*/
if
(
sysInfo
->
pllFwdDiv
==
1
)
{
sysInfo
->
freqProcessor
=
CONFIG_SYS_CLK_FREQ
;
...
...
cpu/s3c44b0/cpu.c
浏览文件 @
8ed44d91
...
...
@@ -256,7 +256,7 @@ void i2c_init(int speed, int slaveaddr)
/*
Enable ACK, IICCLK=MCLK/16, enable interrupt
75M
h
z/16/(12+1) = 390625 Hz
75M
H
z/16/(12+1) = 390625 Hz
*/
rIICCON
=
(
1
<<
7
)
|
(
0
<<
6
)
|
(
1
<<
5
)
|
(
0xC
);
IICCON
=
rIICCON
;
...
...
drivers/block/sym53c8xx.c
浏览文件 @
8ed44d91
...
...
@@ -836,10 +836,10 @@ void scsi_chip_init(void)
scsi_write_byte
(
SCNTL0
,
0xC0
);
/* full arbitration no start, no message, parity disabled, master */
scsi_write_byte
(
SCNTL1
,
0x00
);
scsi_write_byte
(
SCNTL2
,
0x00
);
#ifndef CONFIG_SYS_SCSI_SYM53C8XX_CCF
/* config value for none 40
mh
z clocks */
#ifndef CONFIG_SYS_SCSI_SYM53C8XX_CCF
/* config value for none 40
MH
z clocks */
scsi_write_byte
(
SCNTL3
,
0x13
);
/* synchronous clock 40/4=10MHz, asynchronous 40MHz */
#else
scsi_write_byte
(
SCNTL3
,
CONFIG_SYS_SCSI_SYM53C8XX_CCF
);
/* config value for none 40
mh
z clocks */
scsi_write_byte
(
SCNTL3
,
CONFIG_SYS_SCSI_SYM53C8XX_CCF
);
/* config value for none 40
MH
z clocks */
#endif
scsi_write_byte
(
SCID
,
0x47
);
/* ID=7, enable reselection */
scsi_write_byte
(
SXFER
,
0x00
);
/* synchronous transfer period 10MHz, asynchronous */
...
...
drivers/i2c/omap1510_i2c.c
浏览文件 @
8ed44d91
...
...
@@ -32,7 +32,7 @@ void i2c_init (int speed, int slaveadd)
udelay
(
5000
);
}
/* 12M
h
z I2C module clock */
/* 12M
H
z I2C module clock */
outw
(
0
,
I2C_PSC
);
outw
(
I2C_CON_EN
,
I2C_CON
);
outw
(
0
,
I2C_SYSTEST
);
...
...
drivers/i2c/omap24xx_i2c.c
浏览文件 @
8ed44d91
...
...
@@ -45,7 +45,7 @@ void i2c_init (int speed, int slaveadd)
udelay
(
50000
);
}
/* 12M
h
z I2C module clock */
/* 12M
H
z I2C module clock */
outw
(
0
,
I2C_PSC
);
speed
=
speed
/
1000
;
/* 100 or 400 */
scl
=
((
12000
/
(
speed
*
2
))
-
7
);
/* use 7 when PSC = 0 */
...
...
drivers/net/natsemi.c
浏览文件 @
8ed44d91
...
...
@@ -409,7 +409,7 @@ natsemi_initialize(bd_t * bis)
The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
/* Delay between EEPROM clock transitions.
No extra delay is needed with 33M
hz PCI, but future 66Mh
z
No extra delay is needed with 33M
Hz PCI, but future 66MH
z
access may need a delay. */
#define eeprom_delay(ee_addr) INL(dev, ee_addr)
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...
drivers/net/ns8382x.c
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...
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@@ -445,7 +445,7 @@ ns8382x_initialize(bd_t * bis)
Read and write MII registers using software-generated serial MDIO
protocol. See the MII specifications or DP83840A data sheet for details.
The maximum data clock rate is 2.5 M
h
z. To meet minimum timing we
The maximum data clock rate is 2.5 M
H
z. To meet minimum timing we
must flush writes to the PCI bus with a PCI read. */
#define mdio_delay(mdio_addr) INL(dev, mdio_addr)
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drivers/net/rtl8139.c
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@@ -287,7 +287,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
/*
Delay between EEPROM clock transitions.
No extra delay is needed with 33M
hz PCI, but 66Mh
z may change this.
No extra delay is needed with 33M
Hz PCI, but 66MH
z may change this.
*/
#define eeprom_delay() inl(ee_addr)
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drivers/net/tigon3.c
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@@ -2247,7 +2247,7 @@ LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice)
REG_WR
(
pDevice
,
Grc
.
Mode
,
Value32
);
/* Setup the timer prescalar register. */
REG_WR
(
pDevice
,
Grc
.
MiscCfg
,
65
<<
1
);
/* Clock is alwasy 66M
h
z. */
REG_WR
(
pDevice
,
Grc
.
MiscCfg
,
65
<<
1
);
/* Clock is alwasy 66M
H
z. */
/* Set up the MBUF pool base address and size. */
REG_WR
(
pDevice
,
BufMgr
.
MbufPoolAddr
,
pDevice
->
MbufBase
);
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drivers/usb/usbdcore_mpc8xx.c
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@@ -1227,7 +1227,7 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr,
return
;
}
/* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48M
h
z)
/* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48M
H
z)
* but, can /probably/ live with close-ish alternative rates.
*/
divisor
=
(
gd
->
cpu_clk
/
48000000L
)
-
1
;
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