Merge git://git.denx.de/u-boot-mmc

board/samsung/common/exynos5-dt.c

@@ -93,6 +93,9 @@ int exynos_power_init(void)
 	struct udevice *dev;
 	int ret;
 
+#ifdef CONFIG_PMIC_S2MPS11
+	ret = pmic_get("s2mps11_pmic", &dev);
+#else
 	ret = pmic_get("max77686", &dev);
 	if (!ret) {
 		/* TODO(sjg@chromium.org): Move into the clock/pmic API */
@@ -112,6 +115,7 @@ int exynos_power_init(void)
 			s5m8767_enable_32khz_cp(dev);
 #endif
 	}
+#endif	/* CONFIG_PMIC_S2MPS11 */
 	if (ret == -ENODEV)
 		return 0;
 

drivers/mmc/mmc.c

@@ -1689,7 +1689,7 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
 
 #if CONFIG_IS_ENABLED(MMC_WRITE)
 				err = sd_read_ssr(mmc);
-				if (!err)
+				if (err)
 					pr_warn("unable to read ssr\n");
 #endif
 				if (!err)

drivers/mmc/sdhci.c

@@ -462,7 +462,8 @@ static int sdhci_set_ios(struct mmc *mmc)
 	else
 		ctrl &= ~SDHCI_CTRL_HISPD;
 
-	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
+	if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
+	    (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 		ctrl &= ~SDHCI_CTRL_HISPD;
 
 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
@@ -602,6 +603,11 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 			cfg->host_caps &= ~MMC_MODE_8BIT;
 	}
 
+	if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
+		cfg->host_caps &= ~MMC_MODE_HS;
+		cfg->host_caps &= ~MMC_MODE_HS_52MHz;
+	}
+
 	if (host->host_caps)
 		cfg->host_caps |= host->host_caps;
 

drivers/mmc/zynq_sdhci.c

@@ -54,7 +54,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
 		       SDHCI_QUIRK_BROKEN_R1B;
 
 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
-	host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+	host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
 #endif
 
 	host->max_clk = clock;

drivers/power/mfd/fg_max77693.c

@@ -60,8 +60,6 @@ static int power_update_battery(struct pmic *p, struct pmic *bat)
 		return ret;
 
 	max77693_get_vcell(&pb->bat->voltage_uV);
-	if (ret)
-		return ret;
 
 	return 0;
 }

include/sdhci.h

@@ -213,6 +213,12 @@
 #define SDHCI_QUIRK_BROKEN_R1B		(1 << 2)
 #define SDHCI_QUIRK_NO_HISPD_BIT	(1 << 3)
 #define SDHCI_QUIRK_BROKEN_VOLTAGE	(1 << 4)
+/*
+ * SDHCI_QUIRK_BROKEN_HISPD_MODE
+ * the hardware cannot operate correctly in high-speed mode,
+ * this quirk forces the sdhci host-controller to non high-speed mode
+ */
+#define SDHCI_QUIRK_BROKEN_HISPD_MODE	BIT(5)
 #define SDHCI_QUIRK_WAIT_SEND_CMD	(1 << 6)
 #define SDHCI_QUIRK_USE_WIDE8		(1 << 8)