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体验新版 GitCode,发现更多精彩内容 >>
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89d56f55
编写于
12月 13, 2008
作者:
W
Wolfgang Denk
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差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-ppc4xx
上级
3680aed0
19ef4f7a
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
25 addition
and
21 deletion
+25
-21
Makefile
Makefile
+1
-4
board/esd/cpci405/config.mk
board/esd/cpci405/config.mk
+1
-5
board/esd/pmc440/pmc440.c
board/esd/pmc440/pmc440.c
+19
-5
include/configs/CPCI405.h
include/configs/CPCI405.h
+3
-3
include/configs/alpr.h
include/configs/alpr.h
+1
-4
未找到文件。
Makefile
浏览文件 @
89d56f55
...
...
@@ -1261,14 +1261,11 @@ CMS700_config: unconfig
CPCI2DP_config
:
unconfig
@
$(MKCONFIG)
$
(
@:_config
=)
ppc ppc4xx cpci2dp esd
CPCI405_config
:
unconfig
@
$(MKCONFIG)
$
(
@:_config
=)
ppc ppc4xx cpci405 esd
CPCI405_config
\
CPCI4052_config
\
CPCI405DT_config
\
CPCI405AB_config
:
unconfig
@
mkdir
-p
$(obj)
board/esd/cpci405
@
echo
"TEXT_BASE = 0xFFFC0000"
>
$(obj)
board/esd/cpci405/config.tmp
@
$(MKCONFIG)
$
(
@:_config
=)
ppc ppc4xx cpci405 esd
CPCIISER4_config
:
unconfig
...
...
board/esd/cpci405/config.mk
浏览文件 @
89d56f55
...
...
@@ -21,8 +21,4 @@
# MA 02111-1307 USA
#
sinclude
$(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef
TEXT_BASE
TEXT_BASE
=
0xFFFD0000
endif
TEXT_BASE
=
0xFFFC0000
board/esd/pmc440/pmc440.c
浏览文件 @
89d56f55
...
...
@@ -107,7 +107,7 @@ int board_early_init_f(void)
* Setup the GPIO pins
* TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
*/
out32
(
GPIO0_OR
,
0x40000
0
02
);
out32
(
GPIO0_OR
,
0x40000
1
02
);
out32
(
GPIO0_TCR
,
0x4c90011f
);
out32
(
GPIO0_OSRL
,
0x28051400
);
out32
(
GPIO0_OSRH
,
0x55005000
);
...
...
@@ -755,17 +755,31 @@ int post_hotkeys_pressed(void)
#ifdef CONFIG_RESET_PHY_R
void
reset_phy
(
void
)
{
char
*
s
;
unsigned
short
val_method
,
val_behavior
;
/* special LED setup for NGCC/CANDES */
if
((
s
=
getenv
(
"bd_type"
))
&&
((
!
strcmp
(
s
,
"ngcc"
))
||
(
!
strcmp
(
s
,
"candes"
))))
{
val_method
=
0x0e0a
;
val_behavior
=
0x0cf2
;
}
else
{
/* PMC440 standard type */
val_method
=
0x0e10
;
val_behavior
=
0x0cf0
;
}
if
(
miiphy_write
(
"ppc_4xx_eth0"
,
CONFIG_PHY_ADDR
,
0x1f
,
0x0001
)
==
0
)
{
miiphy_write
(
"ppc_4xx_eth0"
,
CONFIG_PHY_ADDR
,
0x11
,
0x0010
);
miiphy_write
(
"ppc_4xx_eth0"
,
CONFIG_PHY_ADDR
,
0x11
,
0x0df0
);
miiphy_write
(
"ppc_4xx_eth0"
,
CONFIG_PHY_ADDR
,
0x10
,
0x0e10
);
miiphy_write
(
"ppc_4xx_eth0"
,
CONFIG_PHY_ADDR
,
0x11
,
val_behavior
);
miiphy_write
(
"ppc_4xx_eth0"
,
CONFIG_PHY_ADDR
,
0x10
,
val_method
);
miiphy_write
(
"ppc_4xx_eth0"
,
CONFIG_PHY_ADDR
,
0x1f
,
0x0000
);
}
if
(
miiphy_write
(
"ppc_4xx_eth1"
,
CONFIG_PHY1_ADDR
,
0x1f
,
0x0001
)
==
0
)
{
miiphy_write
(
"ppc_4xx_eth1"
,
CONFIG_PHY1_ADDR
,
0x11
,
0x0010
);
miiphy_write
(
"ppc_4xx_eth1"
,
CONFIG_PHY1_ADDR
,
0x11
,
0x0df0
);
miiphy_write
(
"ppc_4xx_eth1"
,
CONFIG_PHY1_ADDR
,
0x10
,
0x0e10
);
miiphy_write
(
"ppc_4xx_eth1"
,
CONFIG_PHY1_ADDR
,
0x11
,
val_behavior
);
miiphy_write
(
"ppc_4xx_eth1"
,
CONFIG_PHY1_ADDR
,
0x10
,
val_method
);
miiphy_write
(
"ppc_4xx_eth1"
,
CONFIG_PHY1_ADDR
,
0x1f
,
0x0000
);
}
}
...
...
include/configs/CPCI405.h
浏览文件 @
89d56f55
...
...
@@ -196,9 +196,9 @@
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE
0xFFFD0000
#define CONFIG_SYS_MONITOR_BASE
CONFIG_SYS_FLASH
_BASE
#define CONFIG_SYS_MONITOR_LEN (
192 * 1024)
/* Reserve 196 kB for Monitor */
#define CONFIG_SYS_FLASH_BASE
TEXT_BASE
#define CONFIG_SYS_MONITOR_BASE
TEXT
_BASE
#define CONFIG_SYS_MONITOR_LEN (
~(TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/* Reserve 128 kB for malloc() */
/*
...
...
include/configs/alpr.h
浏览文件 @
89d56f55
...
...
@@ -235,18 +235,15 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_NFS
#undef CONFIG_WATCHDOG
/* watchdog disabled */
...
...
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