x86: Rename existing FSP code to fsp1

Since there is now a new version of the FSP and it is incompatible with
the existing version, move the code into an fsp1 directory. This will
allow us to put FSP v2 code into an fsp2 directory.

Add a Kconfig which defines which version is in use.

Some of the code in this new fsp1/ directory is generic across both FSPv1
and FSPv2. Future patches will address this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

arch/x86/Kconfig

@@ -364,6 +364,29 @@ config HAVE_FSP
 	  Note: Without this binary U-Boot will not be able to set up its
 	  SDRAM so will not boot.
 
+choice
+	prompt "FSP version"
+	depends on HAVE_FSP
+	default FSP_VERSION1
+	help
+	  Selects the FSP version to use. Intel has published several versions
+	  of the FSP External Architecture Specification and this allows
+	  selection of the version number used by a particular SoC.
+
+config FSP_VERSION1
+	bool "FSP version 1.x"
+	help
+	  This covers versions 1.0 and 1.1a. See here for details:
+	  https://github.com/IntelFsp/fsp/wiki
+
+config FSP_VERSION2
+	bool "FSP version 2.x"
+	help
+	  This covers versions 2.0 and 2.1. See here for details:
+	  https://github.com/IntelFsp/fsp/wiki
+
+endchoice
+
 config FSP_FILE
 	string "Firmware Support Package binary filename"
 	depends on HAVE_FSP
@@ -429,7 +452,7 @@ config ENABLE_MRC_CACHE
 
 	  For platforms that use Intel FSP for the memory initialization,
 	  please check FSP output HOB via U-Boot command 'fsp hob' to see
-	  if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
+	  if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
 	  If such GUID does not exist, MRC cache is not available on such
 	  platform (eg: Intel Queensbay), which means selecting this option
 	  here does not make any difference.

arch/x86/cpu/baytrail/acpi.c

@@ -167,7 +167,7 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
  * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses
  * of these two blocks are programmed by either U-Boot or FSP.
  *
- * It has been verified that 1st phase API (see arch/x86/lib/fsp/fsp_car.S)
+ * It has been verified that 1st phase API (see arch/x86/lib/fsp1/fsp_car.S)
  * on Intel BayTrail SoC already initializes these two base addresses so
  * we are safe to access these registers here.
  */

arch/x86/cpu/baytrail/fsp_configs.c

@@ -7,7 +7,7 @@
 
 #include <common.h>
 #include <fdtdec.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

arch/x86/cpu/braswell/fsp_configs.c

@@ -5,7 +5,7 @@
 
 #include <common.h>
 #include <fdtdec.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

arch/x86/cpu/ivybridge/fsp_configs.c

@@ -5,7 +5,7 @@
 
 #include <common.h>
 #include <fdtdec.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

arch/x86/cpu/queensbay/fsp_configs.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 
 void update_fsp_configs(struct fsp_config_data *config,
 			struct fspinit_rtbuf *rt_buf)

arch/x86/cpu/queensbay/tnc.c

@@ -12,7 +12,7 @@
 #include <asm/post.h>
 #include <asm/arch/device.h>
 #include <asm/arch/tnc.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 #include <asm/processor.h>
 
 static int __maybe_unused disable_igd(void)

arch/x86/include/asm/u-boot-x86.h

@@ -74,7 +74,7 @@ u32 isa_map_rom(u32 bus_addr, int size);
 /* arch/x86/lib/... */
 int video_bios_init(void);
 
-/* arch/x86/lib/fsp/... */
+/* arch/x86/lib/fsp1,2/... */
 
 /**
  * fsp_save_s3_stack() - save stack address to CMOS for next S3 boot

arch/x86/lib/Makefile

@@ -43,7 +43,8 @@ ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_ZBOOT)	+= zimage.o
 endif
 obj-$(CONFIG_USE_HOB) += hob.o
-obj-$(CONFIG_HAVE_FSP) += fsp/
+obj-$(CONFIG_FSP_VERSION1) += fsp1/
+obj-$(CONFIG_FSP_VERSION2) += fsp2/
 
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TPL_BUILD

arch/x86/lib/fsp/fsp_common.c → arch/x86/lib/fsp1/fsp_common.c

@@ -14,7 +14,7 @@
 #include <asm/mrccache.h>
 #include <asm/post.h>
 #include <asm/processor.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

arch/x86/lib/fsp/fsp_dram.c → arch/x86/lib/fsp1/fsp_dram.c

@@ -4,7 +4,7 @@
  */
 
 #include <common.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 #include <asm/e820.h>
 #include <asm/mrccache.h>
 #include <asm/post.h>

arch/x86/lib/fsp/fsp_graphics.c → arch/x86/lib/fsp1/fsp_graphics.c

@@ -7,7 +7,7 @@
 #include <dm.h>
 #include <vbe.h>
 #include <video.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

arch/x86/lib/fsp/fsp_support.c → arch/x86/lib/fsp1/fsp_support.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 #include <asm/post.h>
 
 struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void)

board/advantech/som-db5800-som-6867/som-db5800-som-6867.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 
 /* ALC262 Verb Table - 10EC0262 */
 static const u32 verb_table_data13[] = {

board/intel/cherryhill/cherryhill.c

@@ -5,7 +5,7 @@
 
 #include <common.h>
 #include <asm/arch/gpio.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 
 static const struct gpio_family gpio_family[] = {
 	GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,

cmd/x86/fsp.c

@@ -5,7 +5,7 @@
 
 #include <common.h>
 #include <command.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

drivers/pci/pci-uclass.c

@@ -12,7 +12,7 @@
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
 #endif
 #include "pci_internal.h"