Merge branch 'master' of git://git.denx.de/u-boot-video

Makefile

@@ -3029,8 +3029,12 @@ apollon_config		: unconfig
 imx31_litekit_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
 
+imx31_phycore_eet_config \
 imx31_phycore_config	: unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+	@if [ -n "$(findstring _eet_,$@)" ]; then			\
+		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
+	fi
+	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
 
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31

board/imx31_phycore/imx31_phycore.c

@@ -23,6 +23,7 @@
 
 
 #include <common.h>
+#include <s6e63d6.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
 
@@ -66,6 +67,62 @@ int board_init (void)
 	return 0;
 }
 
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_S6E63D6
+	struct s6e63d6 data = {
+		/*
+		 * See comment in mxc_spi.c::decode_cs() for .cs field format.
+		 * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
+		 * 2 of the SPI controller #1, since it is unused.
+		 */
+		.cs = 2 | (57 << 8),
+		.bus = 0,
+		.id = 0,
+	};
+	int ret;
+
+	/* SPI1 */
+	mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
+	mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
+	mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
+	mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
+	mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
+	mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
+
+	/* start SPI1 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
+
+	/* GPIO 57 */
+	/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
+	mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
+
+	/* SPI1 CS2 is free */
+	ret = s6e63d6_init(&data);
+	if (ret)
+		return ret;
+
+	/*
+	 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
+	 * OLED display connected to a S6E63D6 SPI display controller in the
+	 * 18 bit RGB mode
+	 */
+	s6e63d6_index(&data, 2);
+	s6e63d6_param(&data, 0x0182);
+	s6e63d6_index(&data, 3);
+	s6e63d6_param(&data, 0x8130);
+	s6e63d6_index(&data, 0x10);
+	s6e63d6_param(&data, 0x0000);
+	s6e63d6_index(&data, 5);
+	s6e63d6_param(&data, 0x0001);
+	s6e63d6_index(&data, 0x22);
+#endif
+	return 0;
+}
+#endif
+
 int checkboard (void)
 {
 	printf("Board: Phytec phyCore i.MX31\n");

common/lcd.c

@@ -84,7 +84,7 @@ extern void lcd_enable (void);
 static void *lcd_logo (void);
 
 
-#if LCD_BPP == LCD_COLOR8
+#if (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
 extern void lcd_setcolreg (ushort regno,
 				ushort red, ushort green, ushort blue);
 #endif
@@ -622,19 +622,15 @@ void bitmap_plot (int x, int y)
  */
 int lcd_display_bitmap(ulong bmp_image, int x, int y)
 {
-#ifdef CONFIG_ATMEL_LCD
-	uint *cmap;
-#elif !defined(CONFIG_MCC200)
-	ushort *cmap;
-#endif
+	ushort *cmap = NULL, *cmap_base = NULL;
 	ushort i, j;
 	uchar *fb;
 	bmp_image_t *bmp=(bmp_image_t *)bmp_image;
 	uchar *bmap;
 	ushort padded_line;
-	unsigned long width, height;
+	unsigned long width, height, byte_width;
 	unsigned long pwidth = panel_info.vl_col;
-	unsigned colors,bpix;
+	unsigned colors, bpix, bmp_bpix;
 	unsigned long compression;
 #if defined(CONFIG_PXA250)
 	struct pxafb_info *fbi = &panel_info.pxa;
@@ -647,22 +643,24 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		(bmp->header.signature[1]=='M'))) {
 		printf ("Error: no valid bmp image at %lx\n", bmp_image);
 		return 1;
-}
+	}
 
 	width = le32_to_cpu (bmp->header.width);
 	height = le32_to_cpu (bmp->header.height);
-	colors = 1<<le16_to_cpu (bmp->header.bit_count);
+	bmp_bpix = le16_to_cpu(bmp->header.bit_count);
+	colors = 1 << bmp_bpix;
 	compression = le32_to_cpu (bmp->header.compression);
 
 	bpix = NBITS(panel_info.vl_bpix);
 
-	if ((bpix != 1) && (bpix != 8)) {
-		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
-			bpix);
+	if ((bpix != 1) && (bpix != 8) && (bpix != 16)) {
+		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
+			bpix, bmp_bpix);
 		return 1;
 	}
 
-	if (bpix != le16_to_cpu(bmp->header.bit_count)) {
+	/* We support displaying 8bpp BMPs on 16bpp LCDs */
+	if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16)) {
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
 			bpix,
 			le16_to_cpu(bmp->header.bit_count));
@@ -674,17 +672,17 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 #if !defined(CONFIG_MCC200)
 	/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
-	if (bpix==8) {
+	if (bmp_bpix == 8) {
 #if defined(CONFIG_PXA250)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
-#elif defined(CONFIG_ATMEL_LCD)
-		cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
-#else
-# error "Don't know location of color map"
+#elif !defined(CONFIG_ATMEL_LCD)
+		cmap = panel_info.cmap;
 #endif
 
+		cmap_base = cmap;
+
 		/* Set color map */
 		for (i=0; i<colors; ++i) {
 			bmp_color_table_entry_t cte = bmp->color_table[i];
@@ -698,10 +696,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 #else
 			*cmap = colreg;
 #endif
-#if defined(CONFIG_PXA250)
-			cmap++;
-#elif defined(CONFIG_MPC823)
+#if defined(CONFIG_MPC823)
 			cmap--;
+#else
+			cmap++;
 #endif
 #else /* CONFIG_ATMEL_LCD */
 			lcd_setcolreg(i, cte.red, cte.green, cte.blue);
@@ -738,17 +736,59 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
-	for (i = 0; i < height; ++i) {
-		WATCHDOG_RESET();
-		for (j = 0; j < width ; j++)
+
+	switch (bmp_bpix) {
+	case 1: /* pass through */
+	case 8:
+		if (bpix != 16)
+			byte_width = width;
+		else
+			byte_width = width * 2;
+
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width; j++) {
+				if (bpix != 16) {
 #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
-			*(fb++) = *(bmap++);
+					*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
-			*(fb++)=255-*(bmap++);
+					*(fb++) = 255 - *(bmap++);
 #endif
-		bmap += (width - padded_line);
-		fb   -= (width + lcd_line_length);
-	}
+				} else {
+					*(uint16_t *)fb = cmap_base[*(bmap++)];
+					fb += sizeof(uint16_t) / sizeof(*fb);
+				}
+			}
+			bmap += (width - padded_line);
+			fb   -= (byte_width + lcd_line_length);
+		}
+		break;
+
+#if defined(CONFIG_BMP_16BPP)
+	case 16:
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width; j++) {
+#if defined(CONFIG_ATMEL_LCD_BGR555)
+				*(fb++) = ((bmap[0] & 0x1f) << 2) |
+					(bmap[1] & 0x03);
+				*(fb++) = (bmap[0] & 0xe0) |
+					((bmap[1] & 0x7c) >> 2);
+				bmap += 2;
+#else
+				*(fb++) = *(bmap++);
+				*(fb++) = *(bmap++);
+#endif
+			}
+			bmap += (padded_line - width) * 2;
+			fb   -= (width * 2 + lcd_line_length);
+		}
+		break;
+#endif /* CONFIG_BMP_16BPP */
+
+	default:
+		break;
+	};
 
 	return (0);
 }

drivers/gpio/Makefile

@@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB 	:= $(obj)libgpio.a
 
-COBJS-$(CONFIG_PCA953X)	+= pca953x.o
+COBJS-$(CONFIG_MX31_GPIO)	+= mx31_gpio.o
+COBJS-$(CONFIG_PCA953X)		+= pca953x.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)

drivers/gpio/mx31_gpio.c

+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+/* GPIO port description */
+static unsigned long gpio_ports[] = {
+	[0] = GPIO1_BASE,
+	[1] = GPIO2_BASE,
+	[2] = GPIO3_BASE,
+};
+
+int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port >= ARRAY_SIZE(gpio_ports))
+		return 1;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + GPIO_GDIR);
+	switch (direction) {
+	case MX31_GPIO_DIRECTION_OUT:
+		l |= 1 << gpio;
+		break;
+	case MX31_GPIO_DIRECTION_IN:
+		l &= ~(1 << gpio);
+	}
+	__REG(gpio_ports[port] + GPIO_GDIR) = l;
+
+	return 0;
+}
+
+void mx31_gpio_set(unsigned int gpio, unsigned int value)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port >= ARRAY_SIZE(gpio_ports))
+		return;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + GPIO_DR);
+	if (value)
+		l |= 1 << gpio;
+	else
+		l &= ~(1 << gpio);
+	__REG(gpio_ports[port] + GPIO_DR) = l;
+}

drivers/spi/mxc_spi.c

@@ -21,6 +21,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <spi.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 
 #ifdef CONFIG_MX27
@@ -32,6 +33,8 @@
 
 #else
 
+#include <asm/arch/mx31.h>
+
 #define MXC_CSPIRXDATA		0x00
 #define MXC_CSPITXDATA		0x04
 #define MXC_CSPICTRL		0x08
@@ -68,6 +71,7 @@ struct mxc_spi_slave {
 	struct spi_slave slave;
 	unsigned long	base;
 	u32		ctrl_reg;
+	int		gpio;
 };
 
 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -85,26 +89,33 @@ static inline void reg_write(unsigned long addr, u32 val)
 	*(volatile unsigned long*)addr = val;
 }
 
-static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
+static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
+			   unsigned long flags)
 {
 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
 
-	if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) {
-		cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
-			MXC_CSPICTRL_BITCOUNT(bitlen - 1);
-		reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
-	}
+	mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
+		MXC_CSPICTRL_BITCOUNT(bitlen - 1);
 
-	reg_write(mxcs->base + MXC_CSPITXDATA, data);
+	if (cfg_reg != mxcs->ctrl_reg)
+		reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
 
-	cfg_reg |= MXC_CSPICTRL_XCH;
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
+		mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
 
-	reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
+	reg_write(mxcs->base + MXC_CSPITXDATA, data);
+
+	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH);
 
 	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
 		;
 
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) {
+		mx31_gpio_set(mxcs->gpio,
+			      !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+	}
+
 	return reg_read(mxcs->base + MXC_CSPIRXDATA);
 }
 
@@ -122,8 +133,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
 	     i < n_blks;
-	     i++, in_l++, out_l++, bitlen -= 32)
-		*in_l = spi_xchg_single(slave, *out_l, bitlen);
+	     i++, in_l++, out_l++, bitlen -= 32) {
+		u32 data = spi_xchg_single(slave, *out_l, bitlen, flags);
+
+		/* Check if we're only transfering 8 or 16 bits */
+		if (!i) {
+			if (bitlen < 9)
+				*(u8 *)din = data;
+			else if (bitlen < 17)
+				*(u16 *)din = data;
+		}
+	}
 
 	return 0;
 }
@@ -132,16 +152,55 @@ void spi_init(void)
 {
 }
 
+static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
+{
+	int ret;
+
+	/*
+	 * Some SPI devices require active chip-select over multiple
+	 * transactions, we achieve this using a GPIO. Still, the SPI
+	 * controller has to be configured to use one of its own chipselects.
+	 * To use this feature you have to call spi_setup_slave() with
+	 * cs = internal_cs | (gpio << 8), and you have to use some unused
+	 * on this SPI controller cs between 0 and 3.
+	 */
+	if (cs > 3) {
+		mxcs->gpio = cs >> 8;
+		cs &= 3;
+		ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
+		if (ret) {
+			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
+			return -EINVAL;
+		}
+	} else {
+		mxcs->gpio = -1;
+	}
+
+	return cs;
+}
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 			unsigned int max_hz, unsigned int mode)
 {
 	unsigned int ctrl_reg;
 	struct mxc_spi_slave *mxcs;
+	int ret;
 
-	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
-	    cs > 3)
+	if (bus >= ARRAY_SIZE(spi_bases))
 		return NULL;
 
+	mxcs = malloc(sizeof(struct mxc_spi_slave));
+	if (!mxcs)
+		return NULL;
+
+	ret = decode_cs(mxcs, cs);
+	if (ret < 0) {
+		free(mxcs);
+		return NULL;
+	}
+
+	cs = ret;
+
 	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 		MXC_CSPICTRL_BITCOUNT(31) |
 		MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
@@ -155,10 +214,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (mode & SPI_CS_HIGH)
 		ctrl_reg |= MXC_CSPICTRL_SSPOL;
 
-	mxcs = malloc(sizeof(struct mxc_spi_slave));
-	if (!mxcs)
-		return NULL;
-
 	mxcs->slave.bus = bus;
 	mxcs->slave.cs = cs;
 	mxcs->base = spi_bases[bus];
@@ -169,7 +224,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
 void spi_free_slave(struct spi_slave *slave)
 {
-	free(slave);
+	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+
+	free(mxcs);
 }
 
 int spi_claim_bus(struct spi_slave *slave)

drivers/video/Makefile

@@ -28,8 +28,10 @@ LIB	:= $(obj)libvideo.a
 COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o
 COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o
+COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o

drivers/video/s6e63d6.c

+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <spi.h>
+#include <s6e63d6.h>
+
+/*
+ * Each transfer is performed as:
+ * 1. chip-select active
+ * 2. send 8-bit start code
+ * 3. send 16-bit data
+ * 4. chip-select inactive
+ */
+static int send_word(struct s6e63d6 *data, u8 rs, u16 word)
+{
+	/*
+	 * The start byte looks like (binary):
+	 * 01110<ID><RS><R/W>
+	 * RS is 0 for index or 1 for data, and R/W is 0 for write.
+	 */
+	u32 buf8 = 0x70 | data->id | (rs & 2);
+	u32 buf16 = cpu_to_le16(word);
+	u32 buf_in;
+	int err;
+
+	err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
+	if (err)
+		return err;
+
+	return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END);
+}
+
+/* Index and param differ in Register Select bit */
+int s6e63d6_index(struct s6e63d6 *data, u8 idx)
+{
+	return send_word(data, 0, idx);
+}
+
+int s6e63d6_param(struct s6e63d6 *data, u16 param)
+{
+	return send_word(data, 2, param);
+}
+
+int s6e63d6_init(struct s6e63d6 *data)
+{
+	if (data->id != 0 && data->id != 4) {
+		printf("s6e63d6: invalid ID %u\n", data->id);
+		return 1;
+	}
+
+	data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
+	if (!data->slave)
+		return 1;
+
+	return 0;
+}

include/asm-arm/arch-mx31/mx31-regs.h

@@ -134,7 +134,14 @@
 #define MUX_CTL_CSPI2_SS0	0x85
 #define MUX_CTL_CSPI2_SS1	0x86
 #define MUX_CTL_CSPI2_SS2	0x87
+#define MUX_CTL_CSPI1_SS2	0x88
+#define MUX_CTL_CSPI1_SCLK	0x89
+#define MUX_CTL_CSPI1_SPI_RDY	0x8a
 #define MUX_CTL_CSPI2_MOSI	0x8b
+#define MUX_CTL_CSPI1_MOSI	0x8c
+#define MUX_CTL_CSPI1_MISO	0x8d
+#define MUX_CTL_CSPI1_SS0	0x8e
+#define MUX_CTL_CSPI1_SS1	0x8f
 
 /*
  * Helper macros for the MUX_[contact name]__[pin function] macros
@@ -160,6 +167,15 @@
 	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
 
+#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
+
 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 

include/asm-arm/arch-mx31/mx31.h

@@ -27,4 +27,24 @@
 extern u32 mx31_get_ipg_clk(void);
 extern void mx31_gpio_mux(unsigned long mode);
 
+enum mx31_gpio_direction {
+	MX31_GPIO_DIRECTION_IN,
+	MX31_GPIO_DIRECTION_OUT,
+};
+
+#ifdef CONFIG_MX31_GPIO
+extern int mx31_gpio_direction(unsigned int gpio,
+			       enum mx31_gpio_direction direction);
+extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
+#else
+static inline int mx31_gpio_direction(unsigned int gpio,
+				      enum mx31_gpio_direction direction)
+{
+	return 1;
+}
+static inline void mx31_gpio_set(unsigned int gpio, unsigned int value)
+{
+}
+#endif
+
 #endif /* __ASM_ARCH_MX31_H */

include/configs/imx31_phycore.h

@@ -178,4 +178,27 @@
 #undef CONFIG_JFFS2_CMDLINE
 #define CONFIG_JFFS2_DEV	"nor0"
 
+/* EET platform additions */
+#ifdef CONFIG_IMX31_PHYCORE_EET
+#define BOARD_LATE_INIT
+
+#define CONFIG_MX31_GPIO			1
+
+#define CONFIG_HARD_SPI				1
+#define CONFIG_MXC_SPI				1
+#define CONFIG_CMD_SPI
+
+#define CONFIG_S6E63D6				1
+
+#define CONFIG_LCD				1
+#define CONFIG_VIDEO_MX3			1
+#define CONFIG_SYS_WHITE_ON_BLACK		1
+#define LCD_BPP					LCD_COLOR8
+#define	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+
+#define	CONFIG_SPLASH_SCREEN			1
+#define CONFIG_CMD_BMP				1
+#endif
+
 #endif /* __CONFIG_H */

include/lcd.h

@@ -148,14 +148,6 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
-#elif defined(CONFIG_MCC200)
-typedef struct vidinfo {
-	ushort	vl_col;		/* Number of columns (i.e. 160) */
-	ushort	vl_row;		/* Number of rows (i.e. 100) */
-
-	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
-} vidinfo_t;
-
 #elif defined(CONFIG_ATMEL_LCD)
 
 typedef struct vidinfo {
@@ -183,6 +175,19 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
+#else
+
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 160) */
+	ushort	vl_row;		/* Number of rows (i.e. 100) */
+
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
+
+	ushort	*cmap;		/* Pointer to the colormap */
+
+	void	*priv;		/* Pointer to driver-specific data */
+} vidinfo_t;
+
 #endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
 
 /* Video functions */

include/s6e63d6.h

+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _S6E63D6_H_
+#define _S6E63D6_H_
+
+struct s6e63d6 {
+	unsigned int bus;
+	unsigned int cs;
+	unsigned int id;
+	struct spi_slave *slave;
+};
+
+extern int s6e63d6_init(struct s6e63d6 *data);
+extern int s6e63d6_index(struct s6e63d6 *data, u8 idx);
+extern int s6e63d6_param(struct s6e63d6 *data, u16 param);
+
+#endif