ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports

This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].

The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus
Signed-off-by: NStefan Roese <sr@denx.de>

board/amcc/taihu/taihu.c

@@ -78,15 +78,6 @@ int checkboard(void)
 	return 0;
 }
 
-/*************************************************************************
- *  phys_size_t initdram
- *
- ************************************************************************/
-phys_size_t initdram(int board)
-{
-	return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
-}
-
 static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
 {
 	char stat;

board/dave/PPChameleonEVB/PPChameleonEVB.c

@@ -203,31 +203,6 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-phys_size_t initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-#if 0 /* test-only */
-	for (;;) {
-		NAND_DISABLE_CE(1);
-		udelay(100);
-		NAND_ENABLE_CE(1);
-		udelay(100);
-	}
-#endif
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
 int testdram (void)
 {
 	/* TODO: XXX XXX XXX */

board/esd/pci405/pci405.c

@@ -356,37 +356,6 @@ int checkboard (void)
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
-#if 0 /* test-only: all PCI405 version must report 16mb */
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-#else
-	return (16*1024*1024);
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
 /* ------------------------------------------------------------------------- */
 int wpeeprom(int wp)
 {

board/quad100hd/quad100hd.c

@@ -86,8 +86,3 @@ int checkboard(void)
 
 	return 0;
 }
-
-phys_size_t initdram(int board_type)
-{
-	return CFG_SDRAM_SIZE;
-}

board/zeus/zeus.c

@@ -190,29 +190,6 @@ int checkboard(void)
 	return (0);
 }
 
-static u32 detect_sdram_size(void)
-{
-	u32 val;
-	u32 size;
-
-	mfsdram(mem_mb0cf, val);
-	size = (4 << 20) << ((val & 0x000e0000) >> 17);
-
-	/*
-	 * Check if 2nd bank is enabled too
-	 */
-	mfsdram(mem_mb1cf, val);
-	if (val & 1)
-		size += (4 << 20) << ((val & 0x000e0000) >> 17);
-
-	return size;
-}
-
-phys_size_t initdram (int board_type)
-{
-	return detect_sdram_size();
-}
-
 static int default_env_var(char *buf, char *var)
 {
 	char *ptr;

cpu/ppc4xx/sdram.c

@@ -209,15 +209,15 @@ phys_size_t initdram(int board_type)
 		udelay(10000);
 
 		if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+			phys_size_t size = mb0cf[i].size;
+
 			/*
 			 * OK, size detected.  Enable second bank if
 			 * defined (assumes same type as bank 0)
 			 */
 #ifdef CONFIG_SDRAM_BANK1
-			u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
-
 			mtsdram(mem_mcopt1, 0x00000000);
-			mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
+			mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
 			mtsdram(mem_mcopt1, 0x80800000);
 			udelay(10000);
 
@@ -230,13 +230,19 @@ phys_size_t initdram(int board_type)
 			    mb0cf[i].size) {
 				mtsdram(mem_mb1cf, 0);
 				mtsdram(mem_mcopt1, 0);
+			} else {
+				/*
+				 * We have two identical banks, so the size
+				 * is twice the bank size
+				 */
+				size = 2 * size;
 			}
 #endif
 
 			/*
 			 * OK, size detected -> all done
 			 */
-			return mb0cf[i].size;
+			return size;
 		}
 	}
 

include/configs/quad100hd.h

@@ -82,7 +82,6 @@
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  */
 #define CONFIG_SDRAM_BANK0  1
-#define CFG_SDRAM_SIZE      0x02000000      /* 32 MB */
 
 /* FIX! SDRAM timings used in datasheet */
 #define CFG_SDRAM_CL            3       /* CAS latency */