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体验新版 GitCode,发现更多精彩内容 >>
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77b25175
编写于
11月 21, 2009
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'next' of
git://www.denx.de/git/u-boot-ppc4xx
into next
上级
1d2e96de
14ce02c8
变更
35
隐藏空白更改
内联
并排
Showing
35 changed file
with
272 addition
and
2041 deletion
+272
-2041
board/amcc/bamboo/bamboo.c
board/amcc/bamboo/bamboo.c
+0
-137
board/amcc/canyonlands/canyonlands.c
board/amcc/canyonlands/canyonlands.c
+0
-37
board/amcc/ebony/ebony.c
board/amcc/ebony/ebony.c
+0
-70
board/amcc/katmai/katmai.c
board/amcc/katmai/katmai.c
+1
-70
board/amcc/kilauea/kilauea.c
board/amcc/kilauea/kilauea.c
+0
-19
board/amcc/luan/luan.c
board/amcc/luan/luan.c
+0
-73
board/amcc/makalu/makalu.c
board/amcc/makalu/makalu.c
+0
-19
board/amcc/ocotea/ocotea.c
board/amcc/ocotea/ocotea.c
+0
-72
board/amcc/sequoia/sequoia.c
board/amcc/sequoia/sequoia.c
+1
-140
board/amcc/taishan/taishan.c
board/amcc/taishan/taishan.c
+0
-70
board/amcc/yosemite/yosemite.c
board/amcc/yosemite/yosemite.c
+0
-137
board/amcc/yucca/yucca.c
board/amcc/yucca/yucca.c
+0
-69
board/esd/du440/du440.c
board/esd/du440/du440.c
+0
-138
board/esd/du440/du440.h
board/esd/du440/du440.h
+0
-3
board/esd/pmc440/config.mk
board/esd/pmc440/config.mk
+0
-4
board/esd/pmc440/pmc440.c
board/esd/pmc440/pmc440.c
+7
-71
board/gdsys/gdppc440etx/gdppc440etx.c
board/gdsys/gdppc440etx/gdppc440etx.c
+4
-129
board/gdsys/intip/intip.c
board/gdsys/intip/intip.c
+0
-37
board/korat/korat.c
board/korat/korat.c
+4
-130
board/lwmon5/lwmon5.c
board/lwmon5/lwmon5.c
+0
-137
board/netstal/hcu5/hcu5.c
board/netstal/hcu5/hcu5.c
+7
-79
board/pcs440ep/pcs440ep.c
board/pcs440ep/pcs440ep.c
+0
-137
board/prodrive/alpr/alpr.c
board/prodrive/alpr/alpr.c
+7
-66
board/prodrive/p3p440/p3p440.c
board/prodrive/p3p440/p3p440.c
+0
-70
board/sandburst/common/sb_common.c
board/sandburst/common/sb_common.c
+0
-72
board/xes/xpedite1000/xpedite1000.c
board/xes/xpedite1000/xpedite1000.c
+2
-33
cpu/ppc4xx/4xx_pci.c
cpu/ppc4xx/4xx_pci.c
+219
-14
cpu/ppc4xx/cpu.c
cpu/ppc4xx/cpu.c
+1
-1
include/asm-ppc/4xx_pci.h
include/asm-ppc/4xx_pci.h
+8
-0
include/configs/DU440.h
include/configs/DU440.h
+3
-2
include/configs/PMC440.h
include/configs/PMC440.h
+3
-2
include/configs/alpr.h
include/configs/alpr.h
+0
-2
include/configs/korat.h
include/configs/korat.h
+2
-0
include/configs/sequoia.h
include/configs/sequoia.h
+1
-0
include/ppc440.h
include/ppc440.h
+2
-1
未找到文件。
board/amcc/bamboo/bamboo.c
浏览文件 @
77b25175
...
...
@@ -466,143 +466,6 @@ phys_size_t initdram (int board_type)
#endif
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr
(
SD0_AMP1
,
addr
);
mtsdr
(
SD0_AMP1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
addr
|
0x80000000
);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr
(
SD0_AMP0
,
addr
);
mtsdr
(
SD0_AMP0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
PLB4_ACR
,
addr
);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
addr
);
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r
(
PCIL0_PMM0MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM0MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PMM1MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM1MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIL0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CONFIG_SYS_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
/*----------------------------------------------------------------------------+
| is_powerpc440ep_pass1.
+----------------------------------------------------------------------------*/
...
...
board/amcc/canyonlands/canyonlands.c
浏览文件 @
77b25175
...
...
@@ -326,43 +326,6 @@ phys_size_t initdram(int board_type)
}
#endif
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*
* Disable everything
*/
out_le32
((
void
*
)
PCIL0_PIM0SA
,
0
);
/* disable */
out_le32
((
void
*
)
PCIL0_PIM1SA
,
0
);
/* disable */
out_le32
((
void
*
)
PCIL0_PIM2SA
,
0
);
/* disable */
out_le32
((
void
*
)
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*/
out_le32
((
void
*
)
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out_le32
((
void
*
)
PCIL0_PIM0LAH
,
0
);
out_le32
((
void
*
)
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out_le32
((
void
*
)
PCIL0_BAR0
,
0
);
/*
* Program the board's subsystem id/vendor id
*/
out_le16
((
void
*
)
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out_le16
((
void
*
)
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out_le16
((
void
*
)
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
int
board_pcie_first
(
void
)
{
...
...
board/amcc/ebony/ebony.c
浏览文件 @
77b25175
...
...
@@ -164,73 +164,3 @@ long int fixed_sdram(void)
return
(
128
*
1024
*
1024
);
/* 128 MB */
}
#endif
/* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
/*--------------------------------------------------------------------------+
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
strap
=
mfdcr
(
CPC0_STRP1
);
if
((
strap
&
0x00100000
)
==
0
)
{
printf
(
"PCI: CPC0_STRP1[PAE] not set.
\n
"
);
return
0
;
}
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM1SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM2SA
,
0
);
/* disable */
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
board/amcc/katmai/katmai.c
浏览文件 @
77b25175
/*
* (C) Copyright 2007-200
8
* (C) Copyright 2007-200
9
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -260,75 +260,6 @@ u32 ddr_clktr(u32 default_val) {
return
(
SDRAM_CLKTR_CLKP_90_DEG_ADV
);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
/*-------------------------------------------------------------------+
* The katmai board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
mfsdr
(
SDR0_SDSTP1
,
strap
);
if
(
(
strap
&
SDR0_SDSTP1_PAE_MASK
)
==
0
)
{
printf
(
"PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.
\n
"
,
strap
);
return
0
;
}
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM1SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM2SA
,
0
);
/* disable */
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*-------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
int
board_pcie_card_present
(
int
port
)
{
...
...
board/amcc/kilauea/kilauea.c
浏览文件 @
77b25175
...
...
@@ -285,25 +285,6 @@ int checkboard (void)
return
(
0
);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
return
0
;
}
#endif
/* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
...
...
board/amcc/luan/luan.c
浏览文件 @
77b25175
...
...
@@ -126,79 +126,6 @@ u32 ddr_clktr(u32 default_val) {
return
(
SDRAM_CLKTR_CLKP_180_DEG_ADV
);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
/*--------------------------------------------------------------------------+
* The luan board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr
(
SDR0_SDSTP1
,
strap
);
if
(
(
strap
&
SDR0_SDSTP1_PAE_MASK
)
==
0
)
{
printf
(
"PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.
\n
"
,
strap
);
return
0
;
}
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM1SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM2SA
,
0
);
/* disable */
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* hw_watchdog_reset
*
...
...
board/amcc/makalu/makalu.c
浏览文件 @
77b25175
...
...
@@ -237,25 +237,6 @@ int checkboard (void)
return
(
0
);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
return
0
;
}
#endif
/* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
...
...
board/amcc/ocotea/ocotea.c
浏览文件 @
77b25175
...
...
@@ -275,78 +275,6 @@ long int fixed_sdram (void)
}
#endif
/* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
/*--------------------------------------------------------------------------+
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr
(
SDR0_SDSTP1
,
strap
);
if
(
(
strap
&
SDR0_SDSTP1_PAE_MASK
)
==
0
){
printf
(
"PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.
\n
"
,
strap
);
return
0
;
}
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM1SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM2SA
,
0
);
/* disable */
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
void
fpga_init
(
void
)
{
unsigned
long
group
;
...
...
board/amcc/sequoia/sequoia.c
浏览文件 @
77b25175
...
...
@@ -364,151 +364,12 @@ int checkboard(void)
/*
* Assign interrupts to PCI devices.
*/
void
sequoia
_pci_fixup_irq
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
)
void
board
_pci_fixup_irq
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
)
{
pci_hose_write_config_byte
(
hose
,
dev
,
PCI_INTERRUPT_LINE
,
VECNUM_EIRQ2
);
}
#endif
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr
(
SD0_AMP1
,
addr
);
mtsdr
(
SD0_AMP1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
addr
|
0x80000000
);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr
(
SD0_AMP0
,
addr
);
mtsdr
(
SD0_AMP0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
PLB4_ACR
,
addr
);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
addr
);
#ifdef CONFIG_PCI_PNP
hose
->
fixup_irq
=
sequoia_pci_fixup_irq
;
#endif
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*
* Set up Direct MMIO registers
*/
/*
* PowerPC440EPX PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0xA0000000-0xDFFFFFFF
* ==> PCI address 0xA0000000-0xDFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
out32r
(
PCIL0_PMM0MA
,
0x00000000
);
/* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r
(
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM0MA
,
0xE0000001
);
/* 512M + No prefetching, */
/* and enable region */
out32r
(
PCIL0_PMM1MA
,
0x00000000
);
/* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r
(
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM1MA
,
0xE0000001
);
/* 512M + No prefetching, */
/* and enable region */
out32r
(
PCIL0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIL0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*
* Set up Configuration registers
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CONFIG_SYS_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
...
...
board/amcc/taishan/taishan.c
浏览文件 @
77b25175
...
...
@@ -209,76 +209,6 @@ int checkboard (void)
return
(
0
);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
/*--------------------------------------------------------------------------+
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr
(
SDR0_SDSTP1
,
strap
);
if
(
(
strap
&
SDR0_SDSTP1_PAE_MASK
)
==
0
){
printf
(
"PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.
\n
"
,
strap
);
return
0
;
}
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM1SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM2SA
,
0
);
/* disable */
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
...
...
board/amcc/yosemite/yosemite.c
浏览文件 @
77b25175
...
...
@@ -352,143 +352,6 @@ phys_size_t initdram(int board)
return
CONFIG_SYS_SDRAM_BANKS
*
(
CONFIG_SYS_KBYTES_SDRAM
*
1024
);
/* return bytes */
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr
(
SD0_AMP1
,
addr
);
mtsdr
(
SD0_AMP1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
addr
|
0x80000000
);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr
(
SD0_AMP0
,
addr
);
mtsdr
(
SD0_AMP0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
PLB4_ACR
,
addr
);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
addr
);
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r
(
PCIL0_PMM0MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM0MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PMM1MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM1MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIL0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CONFIG_SYS_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
/*************************************************************************
* hw_watchdog_reset
*
...
...
board/amcc/yucca/yucca.c
浏览文件 @
77b25175
...
...
@@ -588,75 +588,6 @@ u32 ddr_clktr(u32 default_val) {
return
default_val
;
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
/*-------------------------------------------------------------------+
* The yucca board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
mfsdr
(
SDR0_SDSTP1
,
strap
);
if
(
(
strap
&
SDR0_SDSTP1_PAE_MASK
)
==
0
)
{
printf
(
"PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.
\n
"
,
strap
);
return
0
;
}
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM1SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM2SA
,
0
);
/* disable */
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*-------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
int
board_pcie_card_present
(
int
port
)
{
...
...
board/esd/du440/du440.c
浏览文件 @
77b25175
...
...
@@ -360,144 +360,6 @@ int checkboard(void)
return
(
0
);
}
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr
(
SD0_AMP1
,
addr
);
mtsdr
(
SD0_AMP1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
addr
|
0x80000000
);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr
(
SD0_AMP0
,
addr
);
mtsdr
(
SD0_AMP0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
PLB4_ACR
,
addr
);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
addr
);
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*
* Set up Direct MMIO registers
*/
/*
* PowerPC440EPX PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0xA0000000-0xDFFFFFFF
* ==> PCI address 0xA0000000-0xDFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
out32r
(
PCIL0_PMM0MA
,
0x00000000
);
/* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r
(
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM0MA
,
0xE0000001
);
/* 512M + No prefetching, */
/* and enable region */
out32r
(
PCIL0_PMM1MA
,
0x00000000
);
/* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r
(
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM1MA
,
0xE0000001
);
/* 512M + No prefetching, */
/* and enable region */
out32r
(
PCIL0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIL0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*
* Set up Configuration registers
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
PCI_VENDOR_ID_ESDGMBH
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
PCI_DEVICE_ID_DU440
);
pci_write_config_word
(
0
,
PCI_CLASS_SUB_CODE
,
PCI_CLASS_BRIDGE_HOST
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
int
last_stage_init
(
void
)
{
int
e
,
i
;
...
...
board/esd/du440/du440.h
浏览文件 @
77b25175
...
...
@@ -38,6 +38,3 @@
#define PWR_RDY 0x10
#define CPLD_IRQ (32+30)
#define PCI_VENDOR_ID_ESDGMBH 0x12fe
#define PCI_DEVICE_ID_DU440 0x0444
board/esd/pmc440/config.mk
浏览文件 @
77b25175
...
...
@@ -20,10 +20,6 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 440EPx Reference Platform (Sequoia) board
#
sinclude
$(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef
TEXT_BASE
...
...
board/esd/pmc440/pmc440.c
浏览文件 @
77b25175
...
...
@@ -39,6 +39,8 @@
#include <miiphy.h>
#endif
#include <serial.h>
#include <asm/4xx_pci.h>
#include "fpga.h"
#include "pmc440.h"
...
...
@@ -478,7 +480,7 @@ int checkboard(void)
/*
* Assign interrupts to PCI devices. Some OSs rely on this.
*/
void
pmc440
_pci_fixup_irq
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
)
void
board
_pci_fixup_irq
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
)
{
unsigned
char
int_line
[]
=
{
IRQ_PCIC
,
IRQ_PCID
,
IRQ_PCIA
,
IRQ_PCIB
};
...
...
@@ -487,64 +489,6 @@ void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
}
#endif
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr
(
SD0_AMP1
,
addr
);
mtsdr
(
SD0_AMP1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
addr
|
0x80000000
);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr
(
SD0_AMP0
,
addr
);
mtsdr
(
SD0_AMP0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
PLB4_ACR
,
addr
);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
addr
);
#ifdef CONFIG_PCI_PNP
hose
->
fixup_irq
=
pmc440_pci_fixup_irq
;
#endif
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*
* pci_target_init
*
...
...
@@ -658,24 +602,16 @@ void pci_target_init(struct pci_controller *hose)
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*
*
pci_master_init
*
Override weak default pci_master_init()
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
* Only configure the master in monach mode
*/
if
(
is_monarch
())
{
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
if
(
is_monarch
())
__pci_master_init
(
hose
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
...
...
board/gdsys/gdppc440etx/gdppc440etx.c
浏览文件 @
77b25175
...
...
@@ -29,6 +29,7 @@
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/4xx_pci.h>
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -158,55 +159,13 @@ int checkboard(void)
}
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
* Override weak pci_pre_init()
*/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr
(
SD0_AMP1
,
addr
);
mtsdr
(
SD0_AMP1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
addr
|
0x80000000
);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr
(
SD0_AMP0
,
addr
);
mtsdr
(
SD0_AMP0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
PLB4_ACR
,
addr
);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
addr
);
/* First call common code */
__pci_pre_init
(
hose
);
/* enable 66 MHz ext. Clock */
out32
(
GPIO1_TCR
,
in32
(
GPIO1_TCR
)
|
0x00008000
);
...
...
@@ -215,87 +174,3 @@ int pci_pre_init(struct pci_controller *hose)
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*
* Set up Direct MMIO registers
*/
/*
* PowerPC440 EP PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0xA0000000-0xDFFFFFFF
* ==> PCI address 0xA0000000-0xDFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
out32r
(
PCIL0_PMM0MA
,
0x00000000
);
/* disabled b4 setting */
out32r
(
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
out32r
(
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
out32r
(
PCIL0_PMM0PCIHA
,
0x00000000
);
out32r
(
PCIL0_PMM0MA
,
0xE0000001
);
/* 512M, no prefetch, enable region */
out32r
(
PCIL0_PMM1MA
,
0x00000000
);
/* disabled b4 setting */
out32r
(
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE2
);
out32r
(
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE2
);
out32r
(
PCIL0_PMM1PCIHA
,
0x00000000
);
out32r
(
PCIL0_PMM1MA
,
0xE0000001
);
/* 512M, no prefetch, enable region */
out32r
(
PCIL0_PTM1MS
,
0x00000001
);
out32r
(
PCIL0_PTM1LA
,
0
);
out32r
(
PCIL0_PTM2MS
,
0
);
out32r
(
PCIL0_PTM2LA
,
0
);
/*
* Set up Configuration registers
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CONFIG_SYS_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*
* pci_master_init
*
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
board/gdsys/intip/intip.c
浏览文件 @
77b25175
...
...
@@ -141,43 +141,6 @@ int checkboard(void)
return
0
;
}
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*
* Disable everything
*/
out_le32
((
void
*
)
PCIL0_PIM0SA
,
0
);
/* disable */
out_le32
((
void
*
)
PCIL0_PIM1SA
,
0
);
/* disable */
out_le32
((
void
*
)
PCIL0_PIM2SA
,
0
);
/* disable */
out_le32
((
void
*
)
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*/
out_le32
((
void
*
)
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out_le32
((
void
*
)
PCIL0_PIM0LAH
,
0
);
out_le32
((
void
*
)
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out_le32
((
void
*
)
PCIL0_BAR0
,
0
);
/*
* Program the board's subsystem id/vendor id
*/
out_le16
((
void
*
)
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out_le16
((
void
*
)
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out_le16
((
void
*
)
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
int
board_early_init_r
(
void
)
{
/*
...
...
board/korat/korat.c
浏览文件 @
77b25175
...
...
@@ -35,6 +35,7 @@
#include <asm/io.h>
#include <asm/ppc4xx-uic.h>
#include <asm/processor.h>
#include <asm/4xx_pci.h>
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -594,70 +595,12 @@ int checkboard(void)
/*
* Assign interrupts to PCI devices.
*/
void
korat
_pci_fixup_irq
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
)
void
board
_pci_fixup_irq
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
)
{
pci_hose_write_config_byte
(
hose
,
dev
,
PCI_INTERRUPT_LINE
,
VECNUM_EIRQ2
);
}
#endif
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr
(
SD0_AMP1
,
addr
);
mtsdr
(
SD0_AMP1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
addr
|
0x80000000
);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr
(
SD0_AMP0
,
addr
);
mtsdr
(
SD0_AMP0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
PLB4_ACR
,
addr
);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
addr
);
#if defined(CONFIG_PCI_PNP)
hose
->
fixup_irq
=
korat_pci_fixup_irq
;
#endif
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*
* pci_target_init
*
...
...
@@ -668,60 +611,8 @@ int pci_pre_init(struct pci_controller *hose)
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*
* Set up Direct MMIO registers
*/
/*
* PowerPC440EPX PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0x80000000-0xBFFFFFFF
* ==> PCI address 0x80000000-0xBFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
out32r
(
PCIL0_PMM0MA
,
0x00000000
);
/* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r
(
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM0MA
,
0xE0000001
);
/* 512M + No prefetching, */
/* and enable region */
out32r
(
PCIL0_PMM1MA
,
0x00000000
);
/* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r
(
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE
+
0x20000000
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE
+
0x20000000
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM1MA
,
0xE0000001
);
/* 512M + No prefetching, */
/* and enable region */
out32r
(
PCIL0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIL0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*
* Set up Configuration registers
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CONFIG_SYS_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
/* First do 440EP(x) common setup */
__pci_target_init
(
hose
);
/*
* Set up Configuration registers for on-board NEC uPD720101 USB
...
...
@@ -731,23 +622,6 @@ void pci_target_init(struct pci_controller *hose)
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
...
...
board/lwmon5/lwmon5.c
浏览文件 @
77b25175
...
...
@@ -275,143 +275,6 @@ int checkboard(void)
return
(
0
);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr
(
SD0_AMP1
,
addr
);
mtsdr
(
SD0_AMP1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
addr
|
0x80000000
);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr
(
SD0_AMP0
,
addr
);
mtsdr
(
SD0_AMP0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
PLB4_ACR
,
addr
);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
addr
);
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440EPX PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r
(
PCIL0_PMM0MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM0MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PMM1MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM1MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIL0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CONFIG_SYS_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
void
hw_watchdog_reset
(
void
)
{
int
val
;
...
...
board/netstal/hcu5/hcu5.c
浏览文件 @
77b25175
...
...
@@ -22,6 +22,8 @@
#include <asm/processor.h>
#include <ppc440.h>
#include <asm/io.h>
#include <asm/4xx_pci.h>
#include "../common/nm.h"
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -377,88 +379,14 @@ int pci_pre_init(struct pci_controller *hose)
}
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
*/
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
if
(
!
board_with_pci
())
{
return
;
}
/*
* Set up Direct MMIO registers
*
* PowerPC440EPX PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
* 0xA0000000-0xDFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM0MA
,
0x00000000
);
out32r
(
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 Local Address */
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
out32r
(
PCIL0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PMM0MA
,
0xE0000001
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM1MA
,
0x00000000
);
out32r
(
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 Local Address */
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE2
);
out32r
(
PCIL0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PMM1MA
,
0xE0000001
);
out32r
(
PCIL0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIL0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*
* Set up Configuration registers
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CONFIG_SYS_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
/*
* pci_master_init
*
* Override weak default pci_master_init()
*/
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
if
(
!
board_with_pci
())
{
return
;
}
/*---------------------------------------------------------------
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*--------------------------------------------------------------*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
if
(
!
board_with_pci
())
return
;
__pci_master_init
(
hose
);
}
#endif
/* defined(CONFIG_PCI) */
...
...
board/pcs440ep/pcs440ep.c
浏览文件 @
77b25175
...
...
@@ -550,143 +550,6 @@ phys_size_t initdram (int board_type)
return
dram_size
;
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr
(
SD0_AMP1
,
addr
);
mtsdr
(
SD0_AMP1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
addr
|
0x80000000
);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr
(
SD0_AMP0
,
addr
);
mtsdr
(
SD0_AMP0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
PLB4_ACR
,
addr
);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
addr
=
(
addr
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
addr
=
(
addr
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
addr
=
(
addr
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
addr
);
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r
(
PCIL0_PMM0MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM0MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PMM1MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 Local Address */
out32r
(
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM0 PCI Low Address */
out32r
(
PCIL0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIL0_PMM1MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIL0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIL0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIL0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CONFIG_SYS_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
/*************************************************************************
* hw_watchdog_reset
*
...
...
board/prodrive/alpr/alpr.c
浏览文件 @
77b25175
...
...
@@ -29,6 +29,7 @@
#include <ppc4xx_enet.h>
#include <miiphy.h>
#include <asm/processor.h>
#include <asm/4xx_pci.h>
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -144,78 +145,20 @@ int checkboard (void)
return
(
0
);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
/*
* Override weak pci_pre_init()
*/
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
/*--------------------------------------------------------------------------+
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr
(
SDR0_SDSTP1
,
strap
);
if
(
(
strap
&
SDR0_SDSTP1_PAE_MASK
)
==
0
){
printf
(
"PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.
\n
"
,
strap
);
if
(
__pci_pre_init
(
hose
)
==
0
)
return
0
;
}
/* FPGA Init */
alpr_fpga_init
();
alpr_fpga_init
();
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM1SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM2SA
,
0
);
/* disable */
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
|
PCI_COMMAND_MASTER
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* Override weak is_pci_host()
...
...
@@ -232,8 +175,6 @@ void pci_target_init(struct pci_controller * hose )
*
*
************************************************************************/
#if defined(CONFIG_PCI)
static
void
wait_for_pci_ready
(
void
)
{
/*
...
...
board/prodrive/p3p440/p3p440.c
浏览文件 @
77b25175
...
...
@@ -164,76 +164,6 @@ int misc_init_r (void)
return
0
;
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
/*--------------------------------------------------------------------------+
* The P3P440 board is always configured as the host & requires the
* PCI arbiter to be disabled because it's an PMC module.
*--------------------------------------------------------------------------*/
strap
=
mfdcr
(
CPC0_STRP1
);
if
(
strap
&
0x00100000
)
{
printf
(
"PCI: CPC0_STRP1[PAE] set.
\n
"
);
return
0
;
}
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM1SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM2SA
,
0
);
/* disable */
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* Override weak is_pci_host()
*
...
...
board/sandburst/common/sb_common.c
浏览文件 @
77b25175
...
...
@@ -300,78 +300,6 @@ long int fixed_sdram (void)
}
#endif
/* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
/*--------------------------------------------------------------------------+
* The metrobox is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr
(
SDR0_SDSTP1
,
strap
);
if
(
(
strap
&
SDR0_SDSTP1_PAE_MASK
)
==
0
){
printf
(
"PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.
\n
"
,
strap
);
return
0
;
}
return
1
;
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM1SA
,
0
);
/* disable */
out32r
(
PCIL0_PIM2SA
,
0
);
/* disable */
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* board_get_enetaddr
*
...
...
board/xes/xpedite1000/xpedite1000.c
浏览文件 @
77b25175
...
...
@@ -136,6 +136,8 @@ phys_size_t initdram(int board_type)
}
/*
* Override weak pci_pre_init()
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
...
...
@@ -144,7 +146,6 @@ phys_size_t initdram(int board_type)
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
...
...
@@ -166,38 +167,6 @@ int pci_pre_init(struct pci_controller * hose)
}
#endif
/* defined(CONFIG_PCI) */
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
/*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/* Disable everything */
out32r
(
PCIL0_PIM0SA
,
0
);
out32r
(
PCIL0_PIM1SA
,
0
);
out32r
(
PCIL0_PIM2SA
,
0
);
out32r
(
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*/
out32r
(
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out32r
(
PCIL0_PIM0LAH
,
0
);
out32r
(
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out32r
(
PCIL0_BAR0
,
0
);
/* Program the board's subsystem id/vendor id */
out16r
(
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out16r
(
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out16r
(
PCIL0_CMD
,
in16r
(
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
/*
* Override weak is_pci_host()
...
...
cpu/ppc4xx/4xx_pci.c
浏览文件 @
77b25175
...
...
@@ -73,23 +73,30 @@
#include <common.h>
#include <command.h>
#if !defined(CONFIG_440)
#include <asm/4xx_pci.h>
#endif
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#ifdef CONFIG_PCI
DECLARE_GLOBAL_DATA_PTR
;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#if defined(CONFIG_PMC405)
ushort
pmc405_pci_subsys_deviceid
(
void
);
#endif
/*#define DEBUG*/
/*
* Board-specific pci initialization
* Platform code can reimplement pci_pre_init() if needed
*/
int
__pci_pre_init
(
struct
pci_controller
*
hose
)
{
#if defined
(CONFIG_405EP)
#if defined(CONFIG_405EP)
/*
* Enable the internal PCI arbiter by default.
*
...
...
@@ -105,15 +112,8 @@ int __pci_pre_init(struct pci_controller *hose)
return
1
;
}
int
pci_pre_init
(
struct
pci_controller
*
hose
)
__attribute__
((
weak
,
alias
(
"__pci_pre_init"
)));
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#if defined(CONFIG_PMC405)
ushort
pmc405_pci_subsys_deviceid
(
void
);
#endif
/*#define DEBUG*/
int
pci_pre_init
(
struct
pci_controller
*
hose
)
__attribute__
((
weak
,
alias
(
"__pci_pre_init"
)));
int
__is_pci_host
(
struct
pci_controller
*
hose
)
{
...
...
@@ -231,7 +231,7 @@ void pci_405gp_init(struct pci_controller *hose)
pciauto_region_init
(
hose
->
pci_fb
);
/* Let board change/modify hose & do initial checks */
if
(
pci_pre_init
(
hose
)
==
0
)
{
if
(
pci_pre_init
(
hose
)
==
0
)
{
printf
(
"PCI: Board-specific initialization failed.
\n
"
);
printf
(
"PCI: Configuration aborted.
\n
"
);
return
;
...
...
@@ -499,6 +499,211 @@ int __is_pci_host(struct pci_controller *hose)
int
is_pci_host
(
struct
pci_controller
*
hose
)
__attribute__
((
weak
,
alias
(
"__is_pci_host"
)));
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX)
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
void
__pci_target_init
(
struct
pci_controller
*
hose
)
{
/*
* Set up Direct MMIO registers
*/
/*
* PowerPC440 EP PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
/* PMM0 Mask/Attribute - disabled b4 setting */
out_le32
((
void
*
)
PCIL0_PMM0MA
,
0x00000000
);
/* PMM0 Local Address */
out_le32
((
void
*
)
PCIL0_PMM0LA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out_le32
((
void
*
)
PCIL0_PMM0PCILA
,
CONFIG_SYS_PCI_MEMBASE
);
/* PMM0 PCI High Address */
out_le32
((
void
*
)
PCIL0_PMM0PCIHA
,
0x00000000
);
/* 512M + No prefetching, and enable region */
out_le32
((
void
*
)
PCIL0_PMM0MA
,
0xE0000001
);
/* PMM1 Mask/Attribute - disabled b4 setting */
out_le32
((
void
*
)
PCIL0_PMM1MA
,
0x00000000
);
/* PMM1 Local Address */
out_le32
((
void
*
)
PCIL0_PMM1LA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM1 PCI Low Address */
out_le32
((
void
*
)
PCIL0_PMM1PCILA
,
CONFIG_SYS_PCI_MEMBASE2
);
/* PMM1 PCI High Address */
out_le32
((
void
*
)
PCIL0_PMM1PCIHA
,
0x00000000
);
/* 512M + No prefetching, and enable region */
out_le32
((
void
*
)
PCIL0_PMM1MA
,
0xE0000001
);
out_le32
((
void
*
)
PCIL0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out_le32
((
void
*
)
PCIL0_PTM1LA
,
0
);
/* Local Addr. Reg */
out_le32
((
void
*
)
PCIL0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out_le32
((
void
*
)
PCIL0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*
* Set up Configuration registers
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CONFIG_SYS_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* CONFIG_SYS_PCI_TARGET_INIT */
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
*/
int
__pci_pre_init
(
struct
pci_controller
*
hose
)
{
u32
reg
;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr
(
SD0_AMP1
,
reg
);
mtsdr
(
SD0_AMP1
,
(
reg
&
0x000000FF
)
|
0x0000FF00
);
reg
=
mfdcr
(
PLB3_ACR
);
mtdcr
(
PLB3_ACR
,
reg
|
0x80000000
);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr
(
SD0_AMP0
,
reg
);
mtsdr
(
SD0_AMP0
,
(
reg
&
0x000000FF
)
|
0x0000FF00
);
reg
=
mfdcr
(
PLB4_ACR
)
|
0xa0000000
;
mtdcr
(
PLB4_ACR
,
reg
);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
reg
=
(
mfdcr
(
PLB0_ACR
)
&
~
PLB0_ACR_PPM_MASK
)
|
PLB0_ACR_PPM_FAIR
;
reg
=
(
reg
&
~
PLB0_ACR_HBU_MASK
)
|
PLB0_ACR_HBU_ENABLED
;
reg
=
(
reg
&
~
PLB0_ACR_RDP_MASK
)
|
PLB0_ACR_RDP_4DEEP
;
reg
=
(
reg
&
~
PLB0_ACR_WRP_MASK
)
|
PLB0_ACR_WRP_2DEEP
;
mtdcr
(
PLB0_ACR
,
reg
);
/* Segment1 */
reg
=
(
mfdcr
(
PLB1_ACR
)
&
~
PLB1_ACR_PPM_MASK
)
|
PLB1_ACR_PPM_FAIR
;
reg
=
(
reg
&
~
PLB1_ACR_HBU_MASK
)
|
PLB1_ACR_HBU_ENABLED
;
reg
=
(
reg
&
~
PLB1_ACR_RDP_MASK
)
|
PLB1_ACR_RDP_4DEEP
;
reg
=
(
reg
&
~
PLB1_ACR_WRP_MASK
)
|
PLB1_ACR_WRP_2DEEP
;
mtdcr
(
PLB1_ACR
,
reg
);
#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
hose
->
fixup_irq
=
board_pci_fixup_irq
;
#endif
return
1
;
}
#else
/* defined(CONFIG_440EP) ... */
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
void
__pci_target_init
(
struct
pci_controller
*
hose
)
{
/*
* Disable everything
*/
out_le32
((
void
*
)
PCIL0_PIM0SA
,
0
);
/* disable */
out_le32
((
void
*
)
PCIL0_PIM1SA
,
0
);
/* disable */
out_le32
((
void
*
)
PCIL0_PIM2SA
,
0
);
/* disable */
out_le32
((
void
*
)
PCIL0_EROMBA
,
0
);
/* disable expansion rom */
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options do not support sizes such as 128/256 MB.
*/
out_le32
((
void
*
)
PCIL0_PIM0LAL
,
CONFIG_SYS_SDRAM_BASE
);
out_le32
((
void
*
)
PCIL0_PIM0LAH
,
0
);
out_le32
((
void
*
)
PCIL0_PIM0SA
,
~
(
gd
->
ram_size
-
1
)
|
1
);
out_le32
((
void
*
)
PCIL0_BAR0
,
0
);
/*
* Program the board's subsystem id/vendor id
*/
out_le16
((
void
*
)
PCIL0_SBSYSVID
,
CONFIG_SYS_PCI_SUBSYS_VENDORID
);
out_le16
((
void
*
)
PCIL0_SBSYSID
,
CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
out_le16
((
void
*
)
PCIL0_CMD
,
in_le16
((
void
*
)
PCIL0_CMD
)
|
PCI_COMMAND_MEMORY
);
}
#endif
/* CONFIG_SYS_PCI_TARGET_INIT */
int
__pci_pre_init
(
struct
pci_controller
*
hose
)
{
/*
* This board is always configured as the host & requires the
* PCI arbiter to be enabled.
*/
if
(
!
pci_arbiter_enabled
())
{
printf
(
"PCI: PCI Arbiter disabled!
\n
"
);
return
0
;
}
return
1
;
}
#endif
/* defined(CONFIG_440EP) ... */
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
__attribute__
((
weak
,
alias
(
"__pci_target_init"
)));
#endif
/* CONFIG_SYS_PCI_TARGET_INIT */
int
pci_pre_init
(
struct
pci_controller
*
hose
)
__attribute__
((
weak
,
alias
(
"__pci_pre_init"
)));
#if defined(CONFIG_SYS_PCI_MASTER_INIT)
void
__pci_master_init
(
struct
pci_controller
*
hose
)
{
u16
reg
;
/*
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
reg
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
reg
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
void
pci_master_init
(
struct
pci_controller
*
hose
)
__attribute__
((
weak
,
alias
(
"__pci_master_init"
)));
#endif
/* CONFIG_SYS_PCI_MASTER_INIT */
int
pci_440_init
(
struct
pci_controller
*
hose
)
{
int
reg_num
=
0
;
...
...
@@ -568,7 +773,7 @@ int pci_440_init (struct pci_controller *hose)
pci_setup_indirect
(
hose
,
PCIL0_CFGADR
,
PCIL0_CFGDATA
);
/* Let board change/modify hose & do initial checks */
if
(
pci_pre_init
(
hose
)
==
0
)
{
if
(
pci_pre_init
(
hose
)
==
0
)
{
printf
(
"PCI: Board-specific initialization failed.
\n
"
);
printf
(
"PCI: Configuration aborted.
\n
"
);
return
-
1
;
...
...
cpu/ppc4xx/cpu.c
浏览文件 @
77b25175
...
...
@@ -81,7 +81,7 @@ static int pci_async_enabled(void)
#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
!defined(CONFIG_405) && !defined(CONFIG_405EX)
static
int
pci_arbiter_enabled
(
void
)
int
pci_arbiter_enabled
(
void
)
{
#if defined(CONFIG_405GP)
return
(
mfdcr
(
CPC0_PSR
)
&
PSR_PCI_ARBIT_EN
);
...
...
include/asm-ppc/4xx_pci.h
浏览文件 @
77b25175
#ifndef _405GP_PCI_H
#define _405GP_PCI_H
#include <pci.h>
/*----------------------------------------------------------------------------+
| 405GP PCI core memory map defines.
+----------------------------------------------------------------------------*/
...
...
@@ -49,4 +51,10 @@
#define PCIDEVID_405GP 0x0
void
board_pci_fixup_irq
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
);
int
pci_arbiter_enabled
(
void
);
int
__pci_pre_init
(
struct
pci_controller
*
hose
);
void
__pci_target_init
(
struct
pci_controller
*
hose
);
void
__pci_master_init
(
struct
pci_controller
*
hose
);
#endif
include/configs/DU440.h
浏览文件 @
77b25175
...
...
@@ -60,8 +60,9 @@
#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
#define CONFIG_SYS_PCI_IOBASE 0xe8000000
#define CONFIG_SYS_PCI_IOBASE 0xe8000000
#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444
/* device ID for DU440 */
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000
/* internal peripherals */
...
...
include/configs/PMC440.h
浏览文件 @
77b25175
...
...
@@ -351,7 +351,6 @@
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_DIAG
...
...
@@ -359,7 +358,6 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
...
...
@@ -435,11 +433,14 @@
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
/* PCI identification */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
/* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441
/* PCI Device ID: Non-Monarch */
#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440
/* PCI Device ID: Monarch */
/* for weak __pci_target_init() */
#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
...
...
include/configs/alpr.h
浏览文件 @
77b25175
...
...
@@ -231,13 +231,11 @@
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
...
...
include/configs/korat.h
浏览文件 @
77b25175
...
...
@@ -69,6 +69,7 @@
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
#define CONFIG_SYS_PCI_BASE 0xe0000000
/* Internal PCI regs */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000
/* mapped pci memory */
#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000
/* internal peripherals */
...
...
@@ -359,6 +360,7 @@
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8
/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe
/* Whatever */
...
...
include/configs/sequoia.h
浏览文件 @
77b25175
...
...
@@ -364,6 +364,7 @@
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8
/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe
/* Whatever */
...
...
include/ppc440.h
浏览文件 @
77b25175
...
...
@@ -1276,7 +1276,8 @@
#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
#endif
/* defined(CONFIG_440GP) */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
#endif
/* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
...
...
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