Skip to content

U
U-Boot.Mirror

OS / U-Boot.Mirror

通知 1
Star 0
Fork 0
U
U-Boot.Mirror

体验新版 GitCode，发现更多精彩内容 >>

提交 7708d8b3 编写于 作者: W Wolfgang Denk
浏览文件
操作

Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master 

* 'master' of ssh://gemini/home/wd/git/u-boot/master:
  board/emk/top860/top860.c: Fix GCC 4.6 build warning
  board/sbc405/strataflash.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc86xx/cpu.c: Fix GCC 4.6 build warning
  board/freescale/mpc8610hpcd/mpc8610hpcd.c: Fix GCC 4.6 build warning
  board/mpl/common/flash.c: Fix GCC 4.6 build warning
  post/board/lwmon5/gdc.c: Fix GCC 4.6 build warning
  drivers/usb/host/sl811-hcd.c: Fix GCC 4.6 build warning
  board/sandburst/common/flash.c: Fix GCC 4.6 build warning
  DB64460: Fix GCC 4.6 build warnings
  DB64360: Fix GCC 4.6 build warnings
  board/cray/L1/flash.c: Fix GCC 4.6 build warning
  drivers/block/sata_dwc.c: Fix GCC 4.6 build warning
  board/amirix/ap1000/flash.c: Fix GCC 4.6 build warning
  alpr board: Fix GCC 4.6 build warnings
  image: Don't detect XIP images as overlapping.
  image: Implement IH_TYPE_KERNEL_NOLOAD
  ppc4xx: Add Io64 board support
  ppc4xx: fix PMC440 painit command
  ppc4xx: remove invalid access to PCI_BRDGOPT2 register
  ppc4xx: use CONFIG_PCI_BOOTDELAY instead of private implementation
  mpc85xx: support for Freescale COM Express P2020
  arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
  mpc85xx: support board-specific reset function
  powerpc/85xx: verify the localbus device tree address before booting the OS
  mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
  powerpc/p3060qds: Add board related support for P3060QDS platform
  powerpc/85xx: clean up and document the QE/FMAN microcode macros
  powerpc/85xx: always implement the work-around for Erratum SATA_A001
  powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
  powerpc/85xx: Add workaround for erratum A-003474
  powerpc/85xx: fixup flexcan device tree clock-frequency
  powerpc/85xx: Add workaround for erratum CPU-A003999
  x86: Fix some bugs in the i8402 driver when no controller is present
  x86: Make the i8042 driver checkpatch clean
  x86: Wrap small helper functions from libgcc to avoid an ABI mismatch
  x86: Import the glibc memset implementation
  x86: Fix a few recently added bugs
  x86: Don't relocate symbols which point to things that aren't relocated
  x86: Fix how the location of the realmode and bios blobs are calculated
  x86: Misc cleanups
  x86: Misc PCI touchups
  x86: Ensure IDT and GDT remain 16-byte aligned post relocation
  x86: Provide more configuration granularity
  x86: Add multiboot header
  sc520: Create arch asm-offsets
  x86: Punt cold- and warm-boot flags
  cosmetic: checkpatch cleanup of board/eNET/*.c
  cosmetic: checkpatch cleanup of arch/x86/lib/*.c
  cosmetic: checkpatch cleanup of arch/x86/cpu/sc520/*.c
  cosmetic: checkpatch cleanup of arch/x86/cpu/*.c
  x86: Call hang() on unrecoverable exception
  menu.c: use puts() instead of printf() where possible
  MAKEALL: drop obsolete mx31pdk_nand target
  dataflash: fix parameters order in write_dataflash()
  hawkboard: Replace HAWKBOARD_KICK{0, 1}_UNLOCK defines
  davinci_sonata: define CONFIG_MACH_TYPE for davinci_sonata board
  davinci_schmoogie: define CONFIG_MACH_TYPE for davinci_schmoogie board
  arm: a320evb: define mach-type in board config file
  OMAP3: Use sdelay from arch/arm/cpu/armv7/syslib.c instead of cloning that.
  Fix Stelian's email address
  DIU: 1080P and 720P support
  CFB: Fix font rendering on mx5 framebuffer
上级 d887ad54 f008b17f
展开全部 隐藏空白更改
内联 并排
Showing with 6602 addition and 1936 deletion
MAINTAINERS
浏览文件 @ 7708d8b3
......@@ -150,6 +150,7 @@ Dirk Eibach <eibach@gdsys.de>
gdppc440etx PPC440EP/GR
intip PPC460EX
io PPC405EP
io64 PPC405EX
iocon PPC405EP
neo PPC405EP
......@@ -450,6 +451,10 @@ Jon Smirl <jonsmirl@gmail.com>
pcm030 MPC5200
Ira W. Snyder <iws@ovro.caltech.edu>
P2020COME P2020
Timur Tabi <timur@freescale.com>
MPC8349E-mITX MPC8349
......
README
浏览文件 @ 7708d8b3
......@@ -3274,6 +3274,44 @@ Low Level (hardware related) configuration options:
be used if available. These functions may be faster under some
conditions but may increase the binary size.
Freescale QE/FMAN Firmware Support:
-----------------------------------
The Freescale QUICCEngine (QE) and Frame Manager (FMAN) both support the
loading of "firmware", which is encoded in the QE firmware binary format.
This firmware often needs to be loaded during U-Boot booting, so macros
are used to identify the storage device (NOR flash, SPI, etc) and the address
within that device.
- CONFIG_SYS_QE_FMAN_FW_ADDR
The address in the storage device where the firmware is located. The
meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
is also specified.
- CONFIG_SYS_QE_FMAN_FW_LENGTH
The maximum possible size of the firmware. The firmware binary format
has a field that specifies the actual size of the firmware, but it
might not be possible to read any part of the firmware unless some
local storage is allocated to hold the entire firmware first.
- CONFIG_SYS_QE_FMAN_FW_IN_NOR
Specifies that QE/FMAN firmware is located in NOR flash, mapped as
normal addressable memory via the LBC. CONFIG_SYS_FMAN_FW_ADDR is the
virtual address in NOR flash.
- CONFIG_SYS_QE_FMAN_FW_IN_NAND
Specifies that QE/FMAN firmware is located in NAND flash.
CONFIG_SYS_FMAN_FW_ADDR is the offset within NAND flash.
- CONFIG_SYS_QE_FMAN_FW_IN_MMC
Specifies that QE/FMAN firmware is located on the primary SD/MMC
device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
Specifies that QE/FMAN firmware is located on the primary SPI
device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
Building the Software:
======================
......
arch/powerpc/cpu/mpc85xx/cmd_errata.c
浏览文件 @ 7708d8b3
......@@ -53,6 +53,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
puts("Work-around for Erratum DDR-A003473 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
#endif
......
arch/powerpc/cpu/mpc85xx/cpu.c
浏览文件 @ 7708d8b3
......@@ -42,6 +42,16 @@
DECLARE_GLOBAL_DATA_PTR;
/*
* Default board reset function
*/
static void
__board_reset(void)
{
/* Do nothing */
}
void board_reset(void) __attribute__((weak, alias("__board_reset")));
int checkcpu (void)
{
sys_info_t sysinfo;
......@@ -215,7 +225,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
mtspr(DBCR0,val);
#else
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
/* Attempt board-specific reset */
board_reset();
/* Next try asserting HRESET_REQ */
out_be32(&gur->rstcr, 0x2);
udelay(100);
#endif
......
arch/powerpc/cpu/mpc85xx/cpu_init.c
浏览文件 @ 7708d8b3
......@@ -37,12 +37,15 @@
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <linux/compiler.h>
#include "mp.h"
#ifdef CONFIG_SYS_QE_FW_IN_NAND
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#include <errno.h>
#endif
#include "../../../../drivers/block/fsl_sata.h"
DECLARE_GLOBAL_DATA_PTR;
extern void srio_init(void);
......@@ -301,6 +304,7 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
*/
int cpu_init_r(void)
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
......@@ -316,10 +320,9 @@ int cpu_init_r(void)
#if defined(CONFIG_L2_CACHE)
volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
uint svr, ver;
uint ver;
u32 l2siz_field;
svr = get_svr();
ver = SVR_SOC_VER(svr);
asm("msync;isync");
......@@ -401,8 +404,8 @@ int cpu_init_r(void)
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
(SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
if ((SVR_SOC_VER(svr) == SVR_P2040) ||
(SVR_SOC_VER(svr) == SVR_P2040_E)) {
puts("N/A\n");
goto skip_l2;
}
......@@ -488,6 +491,32 @@ skip_l2:
fman_enet_init();
#endif
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
* controller is configured in legacy mode instead of the
* expected enterprise mode. Software needs to clear bit[28]
* of HControl register to change to enterprise mode from
* legacy mode. We assume that the controller is offline.
*/
if (IS_SVR_REV(svr, 1, 0) &&
((SVR_SOC_VER(svr) == SVR_P1022) ||
(SVR_SOC_VER(svr) == SVR_P1022_E) ||
(SVR_SOC_VER(svr) == SVR_P1013) ||
(SVR_SOC_VER(svr) == SVR_P1013_E))) {
fsl_sata_reg_t *reg;
/* first SATA controller */
reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
/* second SATA controller */
reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
}
#endif
return 0;
}
......@@ -523,17 +552,17 @@ void cpu_secondary_init_r(void)
{
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
#ifdef CONFIG_SYS_QE_FW_IN_NAND
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
int ret;
size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
/* load QE firmware from NAND flash to DDR first */
ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
&fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
&fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
if (ret && ret == -EUCLEAN) {
printf ("NAND read for QE firmware at offset %x failed %d\n",
CONFIG_SYS_QE_FW_IN_NAND, ret);
CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
}
#endif
qe_init(qe_base);
......
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
浏览文件 @ 7708d8b3
......@@ -115,6 +115,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
for (i = 0; i < 32; i++)
out_be32(&ddr->debug[i], regs->debug[i]);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
out_be32(&ddr->debug[12], 0x00000015);
out_be32(&ddr->debug[21], 0x24000000);
#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
/* Set, but do not enable the memory */
temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
......
arch/powerpc/cpu/mpc85xx/fdt.c
浏览文件 @ 7708d8b3
......@@ -466,7 +466,7 @@ void fdt_fixup_fman_firmware(void *blob)
return;
}
if (length > CONFIG_SYS_FMAN_FW_LENGTH) {
if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
printf("Fman firmware at %p is too large (size=%u)\n",
fmanfw, length);
return;
......@@ -660,8 +660,19 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
"timer-frequency", gd->bus_clk/2, 1);
/*
* clock-freq should change to clock-frequency and
* flexcan-v1.0 should change to p1010-flexcan respectively
* in the future.
*/
do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
"clock_freq", gd->bus_clk, 1);
"clock_freq", gd->bus_clk/2, 1);
do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
"clock-frequency", gd->bus_clk/2, 1);
do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
"clock-frequency", gd->bus_clk/2, 1);
fdt_fixup_usb(blob);
}
......@@ -677,6 +688,12 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#define CCSR_VIRT_TO_PHYS(x) \
(CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
{
printf("Warning: U-Boot configured %s at address %llx,\n"
"but the device tree has it at %llx\n", name, uaddr, daddr);
}
/*
* Verify the device tree
*
......@@ -692,33 +709,32 @@ void ft_cpu_setup(void *blob, bd_t *bd)
*/
int ft_verify_fdt(void *fdt)
{
uint64_t ccsr = 0;
uint64_t addr = 0;
int aliases;
int off;
/* First check the CCSR base address */
off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
if (off > 0)
ccsr = fdt_get_base_address(fdt, off);
addr = fdt_get_base_address(fdt, off);
if (!ccsr) {
if (!addr) {
printf("Warning: could not determine base CCSR address in "
"device tree\n");
/* No point in checking anything else */
return 0;
}
if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) {
printf("Warning: U-Boot configured CCSR at address %llx,\n"
"but the device tree has it at %llx\n",
(uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr);
if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
/* No point in checking anything else */
return 0;
}
/*
* Get the 'aliases' node. If there isn't one, then there's nothing
* left to do.
* Check some nodes via aliases. We assume that U-Boot and the device
* tree enumerate the devices equally. E.g. the first serial port in
* U-Boot is the same as "serial0" in the device tree.
*/
aliases = fdt_path_offset(fdt, "/aliases");
if (aliases > 0) {
......@@ -735,5 +751,30 @@ int ft_verify_fdt(void *fdt)
#endif
}
/*
* The localbus node is typically a root node, even though the lbc
* controller is part of CCSR. If we were to put the lbc node under
* the SOC node, then the 'ranges' property in the lbc node would
* translate through the 'ranges' property of the parent SOC node, and
* we don't want that. Since it's a separate node, it's possible for
* the 'reg' property to be wrong, so check it here. For now, we
* only check for "fsl,elbc" nodes.
*/
#ifdef CONFIG_SYS_LBC_ADDR
off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
if (off > 0) {
const u32 *reg = fdt_getprop(fdt, off, "reg", NULL);
if (reg) {
uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
addr = fdt_translate_address(fdt, off, reg);
if (uaddr != addr) {
msg("the localbus", uaddr, addr);
return 0;
}
}
}
#endif
return 1;
}
arch/powerpc/cpu/mpc85xx/release.S
浏览文件 @ 7708d8b3
......@@ -68,6 +68,12 @@ __secondary_start_page:
mtspr SPRN_HID1,r3
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
mfspr r3,977
oris r3,r3,0x0100
mtspr 977,r3
#endif
/* Enable branch prediction */
lis r3,BUCSR_ENABLE@h
ori r3,r3,BUCSR_ENABLE@l
......
arch/powerpc/cpu/mpc85xx/start.S
浏览文件 @ 7708d8b3
......@@ -253,6 +253,12 @@ l2_disabled:
mtspr HID1,r0
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
mfspr r3,977
oris r3,r3,0x0100
mtspr 977,r3
#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
lis r0,BUCSR_ENABLE@h
......
arch/powerpc/cpu/mpc86xx/cpu.c
浏览文件 @ 7708d8b3
......@@ -48,7 +48,6 @@ checkcpu(void)
{
sys_info_t sysinfo;
uint pvr, svr;
uint ver;
uint major, minor;
char buf1[32], buf2[32];
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
......@@ -57,7 +56,6 @@ checkcpu(void)
uint msscr0 = mfspr(MSSCR0);
svr = get_svr();
ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
......@@ -77,7 +75,6 @@ checkcpu(void)
puts("Core: ");
pvr = get_pvr();
ver = PVR_E600_VER(pvr);
major = PVR_E600_MAJ(pvr);
minor = PVR_E600_MIN(pvr);
......
arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
浏览文件 @ 7708d8b3
......@@ -135,6 +135,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
case DDR3_SPD_MODULETYPE_RDIMM:
case DDR3_SPD_MODULETYPE_MINI_RDIMM:
case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
/* Registered/buffered DIMMs */
pdimm->registered_dimm = 1;
for (i = 0; i < 16; i += 2) {
......@@ -148,6 +149,12 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
case DDR3_SPD_MODULETYPE_SO_DIMM:
case DDR3_SPD_MODULETYPE_MICRO_DIMM:
case DDR3_SPD_MODULETYPE_MINI_UDIMM:
case DDR3_SPD_MODULETYPE_MINI_CDIMM:
case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
case DDR3_SPD_MODULETYPE_LRDIMM:
case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
/* Unbuffered DIMMs */
if (spd->mod_section.unbuffered.addr_mapping & 0x1)
pdimm->mirrored_dimm = 1;
......
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
浏览文件 @ 7708d8b3
......@@ -1354,7 +1354,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
{
unsigned long long ddrsize;
const char *prompt = "FSL DDR>";
unsigned int len;
char buffer[CONFIG_SYS_CBSIZE];
char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
int argc;
......@@ -1389,7 +1388,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
* No need to worry for buffer overflow here in
* this function; readline() maxes out at CFG_CBSIZE
*/
len = readline_into_buffer(prompt, buffer);
readline_into_buffer(prompt, buffer);
argc = parse_line(buffer, argv);
if (argc == 0)
continue;
......
arch/powerpc/include/asm/config_mpc85xx.h
浏览文件 @ 7708d8b3
......@@ -150,6 +150,7 @@
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
......@@ -237,6 +238,7 @@
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
......@@ -313,12 +315,15 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P2041)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
......@@ -331,12 +336,15 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
......@@ -349,6 +357,8 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P3060)
#define CONFIG_MAX_CPUS 8
......@@ -364,6 +374,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P4040)
#define CONFIG_MAX_CPUS 4
......@@ -374,6 +385,8 @@
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
......@@ -402,6 +415,8 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
/* P5010 is single core version of P5020 */
#elif defined(CONFIG_PPC_P5010)
......@@ -409,6 +424,7 @@
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
......@@ -421,12 +437,14 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P5020)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
......@@ -439,6 +457,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#else
#error Processor type not defined for this platform
......
arch/powerpc/include/asm/immap_85xx.h
浏览文件 @ 7708d8b3
......@@ -2420,6 +2420,7 @@ struct ccsr_rman {
#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
#ifdef CONFIG_TSECV2
#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
#else
......
arch/x86/config.mk
浏览文件 @ 7708d8b3
......@@ -41,3 +41,10 @@ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
LDFLAGS_FINAL += --gc-sections -pie
LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
PREFIXED_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/$(shell basename $(NORMAL_LIBGCC))
export USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC))
arch/x86/cpu/cpu.c
浏览文件 @ 7708d8b3
......@@ -37,6 +37,7 @@
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/interrupt.h>
#include <linux/compiler.h>
/*
* Constructor for a conventional segment GDT (or LDT) entry
......@@ -52,7 +53,7 @@
struct gdt_ptr {
u16 len;
u32 ptr;
} __attribute__((packed));
} __packed;
static void reload_gdt(void)
{
......@@ -115,14 +116,14 @@ int x86_cpu_init_r(void)
reload_gdt();
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts ();
cpu_init_interrupts();
return 0;
}
int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf ("resetting ...\n");
printf("resetting ...\n");
/* wait 50 ms */
udelay(50000);
......@@ -133,7 +134,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
void flush_cache (unsigned long dummy1, unsigned long dummy2)
void flush_cache(unsigned long dummy1, unsigned long dummy2)
{
asm("wbinvd\n");
}
......@@ -142,16 +143,16 @@ void __attribute__ ((regparm(0))) generate_gpf(void);
/* segment 0x70 is an arbitrary segment which does not exist */
asm(".globl generate_gpf\n"
".hidden generate_gpf\n"
".type generate_gpf, @function\n"
"generate_gpf:\n"
"ljmp $0x70, $0x47114711\n");
".hidden generate_gpf\n"
".type generate_gpf, @function\n"
"generate_gpf:\n"
"ljmp $0x70, $0x47114711\n");
void __reset_cpu(ulong addr)
{
printf("Resetting using x86 Triple Fault\n");
set_vector(13, generate_gpf); /* general protection fault handler */
set_vector(8, generate_gpf); /* double fault handler */
generate_gpf(); /* start the show */
set_vector(13, generate_gpf); /* general protection fault handler */
set_vector(8, generate_gpf); /* double fault handler */
generate_gpf(); /* start the show */
}
void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));
arch/x86/cpu/interrupts.c
浏览文件 @ 7708d8b3
......@@ -31,6 +31,7 @@
#include <asm/interrupt.h>
#include <asm/io.h>
#include <asm/processor-flags.h>
#include <linux/compiler.h>
#define DECLARE_INTERRUPT(x) \
".globl irq_"#x"\n" \
......@@ -83,22 +84,22 @@ static inline unsigned long get_debugreg(int regno)
switch (regno) {
case 0:
asm("mov %%db0, %0" :"=r" (val));
asm("mov %%db0, %0" : "=r" (val));
break;
case 1:
asm("mov %%db1, %0" :"=r" (val));
asm("mov %%db1, %0" : "=r" (val));
break;
case 2:
asm("mov %%db2, %0" :"=r" (val));
asm("mov %%db2, %0" : "=r" (val));
break;
case 3:
asm("mov %%db3, %0" :"=r" (val));
asm("mov %%db3, %0" : "=r" (val));
break;
case 6:
asm("mov %%db6, %0" :"=r" (val));
asm("mov %%db6, %0" : "=r" (val));
break;
case 7:
asm("mov %%db7, %0" :"=r" (val));
asm("mov %%db7, %0" : "=r" (val));
break;
default:
val = 0;
......@@ -120,7 +121,8 @@ void dump_regs(struct irq_regs *regs)
printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
regs->esi, regs->edi, regs->ebp, regs->esp);
printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
(u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss);
(u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
(u16)regs->xgs, (u16)regs->xss);
cr0 = read_cr0();
cr2 = read_cr2();
......@@ -164,21 +166,21 @@ struct idt_entry {
u8 res;
u8 access;
u16 base_high;
} __attribute__ ((packed));
} __packed;
struct desc_ptr {
unsigned short size;
unsigned long address;
unsigned short segment;
} __attribute__((packed));
} __packed;
struct idt_entry idt[256];
struct idt_entry idt[256] __attribute__((aligned(16)));
struct desc_ptr idt_ptr;
static inline void load_idt(const struct desc_ptr *dtr)
{
asm volatile("cs lidt %0"::"m" (*dtr));
asm volatile("cs lidt %0" : : "m" (*dtr));
}
void set_vector(u8 intnum, void *routine)
......@@ -187,6 +189,11 @@ void set_vector(u8 intnum, void *routine)
idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
}
/*
* Ideally these would be defined static to avoid a checkpatch warning, but
* the compiler cannot see them in the inline asm and complains that they
* aren't defined
*/
void irq_0(void);
void irq_1(void);
......@@ -201,7 +208,7 @@ int cpu_init_interrupts(void)
disable_interrupts();
/* Setup the IDT */
for (i=0;i<256;i++) {
for (i = 0; i < 256; i++) {
idt[i].access = 0x8e;
idt[i].res = 0;
idt[i].selector = 0x10;
......@@ -238,7 +245,7 @@ int disable_interrupts(void)
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */
return flags & X86_EFLAGS_IF;
}
/* IRQ Low-Level Service Routine */
......@@ -255,7 +262,7 @@ void irq_llsr(struct irq_regs *regs)
case 0x00:
printf("Divide Error (Division by zero)\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x01:
printf("Debug Interrupt (Single step)\n");
......@@ -272,32 +279,32 @@ void irq_llsr(struct irq_regs *regs)
case 0x04:
printf("Overflow\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x05:
printf("BOUND Range Exceeded\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x06:
printf("Invalid Opcode (UnDefined Opcode)\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x07:
printf("Device Not Available (No Math Coprocessor)\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x08:
printf("Double fault\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x09:
printf("Co-processor segment overrun\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x0a:
printf("Invalid TSS\n");
......@@ -306,12 +313,12 @@ void irq_llsr(struct irq_regs *regs)
case 0x0b:
printf("Segment Not Present\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x0c:
printf("Stack Segment Fault\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x0d:
printf("General Protection\n");
......@@ -320,7 +327,7 @@ void irq_llsr(struct irq_regs *regs)
case 0x0e:
printf("Page fault\n");
dump_regs(regs);
while(1);
hang();
break;
case 0x0f:
printf("Floating-Point Error (Math Fault)\n");
......
arch/x86/cpu/sc520/asm-offsets.c 0 → 100644
浏览文件 @ 7708d8b3
/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* This program is used to generate definitions needed by
* assembly language modules.
*
* We use the technique used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <common.h>
#include <asm/arch/sc520.h>
#include <linux/kbuild.h>
int main(void)
{
DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0]));
DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1]));
DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2]));
DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3]));
DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4]));
DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5]));
DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6]));
DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7]));
DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8]));
DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9]));
DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10]));
DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11]));
DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12]));
DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13]));
DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14]));
DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15]));
return 0;
}
arch/x86/cpu/sc520/sc520.c
浏览文件 @ 7708d8b3
......@@ -49,7 +49,7 @@ int cpu_init_f(void)
asm("movl $0x2000, %%ecx\n"
"0: pushl %%ecx\n"
"popl %%ecx\n"
"loop 0b\n": : : "ecx");
"loop 0b\n" : : : "ecx");
return x86_cpu_init_f();
}
......
arch/x86/cpu/sc520/sc520_car.S
浏览文件 @ 7708d8b3
......@@ -24,6 +24,7 @@
#include <config.h>
#include <asm/processor-flags.h>
#include <asm/arch/sc520.h>
#include <generated/asm-offsets.h>
.section .text
......@@ -55,7 +56,7 @@ car_init:
/* Configure Cache-As-RAM PAR */
movl $CONFIG_SYS_SC520_CAR_PAR, %eax
movl $SC520_PAR2, %edi
movl $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi
movl %eax, (%edi)
/* Trash the cache then turn it on */
......
arch/x86/cpu/sc520/sc520_pci.c
浏览文件 @ 7708d8b3
......@@ -70,26 +70,28 @@ int pci_sc520_set_irq(int pci_pin, int irq)
debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
if (irq < 0 || irq > 15) {
if (irq < 0 || irq > 15)
return -1; /* illegal irq */
}
if (pci_pin < 0 || pci_pin > 15) {
if (pci_pin < 0 || pci_pin > 15)
return -1; /* illegal pci int pin */
}
/* first disable any non-pci interrupt source that use
* this level */
/* PCI interrupt mapping (A through D)*/
for (i=0; i<=3 ;i++) {
if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority)
for (i = 0; i <= 3 ; i++) {
tmpb = readb(&sc520_mmcr->pci_int_map[i]);
if (tmpb == sc520_irq[irq].priority)
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
}
/* GP IRQ interrupt mapping */
for (i=0; i<=10 ;i++) {
if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority)
for (i = 0; i <= 10 ; i++) {
tmpb = readb(&sc520_mmcr->gp_int_map[i]);
if (tmpb == sc520_irq[irq].priority)
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
}
......@@ -102,10 +104,12 @@ int pci_sc520_set_irq(int pci_pin, int irq)
if (pci_pin < 4) {
/* PCI INTA-INTD */
/* route the interrupt */
writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]);
writeb(sc520_irq[irq].priority,
&sc520_mmcr->pci_int_map[pci_pin]);
} else {
/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]);
writeb(sc520_irq[irq].priority,
&sc520_mmcr->gp_int_map[pci_pin - 4]);
/* also set the polarity in this case */
tmpw = readw(&sc520_mmcr->intpinpol);
......@@ -126,9 +130,7 @@ void pci_sc520_init(struct pci_controller *hose)
hose->last_busno = 0xff;
hose->region_count = pci_set_regions(hose);
pci_setup_type1(hose,
SC520_REG_ADDR,
SC520_REG_DATA);
pci_setup_type1(hose);
pci_register_hose(hose);
......
arch/x86/cpu/sc520/sc520_sdram.c
浏览文件 @ 7708d8b3
......@@ -40,9 +40,6 @@ static void sc520_set_dram_timing(void);
static void sc520_set_dram_refresh_rate(void);
static void sc520_enable_dram_refresh(void);
static void sc520_enable_sdram(void);
#if CONFIG_SYS_SDRAM_ECC_ENABLE
static void sc520_enable_ecc(void)
#endif
int dram_init_f(void)
{
......@@ -51,9 +48,6 @@ int dram_init_f(void)
sc520_set_dram_refresh_rate();
sc520_enable_dram_refresh();
sc520_enable_sdram();
#if CONFIG_SYS_SDRAM_ECC_ENABLE
sc520_enable_ecc();
#endif
return 0;
}
......@@ -426,53 +420,6 @@ static void sc520_sizemem(void)
writel(0x00000000, &sc520_mmcr->par[4]);
}
#if CONFIG_SYS_SDRAM_ECC_ENABLE
static void sc520_enable_ecc(void)
/* A nominal memory test: just a byte at each address line */
movl %eax, %ecx
shrl $0x1, %ecx
movl $0x1, %edi
memtest0:
movb $0xa5, (%edi)
cmpb $0xa5, (%edi)
jne out
shrl $0x1, %ecx
andl %ecx, %ecx
jz set_ecc
shll $0x1, %edi
jmp memtest0
set_ecc:
/* clear all ram with a memset */
movl %eax, %ecx
xorl %esi, %esi
xorl %edi, %edi
xorl %eax, %eax
shrl $0x2, %ecx
cld
rep stosl
/* enable read, write buffers */
movb $0x11, %al
movl $DBCTL, %edi
movb %al, (%edi)
/* enable NMI mapping for ECC */
movl $ECCINT, %edi
movb $0x10, %al
movb %al, (%edi)
/* Turn on ECC */
movl $ECCCTL, %edi
movb $0x05, %al
movb %al,(%edi)
out:
jmp init_ecc_ret
}
#endif
int dram_init(void)
{
ulong dram_ctrl;
......
arch/x86/cpu/sc520/sc520_ssi.c
浏览文件 @ 7708d8b3
......@@ -28,37 +28,33 @@
int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
{
u8 temp=0;
u8 temp = 0;
if (freq >= 8192) {
if (freq >= 8192)
temp |= CTL_CLK_SEL_4;
} else if (freq >= 4096) {
else if (freq >= 4096)
temp |= CTL_CLK_SEL_8;
} else if (freq >= 2048) {
else if (freq >= 2048)
temp |= CTL_CLK_SEL_16;
} else if (freq >= 1024) {
else if (freq >= 1024)
temp |= CTL_CLK_SEL_32;
} else if (freq >= 512) {
else if (freq >= 512)
temp |= CTL_CLK_SEL_64;
} else if (freq >= 256) {
else if (freq >= 256)
temp |= CTL_CLK_SEL_128;
} else if (freq >= 128) {
else if (freq >= 128)
temp |= CTL_CLK_SEL_256;
} else {
else
temp |= CTL_CLK_SEL_512;
}
if (!lsb_first) {
if (!lsb_first)
temp |= MSBF_ENB;
}
if (inv_clock) {
if (inv_clock)
temp |= CLK_INV_ENB;
}
if (inv_phase) {
if (inv_phase)
temp |= PHS_INV_ENB;
}
writeb(temp, &sc520_mmcr->ssictl);
......@@ -68,9 +64,11 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
u8 ssi_txrx_byte(u8 data)
{
writeb(data, &sc520_mmcr->ssixmit);
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
;
writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
;
return readb(&sc520_mmcr->ssircv);
}
......@@ -78,15 +76,18 @@ u8 ssi_txrx_byte(u8 data)
void ssi_tx_byte(u8 data)
{
writeb(data, &sc520_mmcr->ssixmit);
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
;
writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
}
u8 ssi_rx_byte(void)
{
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
;
writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
;
return readb(&sc520_mmcr->ssircv);
}
arch/x86/cpu/sc520/sc520_timer.c
浏览文件 @ 7708d8b3
......@@ -38,7 +38,7 @@ void sc520_timer_isr(void)
int timer_init(void)
{
/* Register the SC520 specific timer interrupt handler */
register_timer_isr (sc520_timer_isr);
register_timer_isr(sc520_timer_isr);
/* Install interrupt handler for GP Timer 1 */
irq_install_handler (0, timer_isr, NULL);
......@@ -62,7 +62,7 @@ int timer_init(void)
writew(100, &sc520_mmcr->gptmr1maxcmpa);
writew(0xe009, &sc520_mmcr->gptmr1ctl);
unmask_irq (0);
unmask_irq(0);
/* Clear the GP Timer 1 status register to get the show rolling*/
writeb(0x02, &sc520_mmcr->gptmrsta);
......
arch/x86/cpu/start.S
浏览文件 @ 7708d8b3
......@@ -30,6 +30,7 @@
#include <version.h>
#include <asm/global_data.h>
#include <asm/processor-flags.h>
#include <generated/asm-offsets.h>
.section .text
.code32
......@@ -47,14 +48,12 @@ _x86boot_start:
cli
cld
/* Turn of cache (this might require a 486-class CPU) */
/* Turn off cache (this might require a 486-class CPU) */
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd
/* Tell 32-bit code it is being entered from an in-RAM copy */
movw $GD_FLG_WARM_BOOT, %bx
_start:
/* This is the 32-bit cold-reset entry point */
......@@ -114,7 +113,7 @@ relocate_code:
/* Setup call address of in-RAM copy of board_init_r() */
movl $board_init_r, %ebp
addl (GD_RELOC_OFF * 4)(%edx), %ebp
addl (GENERATED_GD_RELOC_OFF)(%edx), %ebp
/* Setup parameters to board_init_r() */
movl %edx, %eax
......@@ -123,10 +122,31 @@ relocate_code:
/* Jump to in-RAM copy of board_init_r() */
call *%ebp
die: hlt
die:
hlt
jmp die
hlt
blank_idt_ptr:
.word 0 /* limit */
.long 0 /* base */
.p2align 2 /* force 4-byte alignment */
multiboot_header:
/* magic */
.long 0x1BADB002
/* flags */
.long (1 << 16)
/* checksum */
.long -0x1BADB002 - (1 << 16)
/* header addr */
.long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE
/* load addr */
.long CONFIG_SYS_TEXT_BASE
/* load end addr */
.long 0
/* bss end addr */
.long 0
/* entry addr */
.long CONFIG_SYS_TEXT_BASE
arch/x86/cpu/start16.S
浏览文件 @ 7708d8b3
......@@ -37,9 +37,6 @@
.code16
.globl start16
start16:
/* Set the Cold Boot / Hard Reset flag */
movl $GD_FLG_COLD_BOOT, %ebx
/*
* First we let the BSP do some early initialization
* this code have to map the flash to its final position
......
arch/x86/include/asm/arch-sc520/sc520.h
浏览文件 @ 7708d8b3
......@@ -259,32 +259,6 @@ extern sc520_mmcr_t *sc520_mmcr;
/* Memory Mapped Control Registers (MMCR) Base Address */
#define SC520_MMCR_BASE 0xfffef000
/* MMCR Addresses (required for assembler code) */
#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010)
#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012)
#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014)
#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018)
#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020)
#define SC520_DBCTL (SC520_MMCR_BASE + 0x040)
#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18)
#define SC520_PAR0 (SC520_MMCR_BASE + 0x088)
#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1))
#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2))
#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3))
#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4))
#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5))
#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6))
#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7))
#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8))
#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9))
#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10))
#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11))
#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12))
#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13))
#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14))
#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
/*
* PARs for maximum allowable 256MB of SDRAM @ 0x00000000
* Two PARs are required due to maximum PAR size of 128MB
......
arch/x86/include/asm/global_data.h
浏览文件 @ 7708d8b3
......@@ -61,25 +61,6 @@ extern gd_t *gd;
#endif
/* Word Offsets into Global Data - MUST match struct gd_t */
#define GD_BD 0
#define GD_FLAGS 1
#define GD_BAUDRATE 2
#define GD_HAVE_CONSOLE 3
#define GD_RELOC_OFF 4
#define GD_LOAD_OFF 5
#define GD_ENV_ADDR 6
#define GD_ENV_VALID 7
#define GD_CPU_CLK 8
#define GD_BUS_CLK 9
#define GD_RELOC_ADDR 10
#define GD_START_ADDR_SP 11
#define GD_RAM_SIZE 12
#define GD_RESET_STATUS 13
#define GD_JT 14
#define GD_SIZE 15
/*
* Global Data Flags
*/
......@@ -91,8 +72,6 @@ extern gd_t *gd;
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */
#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */
#if 0
#define DECLARE_GLOBAL_DATA_PTR
......
arch/x86/include/asm/pci.h
浏览文件 @ 7708d8b3
......@@ -26,7 +26,10 @@
#ifndef _PCI_I386_H_
#define _PCI_I386_H_ 1
void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
#define DEFINE_PCI_DEVICE_TABLE(_table) \
const struct pci_device_id _table[]
void pci_setup_type1(struct pci_controller *hose);
int pci_enable_legacy_video_ports(struct pci_controller* hose);
int pci_shadow_rom(pci_dev_t dev, unsigned char *dest);
void pci_remove_rom_window(struct pci_controller* hose, u32 addr);
......
arch/x86/include/asm/realmode.h
浏览文件 @ 7708d8b3
......@@ -25,6 +25,10 @@
#define __ASM_REALMODE_H_
#include <asm/ptrace.h>
extern ulong __realmode_start;
extern ulong __realmode_size;
extern char realmode_enter;
int bios_setup(void);
int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out);
int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out);
......
arch/x86/include/asm/string.h
浏览文件 @ 7708d8b3
......@@ -23,7 +23,7 @@ extern void * memmove(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMCHR
extern void * memchr(const void *, int, __kernel_size_t);
#undef __HAVE_ARCH_MEMSET
#define __HAVE_ARCH_MEMSET
extern void * memset(void *, int, __kernel_size_t);
#undef __HAVE_ARCH_MEMZERO
......
arch/x86/include/asm/u-boot-x86.h
浏览文件 @ 7708d8b3
......@@ -24,6 +24,14 @@
#ifndef _U_BOOT_I386_H_
#define _U_BOOT_I386_H_ 1
/* Exports from the Linker Script */
extern ulong __text_start;
extern ulong __data_end;
extern ulong __rel_dyn_start;
extern ulong __rel_dyn_end;
extern ulong __bss_start;
extern ulong __bss_end;
/* cpu/.../cpu.c */
int x86_cpu_init_r(void);
int cpu_init_r(void);
......
arch/x86/lib/Makefile
浏览文件 @ 7708d8b3
......@@ -25,23 +25,25 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(ARCH).o
SOBJS-y += bios.o
SOBJS-y += bios_pci.o
SOBJS-y += realmode_switch.o
SOBJS-$(CONFIG_SYS_PC_BIOS) += bios.o
SOBJS-$(CONFIG_SYS_PCI_BIOS) += bios_pci.o
SOBJS-$(CONFIG_SYS_X86_REALMODE) += realmode_switch.o
COBJS-y += bios_setup.o
COBJS-$(CONFIG_SYS_PC_BIOS) += bios_setup.o
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-y += gcc.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_PCI) += pci_type1.o
COBJS-y += realmode.o
COBJS-y += timer.o
COBJS-y += video_bios.o
COBJS-y += video.o
COBJS-y += zimage.o
COBJS-$(CONFIG_SYS_X86_REALMODE) += realmode.o
COBJS-y += string.o
COBJS-$(CONFIG_SYS_X86_ISR_TIMER) += timer.o
COBJS-$(CONFIG_VIDEO) += video_bios.o
COBJS-$(CONFIG_VIDEO) += video.o
COBJS-$(CONFIG_CMD_ZBOOT) += zimage.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
......@@ -49,6 +51,11 @@ OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
$(PREFIXED_LIBGCC): $(NORMAL_LIBGCC)
$(OBJCOPY) $< $@ --prefix-symbols=__normal_
$(LIB): $(PREFIXED_LIBGCC)
#########################################################################
# defines $(obj).depend target
......
arch/x86/lib/bios.h
浏览文件 @ 7708d8b3
......@@ -24,69 +24,150 @@
#ifndef _BIOS_H_
#define _BIOS_H_
#define OFFS_ES 0 /* 16bit */
#define OFFS_GS 2 /* 16bit */
#define OFFS_DS 4 /* 16bit */
#define OFFS_EDI 6 /* 32bit */
#define OFFS_DI 6 /* low 16 bits of EDI */
#define OFFS_ESI 10 /* 32bit */
#define OFFS_SI 10 /* low 16 bits of ESI */
#define OFFS_EBP 14 /* 32bit */
#define OFFS_BP 14 /* low 16 bits of EBP */
#define OFFS_ESP 18 /* 32bit */
#define OFFS_SP 18 /* low 16 bits of ESP */
#define OFFS_EBX 22 /* 32bit */
#define OFFS_BX 22 /* low 16 bits of EBX */
#define OFFS_BL 22 /* low 8 bits of BX */
#define OFFS_BH 23 /* high 8 bits of BX */
#define OFFS_EDX 26 /* 32bit */
#define OFFS_DX 26 /* low 16 bits of EBX */
#define OFFS_DL 26 /* low 8 bits of BX */
#define OFFS_DH 27 /* high 8 bits of BX */
#define OFFS_ECX 30 /* 32bit */
#define OFFS_CX 30 /* low 16 bits of EBX */
#define OFFS_CL 30 /* low 8 bits of BX */
#define OFFS_CH 31 /* high 8 bits of BX */
#define OFFS_EAX 34 /* 32bit */
#define OFFS_AX 34 /* low 16 bits of EBX */
#define OFFS_AL 34 /* low 8 bits of BX */
#define OFFS_AH 35 /* high 8 bits of BX */
#define OFFS_VECTOR 38 /* 16bit */
#define OFFS_IP 40 /* 16bit */
#define OFFS_CS 42 /* 16bit */
#define OFFS_FLAGS 44 /* 16bit */
#define OFFS_ES 0 /* 16bit */
#define OFFS_GS 2 /* 16bit */
#define OFFS_DS 4 /* 16bit */
#define OFFS_EDI 6 /* 32bit */
#define OFFS_DI 6 /* low 16 bits of EDI */
#define OFFS_ESI 10 /* 32bit */
#define OFFS_SI 10 /* low 16 bits of ESI */
#define OFFS_EBP 14 /* 32bit */
#define OFFS_BP 14 /* low 16 bits of EBP */
#define OFFS_ESP 18 /* 32bit */
#define OFFS_SP 18 /* low 16 bits of ESP */
#define OFFS_EBX 22 /* 32bit */
#define OFFS_BX 22 /* low 16 bits of EBX */
#define OFFS_BL 22 /* low 8 bits of BX */
#define OFFS_BH 23 /* high 8 bits of BX */
#define OFFS_EDX 26 /* 32bit */
#define OFFS_DX 26 /* low 16 bits of EBX */
#define OFFS_DL 26 /* low 8 bits of BX */
#define OFFS_DH 27 /* high 8 bits of BX */
#define OFFS_ECX 30 /* 32bit */
#define OFFS_CX 30 /* low 16 bits of EBX */
#define OFFS_CL 30 /* low 8 bits of BX */
#define OFFS_CH 31 /* high 8 bits of BX */
#define OFFS_EAX 34 /* 32bit */
#define OFFS_AX 34 /* low 16 bits of EBX */
#define OFFS_AL 34 /* low 8 bits of BX */
#define OFFS_AH 35 /* high 8 bits of BX */
#define OFFS_VECTOR 38 /* 16bit */
#define OFFS_IP 40 /* 16bit */
#define OFFS_CS 42 /* 16bit */
#define OFFS_FLAGS 44 /* 16bit */
#define SEGMENT 0x40
#define STACK 0x800 /* stack at 0x40:0x800 -> 0x800 */
/* stack at 0x40:0x800 -> 0x800 */
#define SEGMENT 0x40
#define STACK 0x800
/* save general registers */
/* save some segments */
/* save callers stack segment .. */
/* ... in gs */
/* setup my segments */
/* setup BIOS stackpointer */
#define MAKE_BIOS_STACK \
pushal; \
pushw %ds; \
pushw %gs; \
pushw %es; \
pushw %ss; \
popw %gs; \
movw $SEGMENT, %ax; \
movw %ax, %ds; \
movw %ax, %es; \
movw %ax, %ss; \
movw %sp, %bp; \
/*
* save general registers
* save some segments
* save callers stack segment
* setup BIOS segments
* setup BIOS stackpointer
*/
#define MAKE_BIOS_STACK \
pushal; \
pushw %ds; \
pushw %gs; \
pushw %es; \
pushw %ss; \
popw %gs; \
movw $SEGMENT, %ax; \
movw %ax, %ds; \
movw %ax, %es; \
movw %ax, %ss; \
movw %sp, %bp; \
movw $STACK, %sp
#define RESTORE_CALLERS_STACK \
pushw %gs; /* restore callers stack segment */ \
popw %ss; \
movw %bp, %sp; /* restore stackpointer */ \
popw %es; /* restore segment selectors */ \
popw %gs; \
popw %ds; \
popal /* restore GP registers */
/*
* restore callers stack segment
* restore some segments
* restore general registers
*/
#define RESTORE_CALLERS_STACK \
pushw %gs; \
popw %ss; \
movw %bp, %sp; \
popw %es; \
popw %gs; \
popw %ds; \
popal
#ifndef __ASSEMBLY__
#define BIOS_DATA ((char *)0x400)
#define BIOS_DATA_SIZE 256
#define BIOS_BASE ((char *)0xf0000)
#define BIOS_CS 0xf000
extern ulong __bios_start;
extern ulong __bios_size;
/* these are defined in a 16bit segment and needs
* to be accessed with the RELOC_16_xxxx() macros below
*/
extern u16 ram_in_64kb_chunks;
extern u16 bios_equipment;
extern u8 pci_last_bus;
extern void *rm_int00;
extern void *rm_int01;
extern void *rm_int02;
extern void *rm_int03;
extern void *rm_int04;
extern void *rm_int05;
extern void *rm_int06;
extern void *rm_int07;
extern void *rm_int08;
extern void *rm_int09;
extern void *rm_int0a;
extern void *rm_int0b;
extern void *rm_int0c;
extern void *rm_int0d;
extern void *rm_int0e;
extern void *rm_int0f;
extern void *rm_int10;
extern void *rm_int11;
extern void *rm_int12;
extern void *rm_int13;
extern void *rm_int14;
extern void *rm_int15;
extern void *rm_int16;
extern void *rm_int17;
extern void *rm_int18;
extern void *rm_int19;
extern void *rm_int1a;
extern void *rm_int1b;
extern void *rm_int1c;
extern void *rm_int1d;
extern void *rm_int1e;
extern void *rm_int1f;
extern void *rm_def_int;
extern void *realmode_reset;
extern void *realmode_pci_bios_call_entry;
#define RELOC_16_LONG(seg, off) (*(u32 *)(seg << 4 | (u32)&off))
#define RELOC_16_WORD(seg, off) (*(u16 *)(seg << 4 | (u32)&off))
#define RELOC_16_BYTE(seg, off) (*(u8 *)(seg << 4 | (u32)&off))
#ifdef PCI_BIOS_DEBUG
extern u32 num_pci_bios_present;
extern u32 num_pci_bios_find_device;
extern u32 num_pci_bios_find_class;
extern u32 num_pci_bios_generate_special_cycle;
extern u32 num_pci_bios_read_cfg_byte;
extern u32 num_pci_bios_read_cfg_word;
extern u32 num_pci_bios_read_cfg_dword;
extern u32 num_pci_bios_write_cfg_byte;
extern u32 num_pci_bios_write_cfg_word;
extern u32 num_pci_bios_write_cfg_dword;
extern u32 num_pci_bios_get_irq_routing;
extern u32 num_pci_bios_set_irq;
extern u32 num_pci_bios_unknown_function;
#endif
#endif
#endif
arch/x86/lib/bios_pci.S
浏览文件 @ 7708d8b3
......@@ -80,11 +80,15 @@ cs incl num_pci_bios_present
#endif
movl $0x20494350, %eax
gs movl %eax, OFFS_EDX(%bp)
/* We support cfg type 1 version 2.10 */
movb $0x01, %al
gs movb %al, OFFS_AL(%bp) /* We support cfg type 1 */
movw $0x0210, %ax /* version 2.10 */
gs movb %al, OFFS_AL(%bp)
movw $0x0210, %ax
gs movw %ax, OFFS_BX(%bp)
cs movb pci_last_bus, %al /* last bus number */
/* last bus number */
cs movb pci_last_bus, %al
gs movb %al, OFFS_CL(%bp)
jmp clear_carry
......@@ -97,16 +101,22 @@ cs incl num_pci_bios_find_device
#endif
gs movw OFFS_CX(%bp), %di
shll $16, %edi
gs movw OFFS_DX(%bp), %di /* edi now holds device in upper 16
* bits and vendor in lower 16 bits */
gs movw OFFS_DX(%bp), %di
/* edi now holds device in upper 16 bits and vendor in lower 16 bits */
gs movw OFFS_SI(%bp), %si
xorw %bx, %bx /* start at bus 0 dev 0 function 0 */
/* start at bus 0 dev 0 function 0 */
xorw %bx, %bx
pfd_loop:
xorw %ax, %ax /* dword 0 is vendor/device */
/* dword 0 is vendor/device */
xorw %ax, %ax
call __pci_bios_select_register
movw $0xcfc, %dx
inl %dx, %eax
cmpl %edi, %eax /* our device ? */
/* our device ? */
cmpl %edi, %eax
je pfd_found_one
pfd_next_dev:
/* check for multi function devices */
......@@ -120,13 +130,16 @@ pfd_next_dev:
andb $0x80, %al
jz pfd_not_multi_function
pfd_function_not_zero:
incw %bx /* next function, overflows in to
* device number, then bus number */
/* next function, overflows in to device number, then bus number */
incw %bx
jmp pfd_check_bus
pfd_not_multi_function:
andw $0xfff8, %bx /* remove function bits */
addw $0x0008, %bx /* next device, overflows in to bus number */
/* remove function bits */
andw $0xfff8, %bx
/* next device, overflows in to bus number */
addw $0x0008, %bx
pfd_check_bus:
cs movb pci_last_bus, %ah
cmpb %ah, %bh
......@@ -142,7 +155,8 @@ gs movw %bx, OFFS_BX(%bp)
jmp clear_carry
pfd_not_found:
movb $0x86, %ah /* device not found */
/* device not found */
movb $0x86, %ah
jmp set_carry
/*****************************************************************************/
......@@ -152,17 +166,24 @@ pci_bios_find_class:
cs incl num_pci_bios_find_class
#endif
gs movl OFFS_ECX(%bp), %edi
andl $0x00ffffff, %edi /* edi now holds class-code in lower 24 bits */
/* edi now holds class-code in lower 24 bits */
andl $0x00ffffff, %edi
gs movw OFFS_SI(%bp), %si
xorw %bx, %bx /* start at bus 0 dev 0 function 0 */
/* start at bus 0 dev 0 function 0 */
xorw %bx, %bx
pfc_loop:
movw $8, %ax /* dword 8 is class-code high 24bits */
/* dword 8 is class-code high 24bits */
movw $8, %ax
call __pci_bios_select_register
movw $0xcfc, %dx
inl %dx, %eax
shrl $8, %eax
andl $0x00ffffff, %eax
cmpl %edi, %eax /* our device ? */
/* our device ? */
cmpl %edi, %eax
je pfc_found_one
pfc_next_dev:
/* check for multi function devices */
......@@ -175,13 +196,16 @@ pfc_next_dev:
andb $0x80, %al
jz pfc_not_multi_function
pfc_function_not_zero:
incw %bx /* next function, overflows in to
* device number, then bus number */
/* next function, overflows in to device number, then bus number */
incw %bx
jmp pfc_check_bus
pfc_not_multi_function:
andw $0xfff8, %bx /* remove function bits */
addw $0x0008, %bx /* next device, overflows in to bus number */
/* remove function bits */
andw $0xfff8, %bx
/* next device, overflows in to bus number */
addw $0x0008, %bx
pfc_check_bus:
cs movb pci_last_bus, %ah
cmpb %ah, %bh
......@@ -197,7 +221,8 @@ gs movw %bx, OFFS_BX(%bp)
jmp clear_carry
pfc_not_found:
movb $0x86, %ah /* device not found */
/* device not found */
movb $0x86, %ah
jmp set_carry
/*****************************************************************************/
......@@ -206,7 +231,8 @@ pci_bios_generate_special_cycle:
#ifdef PCI_BIOS_DEBUG
cs incl num_pci_bios_generate_special_cycle
#endif
movb $0x81, %ah /* function not supported */
/* function not supported */
movb $0x81, %ah
jmp set_carry
/*****************************************************************************/
......@@ -296,7 +322,8 @@ pci_bios_get_irq_routing:
#ifdef PCI_BIOS_DEBUG
cs incl num_pci_bios_get_irq_routing
#endif
movb $0x81, %ah /* function not supported */
/* function not supported */
movb $0x81, %ah
jmp set_carry
/*****************************************************************************/
......@@ -305,7 +332,8 @@ pci_bios_set_irq:
#ifdef PCI_BIOS_DEBUG
cs incl num_pci_bios_set_irq
#endif
movb $0x81, %ah /* function not supported */
/* function not supported */
movb $0x81, %ah
jmp set_carry
/*****************************************************************************/
......@@ -314,7 +342,8 @@ unknown_function:
#ifdef PCI_BIOS_DEBUG
cs incl num_pci_bios_unknown_function
#endif
movb $0x81, %ah /* function not supported */
/* function not supported */
movb $0x81, %ah
jmp set_carry
/*****************************************************************************/
......@@ -323,7 +352,8 @@ pci_bios_select_register:
gs movw OFFS_BX(%bp), %bx
gs movw OFFS_DI(%bp), %ax
/* destroys eax, dx */
__pci_bios_select_register: /* BX holds device id, AX holds register index */
__pci_bios_select_register:
/* BX holds device id, AX holds register index */
pushl %ebx
andl $0xfc, %eax
andl $0xffff, %ebx
......@@ -338,7 +368,9 @@ __pci_bios_select_register: /* BX holds device id, AX holds regist
clear_carry:
gs movw OFFS_FLAGS(%bp), %ax
andw $0xfffe, %ax /* clear carry -- function succeeded */
/* clear carry -- function succeeded */
andw $0xfffe, %ax
gs movw %ax, OFFS_FLAGS(%bp)
xorw %ax, %ax
gs movb %ah, OFFS_AH(%bp)
......@@ -347,7 +379,9 @@ gs movb %ah, OFFS_AH(%bp)
set_carry:
gs movb %ah, OFFS_AH(%bp)
gs movw OFFS_FLAGS(%bp), %ax
orw $1, %ax /* return carry -- function not supported */
/* return carry -- function not supported */
orw $1, %ax
gs movw %ax, OFFS_FLAGS(%bp)
movw $-1, %ax
ret
......
arch/x86/lib/bios_setup.c
浏览文件 @ 7708d8b3
......@@ -34,74 +34,22 @@
#include <pci.h>
#include <asm/realmode.h>
#include <asm/io.h>
#include "bios.h"
DECLARE_GLOBAL_DATA_PTR;
#define NUMVECTS 256
#define BIOS_DATA ((char*)0x400)
#define BIOS_DATA_SIZE 256
#define BIOS_BASE ((char*)0xf0000)
#define BIOS_CS 0xf000
extern ulong __bios_start;
extern ulong __bios_size;
/* these are defined in a 16bit segment and needs
* to be accessed with the RELOC_16_xxxx() macros below
*/
extern u16 ram_in_64kb_chunks;
extern u16 bios_equipment;
extern u8 pci_last_bus;
extern void *rm_int00;
extern void *rm_int01;
extern void *rm_int02;
extern void *rm_int03;
extern void *rm_int04;
extern void *rm_int05;
extern void *rm_int06;
extern void *rm_int07;
extern void *rm_int08;
extern void *rm_int09;
extern void *rm_int0a;
extern void *rm_int0b;
extern void *rm_int0c;
extern void *rm_int0d;
extern void *rm_int0e;
extern void *rm_int0f;
extern void *rm_int10;
extern void *rm_int11;
extern void *rm_int12;
extern void *rm_int13;
extern void *rm_int14;
extern void *rm_int15;
extern void *rm_int16;
extern void *rm_int17;
extern void *rm_int18;
extern void *rm_int19;
extern void *rm_int1a;
extern void *rm_int1b;
extern void *rm_int1c;
extern void *rm_int1d;
extern void *rm_int1e;
extern void *rm_int1f;
extern void *rm_def_int;
extern void *realmode_reset;
extern void *realmode_pci_bios_call_entry;
static int set_jmp_vector(int entry_point, void *target)
{
if (entry_point & ~0xffff) {
if (entry_point & ~0xffff)
return -1;
}
if (((u32)target-0xf0000) & ~0xffff) {
if (((u32)target - 0xf0000) & ~0xffff)
return -1;
}
printf("set_jmp_vector: 0xf000:%04x -> %p\n",
entry_point, target);
entry_point, target);
/* jmp opcode */
writeb(0xea, 0xf0000 + entry_point);
......@@ -115,51 +63,42 @@ static int set_jmp_vector(int entry_point, void *target)
return 0;
}
/*
************************************************************
* Install an interrupt vector
************************************************************
*/
/* Install an interrupt vector */
static void setvector(int vector, u16 segment, void *handler)
{
u16 *ptr = (u16*)(vector*4);
ptr[0] = ((u32)handler - (segment << 4))&0xffff;
u16 *ptr = (u16 *)(vector * 4);
ptr[0] = ((u32)handler - (segment << 4)) & 0xffff;
ptr[1] = segment;
#if 0
printf("setvector: int%02x -> %04x:%04x\n",
vector, ptr[1], ptr[0]);
vector, ptr[1], ptr[0]);
#endif
}
#define RELOC_16_LONG(seg, off) *(u32*)(seg << 4 | (u32)&off)
#define RELOC_16_WORD(seg, off) *(u16*)(seg << 4 | (u32)&off)
#define RELOC_16_BYTE(seg, off) *(u8*)(seg << 4 | (u32)&off)
int bios_setup(void)
{
ulong bios_start = (ulong)&__bios_start + gd->reloc_off;
/* The BIOS section is not relocated and still in the ROM. */
ulong bios_start = (ulong)&__bios_start;
ulong bios_size = (ulong)&__bios_size;
static int done=0;
static int done;
int vector;
#ifdef CONFIG_PCI
struct pci_controller *pri_hose;
#endif
if (done) {
if (done)
return 0;
}
done = 1;
if (bios_size > 65536) {
printf("BIOS too large (%ld bytes, max is 65536)\n",
bios_size);
bios_size);
return -1;
}
memcpy(BIOS_BASE, (void*)bios_start, bios_size);
memcpy(BIOS_BASE, (void *)bios_start, bios_size);
/* clear bda */
memset(BIOS_DATA, 0, BIOS_DATA_SIZE);
......@@ -178,9 +117,8 @@ int bios_setup(void)
/* setup realmode interrupt vectors */
for (vector = 0; vector < NUMVECTS; vector++) {
for (vector = 0; vector < NUMVECTS; vector++)
setvector(vector, BIOS_CS, &rm_def_int);
}
setvector(0x00, BIOS_CS, &rm_int00);
setvector(0x01, BIOS_CS, &rm_int01);
......
arch/x86/lib/board.c
浏览文件 @ 7708d8b3
......@@ -56,15 +56,6 @@
#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
/* Exports from the Linker Script */
extern ulong __text_start;
extern ulong __data_end;
extern ulong __rel_dyn_start;
extern ulong __rel_dyn_end;
extern ulong __bss_start;
extern ulong __bss_end;
/************************************************************************
* Init Utilities *
************************************************************************
......@@ -72,49 +63,41 @@ extern ulong __bss_end;
* or dropped completely,
* but let's get it working (again) first...
*/
static int init_baudrate (void)
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
return 0;
}
static int display_banner (void)
static int display_banner(void)
{
printf ("\n\n%s\n\n", version_string);
/*
printf ("U-Boot code: %08lX -> %08lX data: %08lX -> %08lX\n"
" BSS: %08lX -> %08lX stack: %08lX -> %08lX\n",
i386boot_start, i386boot_romdata_start-1,
i386boot_romdata_dest, i386boot_romdata_dest+i386boot_romdata_size-1,
i386boot_bss_start, i386boot_bss_start+i386boot_bss_size-1,
i386boot_bss_start+i386boot_bss_size,
i386boot_bss_start+i386boot_bss_size+CONFIG_SYS_STACK_SIZE-1);
*/
printf("\n\n%s\n\n", version_string);
return (0);
return 0;
}
static int display_dram_config (void)
static int display_dram_config(void)
{
int i;
puts ("DRAM Configuration:\n");
puts("DRAM Configuration:\n");
for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
print_size (gd->bd->bi_dram[i].size, "\n");
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
print_size(gd->bd->bi_dram[i].size, "\n");
}
return (0);
return 0;
}
static void display_flash_config (ulong size)
#ifndef CONFIG_SYS_NO_FLASH
static void display_flash_config(ulong size)
{
puts ("Flash: ");
print_size (size, "\n");
puts("Flash: ");
print_size(size, "\n");
}
#endif
/*
* Breath some life into the board...
......@@ -178,19 +161,26 @@ gd_t *gd;
static int calculate_relocation_address(void)
{
void *text_start = &__text_start;
void *bss_end = &__bss_end;
void *dest_addr;
ulong text_start = (ulong)&__text_start;
ulong bss_end = (ulong)&__bss_end;
ulong dest_addr;
ulong rel_offset;
/* Calculate destination RAM Address and relocation offset */
dest_addr = (void *)gd->ram_size;
dest_addr = gd->ram_size;
dest_addr -= CONFIG_SYS_STACK_SIZE;
dest_addr -= (bss_end - text_start);
/*
* Round destination address down to 16-byte boundary to keep
* IDT and GDT 16-byte aligned
*/
dest_addr &= ~15;
rel_offset = dest_addr - text_start;
gd->start_addr_sp = gd->ram_size;
gd->relocaddr = (ulong)dest_addr;
gd->relocaddr = dest_addr;
gd->reloc_off = rel_offset;
return 0;
......@@ -214,7 +204,7 @@ static int clear_bss(void)
void *bss_end = &__bss_end;
ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off);
ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);;
ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);
while (dst_addr < end_addr)
*dst_addr++ = 0x00000000;
......@@ -227,10 +217,30 @@ static int do_elf_reloc_fixups(void)
Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
Elf32_Addr *offset_ptr_rom;
Elf32_Addr *offset_ptr_ram;
/* The size of the region of u-boot that runs out of RAM. */
uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
do {
if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE)
if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) >= CONFIG_SYS_TEXT_BASE)
*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) += gd->reloc_off;
/* Get the location from the relocation entry */
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* Check that the location of the relocation is in .text */
if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE) {
/* Switch to the in-RAM version */
offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
gd->reloc_off);
/* Check that the target points into .text */
if (*offset_ptr_ram >= CONFIG_SYS_TEXT_BASE &&
*offset_ptr_ram <
(CONFIG_SYS_TEXT_BASE + size)) {
*offset_ptr_ram += gd->reloc_off;
}
}
} while (re_src++ < re_end);
return 0;
......@@ -254,13 +264,18 @@ void board_init_f(ulong boot_flags)
relocate_code(gd->start_addr_sp, gd, gd->relocaddr);
/* NOTREACHED - relocate_code() does not return */
while(1);
while (1)
;
}
void board_init_r(gd_t *id, ulong dest_addr)
{
#if defined(CONFIG_CMD_NET)
char *s;
#endif
#ifndef CONFIG_SYS_NO_FLASH
ulong size;
#endif
static bd_t bd_data;
static gd_t gd_data;
init_fnc_t **init_fnc_ptr;
......@@ -272,10 +287,10 @@ void board_init_r(gd_t *id, ulong dest_addr)
memcpy(gd, id, sizeof(gd_t));
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
__asm__ __volatile__("" : : : "memory");
gd->bd = &bd_data;
memset (gd->bd, 0, sizeof (bd_t));
memset(gd->bd, 0, sizeof(bd_t));
show_boot_progress(0x22);
gd->baudrate = CONFIG_BAUDRATE;
......@@ -285,28 +300,31 @@ void board_init_r(gd_t *id, ulong dest_addr)
for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0)
hang ();
hang();
}
show_boot_progress(0x23);
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
#ifndef CONFIG_SYS_NO_FLASH
/* configure available FLASH banks */
size = flash_init();
display_flash_config(size);
show_boot_progress(0x24);
#endif
show_boot_progress(0x25);
/* initialize environment */
env_relocate ();
env_relocate();
show_boot_progress(0x26);
#ifdef CONFIG_CMD_NET
/* IP Address */
bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr");
bd_data.bi_ip_addr = getenv_IPaddr("ipaddr");
#endif
#if defined(CONFIG_PCI)
......@@ -319,9 +337,9 @@ void board_init_r(gd_t *id, ulong dest_addr)
show_boot_progress(0x27);
stdio_init ();
stdio_init();
jumptable_init ();
jumptable_init();
/* Initialize the console (after the relocation and devices init) */
console_init_r();
......@@ -333,7 +351,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
puts ("PCMCIA:");
puts("PCMCIA:");
pcmcia_init();
#endif
......@@ -348,7 +366,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
show_boot_progress(0x28);
#ifdef CONFIG_STATUS_LED
status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
udelay(20);
......@@ -356,9 +374,10 @@ void board_init_r(gd_t *id, ulong dest_addr)
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#if defined(CONFIG_CMD_NET)
if ((s = getenv ("bootfile")) != NULL) {
copy_filename (BootFile, s, sizeof (BootFile));
}
s = getenv("bootfile");
if (s != NULL)
copy_filename(BootFile, s, sizeof(BootFile));
#endif
WATCHDOG_RESET();
......@@ -390,10 +409,10 @@ void board_init_r(gd_t *id, ulong dest_addr)
eth_initialize(gd->bd);
#endif
#if ( defined(CONFIG_CMD_NET)) && (0)
#if (defined(CONFIG_CMD_NET)) && (0)
WATCHDOG_RESET();
# ifdef DEBUG
puts ("Reset Ethernet PHY\n");
puts("Reset Ethernet PHY\n");
# endif
reset_phy();
#endif
......@@ -410,27 +429,27 @@ void board_init_r(gd_t *id, ulong dest_addr)
#ifdef CONFIG_POST
post_run (NULL, POST_RAM | post_bootmode_get(0));
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
show_boot_progress(0x29);
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
for (;;)
main_loop();
}
/* NOTREACHED - no way out of command loop except booting */
}
void hang (void)
void hang(void)
{
puts ("### ERROR ### Please RESET the board ###\n");
for (;;);
puts("### ERROR ### Please RESET the board ###\n");
for (;;)
;
}
unsigned long do_go_exec (ulong (*entry)(int, char * const []), int argc, char * const argv[])
unsigned long do_go_exec(ulong (*entry)(int, char * const []),
int argc, char * const argv[])
{
unsigned long ret = 0;
char **argv_tmp;
......
arch/x86/lib/bootm.c
浏览文件 @ 7708d8b3
......@@ -32,9 +32,10 @@
#include <asm/zimage.h>
/*cmd_boot.c*/
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *images)
{
void *base_ptr;
void *base_ptr = NULL;
ulong os_data, os_len;
image_header_t *hdr;
......@@ -48,41 +49,43 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
if (images->legacy_hdr_valid) {
hdr = images->legacy_hdr_os;
if (image_check_type (hdr, IH_TYPE_MULTI)) {
if (image_check_type(hdr, IH_TYPE_MULTI)) {
/* if multi-part image, we need to get first subimage */
image_multi_getimg (hdr, 0, &os_data, &os_len);
image_multi_getimg(hdr, 0, &os_data, &os_len);
} else {
/* otherwise get image data */
os_data = image_get_data (hdr);
os_len = image_get_data_size (hdr);
os_data = image_get_data(hdr);
os_len = image_get_data_size(hdr);
}
#if defined(CONFIG_FIT)
} else if (images->fit_uname_os) {
ret = fit_image_get_data (images->fit_hdr_os,
ret = fit_image_get_data(images->fit_hdr_os,
images->fit_noffset_os, &data, &len);
if (ret) {
puts ("Can't get image data/size!\n");
puts("Can't get image data/size!\n");
goto error;
}
os_data = (ulong)data;
os_len = (ulong)len;
#endif
} else {
puts ("Could not find kernel image!\n");
puts("Could not find kernel image!\n");
goto error;
}
base_ptr = load_zimage ((void*)os_data, os_len,
#ifdef CONFIG_CMD_ZBOOT
base_ptr = load_zimage((void *)os_data, os_len,
images->rd_start, images->rd_end - images->rd_start, 0);
#endif
if (NULL == base_ptr) {
printf ("## Kernel loading failed ...\n");
printf("## Kernel loading failed ...\n");
goto error;
}
#ifdef DEBUG
printf ("## Transferring control to Linux (at address %08x) ...\n",
printf("## Transferring control to Linux (at address %08x) ...\n",
(u32)base_ptr);
#endif
......
arch/x86/lib/gcc.c 0 → 100644
浏览文件 @ 7708d8b3
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 or later of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
#ifdef __GNUC__
/*
* GCC's libgcc handling is quite broken. While the libgcc functions
* are always regparm(0) the code that calls them uses whatever the
* compiler call specifies. Therefore we need a wrapper around those
* functions. See gcc bug PR41055 for more information.
*/
#define WRAP_LIBGCC_CALL(type, name) \
type __normal_##name(type a, type b) __attribute__((regparm(0))); \
type __wrap_##name(type a, type b); \
type __wrap_##name(type a, type b) { return __normal_##name(a, b); }
WRAP_LIBGCC_CALL(long long, __divdi3)
WRAP_LIBGCC_CALL(unsigned long long, __udivdi3)
WRAP_LIBGCC_CALL(long long, __moddi3)
WRAP_LIBGCC_CALL(unsigned long long, __umoddi3)
#endif
arch/x86/lib/interrupts.c
浏览文件 @ 7708d8b3
......@@ -56,8 +56,8 @@ struct irq_action {
};
static struct irq_action irq_handlers[CONFIG_SYS_NUM_IRQS] = { {0} };
static int spurious_irq_cnt = 0;
static int spurious_irq = 0;
static int spurious_irq_cnt;
static int spurious_irq;
void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
{
......@@ -70,10 +70,10 @@ void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
if (irq_handlers[irq].handler != NULL)
printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
(ulong) handler,
(ulong) irq_handlers[irq].handler);
(ulong) handler,
(ulong) irq_handlers[irq].handler);
status = disable_interrupts ();
status = disable_interrupts();
irq_handlers[irq].handler = handler;
irq_handlers[irq].arg = arg;
......@@ -96,7 +96,7 @@ void irq_free_handler(int irq)
return;
}
status = disable_interrupts ();
status = disable_interrupts();
mask_irq(irq);
......@@ -141,14 +141,14 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int irq;
printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
spurious_irq_cnt, spurious_irq);
spurious_irq_cnt, spurious_irq);
printf ("Interrupt-Information:\n");
printf ("Nr Routine Arg Count\n");
printf("Interrupt-Information:\n");
printf("Nr Routine Arg Count\n");
for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) {
if (irq_handlers[irq].handler != NULL) {
printf ("%02d %08lx %08lx %d\n",
printf("%02d %08lx %08lx %d\n",
irq,
(ulong)irq_handlers[irq].handler,
(ulong)irq_handlers[irq].arg,
......
arch/x86/lib/pcat_interrupts.c
浏览文件 @ 7708d8b3
......@@ -76,7 +76,7 @@ int interrupt_init(void)
* Enable cascaded interrupts by unmasking the cascade IRQ pin of
* the master PIC
*/
unmask_irq (2);
unmask_irq(2);
enable_interrupts();
......
arch/x86/lib/pcat_timer.c
浏览文件 @ 7708d8b3
......@@ -30,7 +30,7 @@
#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */
#define TIMER2_VALUE 0x0a8e /* 440Hz */
static int timer_init_done = 0;
static int timer_init_done;
int timer_init(void)
{
......@@ -42,18 +42,18 @@ int timer_init(void)
* (to stasrt a beep: write 3 to port 0x61,
* to stop it again: write 0)
*/
outb (PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2,
PIT_BASE + PIT_COMMAND);
outb (TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0);
outb (TIMER0_VALUE >> 8, PIT_BASE + PIT_T0);
outb(PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2,
PIT_BASE + PIT_COMMAND);
outb(TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0);
outb(TIMER0_VALUE >> 8, PIT_BASE + PIT_T0);
outb (PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
PIT_BASE + PIT_COMMAND);
outb (TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
outb (TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
PIT_BASE + PIT_COMMAND);
outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
irq_install_handler (0, timer_isr, NULL);
unmask_irq (0);
irq_install_handler(0, timer_isr, NULL);
unmask_irq(0);
timer_init_done = 1;
......@@ -64,21 +64,20 @@ static u16 read_pit(void)
{
u8 low;
outb (PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND);
low = inb (PIT_BASE + PIT_T0);
outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND);
low = inb(PIT_BASE + PIT_T0);
return ((inb (PIT_BASE + PIT_T0) << 8) | low);
return (inb(PIT_BASE + PIT_T0) << 8) | low;
}
/* this is not very exact */
void __udelay (unsigned long usec)
void __udelay(unsigned long usec)
{
int counter;
int wraps;
if (timer_init_done)
{
counter = read_pit ();
if (timer_init_done) {
counter = read_pit();
wraps = usec / 1000;
usec = usec % 1000;
......@@ -92,7 +91,7 @@ void __udelay (unsigned long usec)
}
while (1) {
int new_count = read_pit ();
int new_count = read_pit();
if (((new_count < usec) && !wraps) || wraps < 0)
break;
......
arch/x86/lib/pci.c
浏览文件 @ 7708d8b3
......@@ -42,11 +42,13 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
u16 device;
u32 class_code;
u32 pci_data;
hose = pci_bus_to_hose(PCI_BUS(dev));
#if 0
printf("pci_shadow_rom() asked to shadow device %x to %x\n",
debug("pci_shadow_rom() asked to shadow device %x to %x\n",
dev, (u32)dest);
#endif
pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
pci_read_config_word(dev, PCI_DEVICE_ID, &device);
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_code);
......@@ -67,7 +69,7 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
return -1;
}
size = (~(addr_reg&PCI_ROM_ADDRESS_MASK))+1;
size = (~(addr_reg&PCI_ROM_ADDRESS_MASK)) + 1;
debug("ROM is %d bytes\n", size);
......@@ -80,27 +82,25 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
|PCI_ROM_ADDRESS_ENABLE);
for (i=rom_addr;i<rom_addr+size; i+=512) {
for (i = rom_addr; i < rom_addr + size; i += 512) {
if (readw(i) == 0xaa55) {
u32 pci_data;
#ifdef PCI_ROM_SCAN_VERBOSE
printf("ROM signature found\n");
#endif
pci_data = readw(0x18+i);
pci_data = readw(0x18 + i);
pci_data += i;
if (0==memcmp((void*)pci_data, "PCIR", 4)) {
if (0 == memcmp((void *)pci_data, "PCIR", 4)) {
#ifdef PCI_ROM_SCAN_VERBOSE
printf("Fount PCI rom image at offset %d\n", i-rom_addr);
printf("Fount PCI rom image at offset %d\n",
i - rom_addr);
printf("Vendor %04x device %04x class %06x\n",
readw(pci_data+4), readw(pci_data+6),
readl(pci_data+0x0d)&0xffffff);
readw(pci_data + 4), readw(pci_data + 6),
readl(pci_data + 0x0d) & 0xffffff);
printf("%s\n",
(readw(pci_data+0x15) &0x80)?
"Last image":"More images follow");
switch (readb(pci_data+0x14)) {
(readw(pci_data + 0x15) & 0x80) ?
"Last image" : "More images follow");
switch (readb(pci_data + 0x14)) {
case 0:
printf("X86 code\n");
break;
......@@ -111,35 +111,38 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
printf("PARISC code\n");
break;
}
printf("Image size %d\n", readw(pci_data+0x10) * 512);
printf("Image size %d\n",
readw(pci_data + 0x10) * 512);
#endif
/* FixMe: I think we should compare the class code
* bytes as well but I have no reference on the
* exact order of these bytes in the PCI ROM header */
if (readw(pci_data+4) == vendor &&
readw(pci_data+6) == device &&
/* (readl(pci_data+0x0d)&0xffffff) == class_code && */
readb(pci_data+0x14) == 0 /* x86 code image */ ) {
/*
* FixMe: I think we should compare the class
* code bytes as well but I have no reference
* on the exact order of these bytes in the PCI
* ROM header
*/
if (readw(pci_data + 4) == vendor &&
readw(pci_data + 6) == device &&
readb(pci_data + 0x14) == 0) {
#ifdef PCI_ROM_SCAN_VERBOSE
printf("Suitable ROM image found, copying\n");
printf("Suitable ROM image found\n");
#endif
memmove(dest, (void*)rom_addr, readw(pci_data+0x10) * 512);
memmove(dest, (void *)rom_addr,
readw(pci_data + 0x10) * 512);
res = 0;
break;
}
if (readw(pci_data+0x15) &0x80) {
if (readw(pci_data + 0x15) & 0x80)
break;
}
}
}
}
#ifdef PCI_ROM_SCAN_VERBOSE
if (res) {
if (res)
printf("No suitable image found\n");
}
#endif
/* disable PAR register and PCI device ROM address devocer */
pci_remove_rom_window(hose, rom_addr);
......@@ -148,3 +151,38 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
return res;
}
#ifdef PCI_BIOS_DEBUG
void print_bios_bios_stat(void)
{
printf("16 bit functions:\n");
printf("pci_bios_present: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_present));
printf("pci_bios_find_device: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_find_device));
printf("pci_bios_find_class: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_find_class));
printf("pci_bios_generate_special_cycle: %d\n",
RELOC_16_LONG(0xf000,
num_pci_bios_generate_special_cycle));
printf("pci_bios_read_cfg_byte: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_byte));
printf("pci_bios_read_cfg_word: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_word));
printf("pci_bios_read_cfg_dword: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_dword));
printf("pci_bios_write_cfg_byte: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_byte));
printf("pci_bios_write_cfg_word: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_word));
printf("pci_bios_write_cfg_dword: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_dword));
printf("pci_bios_get_irq_routing: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_get_irq_routing));
printf("pci_bios_set_irq: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_set_irq));
printf("pci_bios_unknown_function: %d\n",
RELOC_16_LONG(0xf000, num_pci_bios_unknown_function));
}
#endif
arch/x86/lib/pci_type1.c
浏览文件 @ 7708d8b3
......@@ -29,7 +29,7 @@
#include <asm/io.h>
#include <pci.h>
#define cfg_read(val, addr, op) *val = op((int)(addr))
#define cfg_read(val, addr, op) (*val = op((int)(addr)))
#define cfg_write(val, addr, op) op((val), (int)(addr))
#define TYPE1_PCI_OP(rw, size, type, op, mask) \
......@@ -42,7 +42,6 @@ type1_##rw##_config_##size(struct pci_controller *hose, \
return 0; \
}
TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
TYPE1_PCI_OP(read, word, u16 *, inw, 2)
TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
......@@ -51,7 +50,11 @@ TYPE1_PCI_OP(write, byte, u8, outb, 3)
TYPE1_PCI_OP(write, word, u16, outw, 2)
TYPE1_PCI_OP(write, dword, u32, outl, 0)
void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
/* bus mapping constants (used for PCI core initialization) */
#define PCI_REG_ADDR 0x00000cf8
#define PCI_REG_DATA 0x00000cfc
void pci_setup_type1(struct pci_controller *hose)
{
pci_set_ops(hose,
type1_read_config_byte,
......@@ -61,6 +64,6 @@ void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
type1_write_config_word,
type1_write_config_dword);
hose->cfg_addr = (unsigned int *) cfg_addr;
hose->cfg_data = (unsigned char *) cfg_data;
hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
hose->cfg_data = (unsigned char *)PCI_REG_DATA;
}
arch/x86/lib/realmode.c
浏览文件 @ 7708d8b3
......@@ -26,15 +26,12 @@
#include <asm/ptrace.h>
#include <asm/realmode.h>
#define REALMODE_MAILBOX ((char*)0xe00)
extern ulong __realmode_start;
extern ulong __realmode_size;
extern char realmode_enter;
#define REALMODE_MAILBOX ((char *)0xe00)
int realmode_setup(void)
{
ulong realmode_start = (ulong)&__realmode_start + gd->reloc_off;
/* The realmode section is not relocated and still in the ROM. */
ulong realmode_start = (ulong)&__realmode_start;
ulong realmode_size = (ulong)&__realmode_size;
/* copy the realmode switch code */
......@@ -63,15 +60,14 @@ int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out)
in->eip = off;
in->xcs = seg;
if (3>(in->esp & 0xffff)) {
if ((in->esp & 0xffff) < 4)
printf("Warning: entering realmode with sp < 4 will fail\n");
}
memcpy(REALMODE_MAILBOX, in, sizeof(struct pt_regs));
asm("wbinvd\n");
__asm__ volatile (
"lcall $0x20,%0\n" : : "i" (&realmode_enter) );
"lcall $0x20,%0\n" : : "i" (&realmode_enter));
asm("wbinvd\n");
memcpy(out, REALMODE_MAILBOX, sizeof(struct pt_regs));
......@@ -79,9 +75,10 @@ int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out)
return out->eax;
}
/* This code is supposed to access a realmode interrupt
* it does currently not work for me */
/*
* This code is supposed to access a realmode interrupt
* it does currently not work for me
*/
int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out)
{
/* place two instructions at 0x700 */
......@@ -92,5 +89,5 @@ int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out)
enter_realmode(0x00, 0x700, in, out);
return out->eflags&1;
return out->eflags & 0x00000001;
}
arch/x86/lib/string.c 0 → 100644
浏览文件 @ 7708d8b3
/*
* Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
* This file is part of the GNU C Library.
* Copyright (c) 2011 The Chromium OS Authors.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* From glibc-2.14, sysdeps/i386/memset.c */
#include <compiler.h>
#include <asm/string.h>
#include <linux/types.h>
typedef uint32_t op_t;
void *memset(void *dstpp, int c, size_t len)
{
int d0;
unsigned long int dstp = (unsigned long int) dstpp;
/* This explicit register allocation improves code very much indeed. */
register op_t x asm("ax");
x = (unsigned char) c;
/* Clear the direction flag, so filling will move forward. */
asm volatile("cld");
/* This threshold value is optimal. */
if (len >= 12) {
/* Fill X with four copies of the char we want to fill with. */
x |= (x << 8);
x |= (x << 16);
/* Adjust LEN for the bytes handled in the first loop. */
len -= (-dstp) % sizeof(op_t);
/*
* There are at least some bytes to set. No need to test for
* LEN == 0 in this alignment loop.
*/
/* Fill bytes until DSTP is aligned on a longword boundary. */
asm volatile(
"rep\n"
"stosb" /* %0, %2, %3 */ :
"=D" (dstp), "=c" (d0) :
"0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) :
"memory");
/* Fill longwords. */
asm volatile(
"rep\n"
"stosl" /* %0, %2, %3 */ :
"=D" (dstp), "=c" (d0) :
"0" (dstp), "1" (len / sizeof(op_t)), "a" (x) :
"memory");
len %= sizeof(op_t);
}
/* Write the last few bytes. */
asm volatile(
"rep\n"
"stosb" /* %0, %2, %3 */ :
"=D" (dstp), "=c" (d0) :
"0" (dstp), "1" (len), "a" (x) :
"memory");
return dstpp;
}
arch/x86/lib/timer.c
浏览文件 @ 7708d8b3
......@@ -35,15 +35,15 @@ struct timer_isr_function {
timer_fnc_t *isr_func;
};
static struct timer_isr_function *first_timer_isr = NULL;
static volatile unsigned long system_ticks = 0;
static struct timer_isr_function *first_timer_isr;
static unsigned long system_ticks;
/*
* register_timer_isr() allows multiple architecture and board specific
* functions to be called every millisecond. Keep the execution time of
* each function as low as possible
*/
int register_timer_isr (timer_fnc_t *isr_func)
int register_timer_isr(timer_fnc_t *isr_func)
{
struct timer_isr_function *new_func;
struct timer_isr_function *temp;
......@@ -61,7 +61,7 @@ int register_timer_isr (timer_fnc_t *isr_func)
* Don't allow timer interrupts while the
* linked list is being modified
*/
flag = disable_interrupts ();
flag = disable_interrupts();
if (first_timer_isr == NULL) {
first_timer_isr = new_func;
......@@ -73,7 +73,7 @@ int register_timer_isr (timer_fnc_t *isr_func)
}
if (flag)
enable_interrupts ();
enable_interrupts();
return 0;
}
......@@ -89,12 +89,12 @@ void timer_isr(void *unused)
/* Execute each registered function */
while (temp != NULL) {
temp->isr_func ();
temp->isr_func();
temp = temp->next;
}
}
ulong get_timer (ulong base)
ulong get_timer(ulong base)
{
return (system_ticks - base);
return system_ticks - base;
}
arch/x86/lib/video.c
浏览文件 @ 7708d8b3
......@@ -123,7 +123,7 @@ static void __video_putc(const char c, int *x, int *y)
static void video_putc(const char c)
{
int x,y,pos;
int x, y, pos;
x = orig_x;
y = orig_y;
......@@ -142,7 +142,7 @@ static void video_putc(const char c)
static void video_puts(const char *s)
{
int x,y,pos;
int x, y, pos;
char c;
x = orig_x;
......@@ -187,7 +187,7 @@ int video_init(void)
printf("pos %x %d %d\n", pos, orig_x, orig_y);
#endif
if (orig_y > lines)
orig_x = orig_y =0;
orig_x = orig_y = 0;
memset(&vga_dev, 0, sizeof(vga_dev));
strcpy(vga_dev.name, "vga");
......
arch/x86/lib/video_bios.c
浏览文件 @ 7708d8b3
......@@ -28,86 +28,55 @@
#include <asm/realmode.h>
#include <asm/io.h>
#include <asm/pci.h>
#include "bios.h"
#undef PCI_BIOS_DEBUG
#undef VGA_BIOS_DEBUG
#ifdef VGA_BIOS_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#define PRINTF(fmt, args...) printf(fmt, ##args)
#else
#define PRINTF(fmt,args...)
#define PRINTF(fmt, args...)
#endif
#ifdef CONFIG_PCI
#define PCI_CLASS_VIDEO 3
#define PCI_CLASS_VIDEO_STD 0
#define PCI_CLASS_VIDEO_PROG_IF_VGA 0
#ifdef PCI_BIOS_DEBUG
#define RELOC_16(seg, off) *(u32*)(seg << 4 | (u32)&off)
extern u32 num_pci_bios_present;
extern u32 num_pci_bios_find_device;
extern u32 num_pci_bios_find_class;
extern u32 num_pci_bios_generate_special_cycle;
extern u32 num_pci_bios_read_cfg_byte;
extern u32 num_pci_bios_read_cfg_word;
extern u32 num_pci_bios_read_cfg_dword;
extern u32 num_pci_bios_write_cfg_byte;
extern u32 num_pci_bios_write_cfg_word;
extern u32 num_pci_bios_write_cfg_dword;
extern u32 num_pci_bios_get_irq_routing;
extern u32 num_pci_bios_set_irq;
extern u32 num_pci_bios_unknown_function;
void print_bios_bios_stat(void)
{
printf("16 bit functions:\n");
printf("pci_bios_present: %d\n", RELOC_16(0xf000, num_pci_bios_present));
printf("pci_bios_find_device: %d\n", RELOC_16(0xf000, num_pci_bios_find_device));
printf("pci_bios_find_class: %d\n", RELOC_16(0xf000, num_pci_bios_find_class));
printf("pci_bios_generate_special_cycle: %d\n", RELOC_16(0xf000, num_pci_bios_generate_special_cycle));
printf("pci_bios_read_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_byte));
printf("pci_bios_read_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_word));
printf("pci_bios_read_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_dword));
printf("pci_bios_write_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_byte));
printf("pci_bios_write_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_word));
printf("pci_bios_write_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_dword));
printf("pci_bios_get_irq_routing: %d\n", RELOC_16(0xf000, num_pci_bios_get_irq_routing));
printf("pci_bios_set_irq: %d\n", RELOC_16(0xf000, num_pci_bios_set_irq));
printf("pci_bios_unknown_function: %d\n", RELOC_16(0xf000, num_pci_bios_unknown_function));
}
#endif
#ifdef CONFIG_VIDEO
#define PCI_CLASS_VIDEO 3
#define PCI_CLASS_VIDEO_STD 0
#define PCI_CLASS_VIDEO_PROG_IF_VGA 0
static struct pci_device_id supported[] = {
DEFINE_PCI_DEVICE_TABLE(supported) = {
{PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID},
{}
};
static u32 probe_pci_video(void)
{
pci_dev_t devbusfn;
struct pci_controller *hose;
pci_dev_t devbusfn = pci_find_devices(supported, 0);
if ((devbusfn = pci_find_devices(supported, 0) != -1)) {
if ((devbusfn != -1)) {
u32 old;
u32 addr;
/* PCI video device detected */
printf("Found PCI VGA device at %02x.%02x.%x\n",
PCI_BUS(devbusfn), PCI_DEV(devbusfn), PCI_FUNC(devbusfn));
PCI_BUS(devbusfn),
PCI_DEV(devbusfn),
PCI_FUNC(devbusfn));
/* Enable I/O decoding as well, PCI viudeo boards
* support I/O accesses, but they provide no
* bar register for this since the ports are fixed.
*/
pci_write_config_word(devbusfn, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
pci_write_config_word(devbusfn,
PCI_COMMAND,
PCI_COMMAND_MEMORY |
PCI_COMMAND_IO |
PCI_COMMAND_MASTER);
/* Test the ROM decoder, do the device support a rom? */
pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old);
pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS,
(u32)PCI_ROM_ADDRESS_MASK);
pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr);
pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old);
......@@ -117,13 +86,14 @@ static u32 probe_pci_video(void)
}
/* device have a rom */
if (pci_shadow_rom(devbusfn, (void*)0xc0000)) {
if (pci_shadow_rom(devbusfn, (void *)0xc0000)) {
printf("Shadowing of PCI VGA BIOS failed\n");
return 0;
}
/* Now enable lagacy VGA port access */
if (pci_enable_legacy_video_ports(pci_bus_to_hose(PCI_BUS(devbusfn)))) {
hose = pci_bus_to_hose(PCI_BUS(devbusfn));
if (pci_enable_legacy_video_ports(hose)) {
printf("PCI VGA enable failed\n");
return 0;
}
......@@ -131,7 +101,7 @@ static u32 probe_pci_video(void)
/* return the pci device info, that we'll need later */
return PCI_BUS(devbusfn) << 8 |
PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn)&7);
PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn) & 7);
}
return 0;
......@@ -142,13 +112,17 @@ static int probe_isa_video(void)
u32 ptr;
char *buf;
if (0 == (ptr = isa_map_rom(0xc0000, 0x8000))) {
ptr = isa_map_rom(0xc0000, 0x8000);
if (!ptr)
return -1;
}
if (NULL == (buf=malloc(0x8000))) {
buf = malloc(0x8000);
if (!buf) {
isa_unmap_rom(ptr);
return -1;
}
if (readw(ptr) != 0xaa55) {
free(buf);
isa_unmap_rom(ptr);
......@@ -156,9 +130,9 @@ static int probe_isa_video(void)
}
/* shadow the rom */
memcpy(buf, (void*)ptr, 0x8000);
memcpy(buf, (void *)ptr, 0x8000);
isa_unmap_rom(ptr);
memcpy((void*)0xc0000, buf, 0x8000);
memcpy((void *)0xc0000, buf, 0x8000);
free(buf);
......@@ -168,35 +142,35 @@ static int probe_isa_video(void)
int video_bios_init(void)
{
struct pt_regs regs;
int size;
int i;
u8 sum;
/* clear the video bios area in case we warmbooted */
memset((void*)0xc0000, 0, 0x8000);
memset((void *)0xc0000, 0, 0x8000);
memset(&regs, 0, sizeof(struct pt_regs));
if (probe_isa_video()) {
if (probe_isa_video())
/* No ISA board found, try the PCI bus */
regs.eax = probe_pci_video();
}
/* Did we succeed in mapping any video bios */
if (readw(0xc0000) == 0xaa55) {
int size;
int i;
u8 sum;
PRINTF("Found video bios signature\n");
size = 512*readb(0xc0002);
size = readb(0xc0002) * 512;
PRINTF("size %d\n", size);
sum=0;
for (i=0;i<size;i++) {
sum = 0;
for (i = 0; i < size; i++)
sum += readb(0xc0000 + i);
}
PRINTF("Checksum is %sOK\n",sum?"NOT ":"");
if (sum) {
PRINTF("Checksum is %sOK\n", sum ? "NOT " : "");
if (sum)
return 1;
}
/* some video bioses (ATI Mach64) seem to think that
/*
* Some video bioses (ATI Mach64) seem to think that
* the original int 10 handler is always at
* 0xf000:0xf065 , place an iret instruction there
*/
......@@ -205,18 +179,18 @@ int video_bios_init(void)
regs.esp = 0x8000;
regs.xss = 0x2000;
enter_realmode(0xc000, 3, &regs, &regs);
PRINTF("INT 0x10 vector after: %04x:%04x\n",
readw(0x42), readw(0x40));
PRINTF("BIOS returned %scarry\n", regs.eflags & 1?"":"NOT ");
PRINTF("BIOS returned %scarry\n",
regs.eflags & 0x00000001 ? "" : "NOT ");
#ifdef PCI_BIOS_DEBUG
print_bios_bios_stat();
#endif
return (regs.eflags & 1);
return regs.eflags & 0x00000001;
}
return 1;
}
#endif
#endif
arch/x86/lib/zimage.c
浏览文件 @ 7708d8b3
......@@ -45,11 +45,11 @@
* 0x8000-0x8FFF Stack and heap
* 0x9000-0x90FF Kernel command line
*/
#define DEFAULT_SETUP_BASE 0x90000
#define COMMAND_LINE_OFFSET 0x9000
#define HEAP_END_OFFSET 0x8e00
#define DEFAULT_SETUP_BASE 0x90000
#define COMMAND_LINE_OFFSET 0x9000
#define HEAP_END_OFFSET 0x8e00
#define COMMAND_LINE_SIZE 2048
#define COMMAND_LINE_SIZE 2048
static void build_command_line(char *command_line, int auto_boot)
{
......@@ -60,23 +60,20 @@ static void build_command_line(char *command_line, int auto_boot)
env_command_line = getenv("bootargs");
/* set console= argument if we use a serial console */
if (NULL == strstr(env_command_line, "console=")) {
if (0==strcmp(getenv("stdout"), "serial")) {
if (!strstr(env_command_line, "console=")) {
if (!strcmp(getenv("stdout"), "serial")) {
/* We seem to use serial console */
sprintf(command_line, "console=ttyS0,%s ",
getenv("baudrate"));
getenv("baudrate"));
}
}
if (auto_boot) {
if (auto_boot)
strcat(command_line, "auto ");
}
if (NULL != env_command_line) {
if (env_command_line)
strcat(command_line, env_command_line);
}
printf("Kernel command line: \"%s\"\n", command_line);
}
......@@ -90,14 +87,16 @@ void *load_zimage(char *image, unsigned long kernel_size,
int bootproto;
int big_image;
void *load_address;
struct setup_header *hdr;
struct setup_header *hdr = (struct setup_header *)(image + SETUP_SECTS_OFF);
hdr = (struct setup_header *)(image + SETUP_SECTS_OFF);
setup_base = (void*)DEFAULT_SETUP_BASE; /* base address for real-mode segment */
/* base address for real-mode segment */
setup_base = (void *)DEFAULT_SETUP_BASE;
if (KERNEL_MAGIC != hdr->boot_flag) {
printf("Error: Invalid Boot Flag (found 0x%04x, expected 0x%04x)\n",
hdr->boot_flag, KERNEL_MAGIC);
hdr->boot_flag, KERNEL_MAGIC);
return 0;
} else {
printf("Valid Boot Flag\n");
......@@ -124,43 +123,50 @@ void *load_zimage(char *image, unsigned long kernel_size,
printf("Setup Size = 0x%8.8lx\n", (ulong)setup_size);
if (setup_size > SETUP_MAX_SIZE) {
if (setup_size > SETUP_MAX_SIZE)
printf("Error: Setup is too large (%d bytes)\n", setup_size);
}
/* Determine image type */
big_image = (bootproto >= 0x0200) && (hdr->loadflags & BIG_KERNEL_FLAG);
big_image = (bootproto >= 0x0200) &&
(hdr->loadflags & BIG_KERNEL_FLAG);
/* Determine load address */
load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR : ZIMAGE_LOAD_ADDR);
load_address = (void *)(big_image ?
BZIMAGE_LOAD_ADDR :
ZIMAGE_LOAD_ADDR);
/* load setup */
printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n", (ulong)setup_base, setup_size);
printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n",
(ulong)setup_base, setup_size);
memmove(setup_base, image, setup_size);
printf("Using boot protocol version %x.%02x\n",
(bootproto & 0xff00) >> 8, bootproto & 0xff);
if (bootproto == 0x0100) {
*(u16 *)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
*(u16 *)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET;
*(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
*(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET;
/* A very old kernel MUST have its real-mode code
* loaded at 0x90000 */
/*
* A very old kernel MUST have its real-mode code
* loaded at 0x90000
*/
if ((u32)setup_base != 0x90000) {
/* Copy the real-mode kernel */
memmove((void*)0x90000, setup_base, setup_size);
memmove((void *)0x90000, setup_base, setup_size);
/* Copy the command line */
memmove((void*)0x99000, setup_base+COMMAND_LINE_OFFSET,
COMMAND_LINE_SIZE);
memmove((void *)0x99000,
setup_base + COMMAND_LINE_OFFSET,
COMMAND_LINE_SIZE);
setup_base = (void*)0x90000; /* Relocated */
/* Relocated */
setup_base = (void *)0x90000;
}
/* It is recommended to clear memory up to the 32K mark */
memset((void*)0x90000 + setup_size, 0, SETUP_MAX_SIZE-setup_size);
memset((void *)0x90000 + setup_size, 0,
SETUP_MAX_SIZE-setup_size);
}
/* We are now setting up the real-mode version of the header */
......@@ -170,8 +176,9 @@ void *load_zimage(char *image, unsigned long kernel_size,
hdr->type_of_loader = 8;
if (hdr->setup_sects >= 15)
printf("Linux kernel version %s\n", (char *)
(setup_base + (hdr->kernel_version + 0x200)));
printf("Linux kernel version %s\n",
(char *)(setup_base +
(hdr->kernel_version + 0x200)));
else
printf("Setup Sectors < 15 - Cannot print kernel version.\n");
......@@ -193,8 +200,8 @@ void *load_zimage(char *image, unsigned long kernel_size,
hdr->cmd_line_ptr = (u32)setup_base + COMMAND_LINE_OFFSET;
} else if (bootproto >= 0x0200) {
*(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
*(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET;
*(u16 *)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC;
*(u16 *)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET;
hdr->setup_move_size = 0x9100;
}
......@@ -221,8 +228,8 @@ void *load_zimage(char *image, unsigned long kernel_size,
/* build command line at COMMAND_LINE_OFFSET */
build_command_line(setup_base + COMMAND_LINE_OFFSET, auto_boot);
printf("Loading %czImage at address 0x%08x (%ld bytes)\n", big_image ? 'b' : ' ',
(u32)load_address, kernel_size);
printf("Loading %czImage at address 0x%08x (%ld bytes)\n",
big_image ? 'b' : ' ', (u32)load_address, kernel_size);
memmove(load_address, image + setup_size, kernel_size);
......@@ -241,10 +248,11 @@ void boot_zimage(void *setup_base)
regs.xss = regs.xds;
regs.esp = 0x9000;
regs.eflags = 0;
enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, &regs, &regs);
enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, &regs,
&regs);
}
int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
void *base_ptr;
void *bzImage_addr = NULL;
......@@ -270,12 +278,12 @@ int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
bzImage_size = simple_strtoul(argv[2], NULL, 16);
/* Lets look for*/
base_ptr = load_zimage (bzImage_addr, bzImage_size, 0, 0, 0);
base_ptr = load_zimage(bzImage_addr, bzImage_size, 0, 0, 0);
if (NULL == base_ptr) {
printf ("## Kernel loading failed ...\n");
if (!base_ptr) {
printf("## Kernel loading failed ...\n");
} else {
printf ("## Transferring control to Linux (at address %08x) ...\n",
printf("## Transferring control to Linux (at address %08x) ...\n",
(u32)base_ptr);
/* we assume that the kernel is in place */
......
board/Marvell/db64360/db64360.c
浏览文件 @ 7708d8b3
......@@ -34,6 +34,7 @@
#include "../include/mv_gen_reg.h"
#include <net.h>
#include <netdev.h>
#include <linux/compiler.h>
#include "eth.h"
#include "mpsc.h"
......@@ -410,7 +411,7 @@ int checkboard (void)
void debug_led (int led, int mode)
{
volatile int *addr = 0;
int dummy;
__maybe_unused int dummy;
if (mode == 1) {
switch (led) {
......
board/Marvell/db64360/mv_eth.c
浏览文件 @ 7708d8b3
......@@ -421,7 +421,7 @@ static int mv64360_eth_real_open (struct eth_device *dev)
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
unsigned int port_num;
u32 port_status, phy_reg_data;
u32 phy_reg_data;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
/* ronen - when we update the MAC env params we only update dev->enetaddr
......@@ -519,7 +519,7 @@ static int mv64360_eth_real_open (struct eth_device *dev)
*/
MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
/* Check Link status on phy */
eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
......@@ -637,15 +637,6 @@ static int mv64360_eth_free_rx_rings (struct eth_device *dev)
int mv64360_eth_stop (struct eth_device *dev)
{
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
/* Disable all gigE address decoder */
MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
......@@ -715,7 +706,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
{
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
unsigned int port_num;
PKT_INFO pkt_info;
ETH_FUNC_RET_STATUS status;
struct net_device_stats *stats;
......@@ -724,7 +714,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
stats = port_private->stats;
......@@ -800,15 +789,12 @@ int mv64360_eth_receive (struct eth_device *dev)
{
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
unsigned int port_num;
PKT_INFO pkt_info;
struct net_device_stats *stats;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
stats = port_private->stats;
while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
......@@ -899,12 +885,10 @@ static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
{
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
mv64360_eth_update_stat (dev);
......@@ -926,13 +910,10 @@ static void mv64360_eth_update_stat (struct eth_device *dev)
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
struct net_device_stats *stats;
unsigned int port_num;
volatile unsigned int dummy;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
stats = port_private->stats;
/* These are false updates */
......@@ -955,12 +936,12 @@ static void mv64360_eth_update_stat (struct eth_device *dev)
* But the unsigned long in PowerPC and MIPS are 32bit. So the next read
* is just a dummy read for proper work of the GigE port
*/
dummy = eth_read_mib_counter (ethernet_private->port_num,
eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
stats->tx_bytes += (unsigned long)
eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_SENT_LOW);
dummy = eth_read_mib_counter (ethernet_private->port_num,
eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_SENT_HIGH);
stats->rx_errors += (unsigned long)
eth_read_mib_counter (ethernet_private->port_num,
......@@ -1008,12 +989,10 @@ static void mv64360_eth_print_stat (struct eth_device *dev)
ETH_PORT_INFO *ethernet_private;
struct mv64360_eth_priv *port_private;
struct net_device_stats *stats;
unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64360_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
stats = port_private->stats;
/* These are false updates */
......@@ -2065,13 +2044,11 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
static void eth_clear_mib_counters (ETH_PORT eth_port_num)
{
int i;
unsigned int dummy;
/* Perform dummy reads from MIB counters */
for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
i += 4)
dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
(eth_port_num) + i));
MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
return;
}
......
board/Marvell/db64360/sdram_init.c
浏览文件 @ 7708d8b3
此差异已折叠。
board/Marvell/db64460/db64460.c
浏览文件 @ 7708d8b3
......@@ -34,6 +34,7 @@
#include "../include/mv_gen_reg.h"
#include <net.h>
#include <netdev.h>
#include <linux/compiler.h>
#include "eth.h"
#include "mpsc.h"
......@@ -410,7 +411,7 @@ int checkboard (void)
void debug_led (int led, int mode)
{
volatile int *addr = 0;
int dummy;
__maybe_unused int dummy;
if (mode == 1) {
switch (led) {
......
board/Marvell/db64460/mv_eth.c
浏览文件 @ 7708d8b3
......@@ -420,7 +420,7 @@ static int mv64460_eth_real_open (struct eth_device *dev)
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
unsigned int port_num;
u32 port_status, phy_reg_data;
u32 phy_reg_data;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
/* ronen - when we update the MAC env params we only update dev->enetaddr
......@@ -518,7 +518,7 @@ static int mv64460_eth_real_open (struct eth_device *dev)
*/
MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
/* Check Link status on phy */
eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
......@@ -636,15 +636,6 @@ static int mv64460_eth_free_rx_rings (struct eth_device *dev)
int mv64460_eth_stop (struct eth_device *dev)
{
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
/* Disable all gigE address decoder */
MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
......@@ -714,7 +705,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
{
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
unsigned int port_num;
PKT_INFO pkt_info;
ETH_FUNC_RET_STATUS status;
struct net_device_stats *stats;
......@@ -723,7 +713,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
stats = port_private->stats;
......@@ -799,15 +788,12 @@ int mv64460_eth_receive (struct eth_device *dev)
{
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
unsigned int port_num;
PKT_INFO pkt_info;
struct net_device_stats *stats;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
stats = port_private->stats;
while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
......@@ -898,12 +884,10 @@ static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
{
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
mv64460_eth_update_stat (dev);
......@@ -925,13 +909,10 @@ static void mv64460_eth_update_stat (struct eth_device *dev)
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
struct net_device_stats *stats;
unsigned int port_num;
volatile unsigned int dummy;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
stats = port_private->stats;
/* These are false updates */
......@@ -954,12 +935,12 @@ static void mv64460_eth_update_stat (struct eth_device *dev)
* But the unsigned long in PowerPC and MIPS are 32bit. So the next read
* is just a dummy read for proper work of the GigE port
*/
dummy = eth_read_mib_counter (ethernet_private->port_num,
eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
stats->tx_bytes += (unsigned long)
eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_SENT_LOW);
dummy = eth_read_mib_counter (ethernet_private->port_num,
eth_read_mib_counter (ethernet_private->port_num,
ETH_MIB_GOOD_OCTETS_SENT_HIGH);
stats->rx_errors += (unsigned long)
eth_read_mib_counter (ethernet_private->port_num,
......@@ -1007,12 +988,10 @@ static void mv64460_eth_print_stat (struct eth_device *dev)
ETH_PORT_INFO *ethernet_private;
struct mv64460_eth_priv *port_private;
struct net_device_stats *stats;
unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv;
port_private =
(struct mv64460_eth_priv *) ethernet_private->port_private;
port_num = port_private->port_num;
stats = port_private->stats;
/* These are false updates */
......@@ -2064,13 +2043,11 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
static void eth_clear_mib_counters (ETH_PORT eth_port_num)
{
int i;
unsigned int dummy;
/* Perform dummy reads from MIB counters */
for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
i += 4)
dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
(eth_port_num) + i));
MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
return;
}
......
board/Marvell/db64460/sdram_init.c
浏览文件 @ 7708d8b3
此差异已折叠。
board/amirix/ap1000/flash.c
浏览文件 @ 7708d8b3
......@@ -774,12 +774,9 @@ static ulong flash_get_size (ulong base, int banknum)
static int flash_write_cfiword (flash_info_t * info, ulong dest,
cfiword_t cword)
{
cfiptr_t ctladdr;
cfiptr_t cptr;
int flag;
ctladdr.cp = flash_make_addr (info, 0, 0);
cptr.cp = (uchar *) dest;
/* Check if Flash is (sufficiently) erased */
......
board/cray/L1/flash.c
浏览文件 @ 7708d8b3
......@@ -273,7 +273,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
int flag, prot, sect;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
......@@ -303,16 +303,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
printf("Erasing sector %p\n", addr2);
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
printf("Erasing sector %p\n", addr2);
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
......@@ -320,15 +318,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
}
}
......
board/eNET/eNET.c
浏览文件 @ 7708d8b3
......@@ -223,7 +223,7 @@ void setup_pcat_compatibility()
* active low polarity on PIC interrupt pins,
* active high polarity on all other irq pins
*/
writew(0x0000,&sc520_mmcr->intpinpol);
writew(0x0000, &sc520_mmcr->intpinpol);
/*
* PIT 0 -> IRQ0
......@@ -252,7 +252,7 @@ void setup_pcat_compatibility()
void enet_timer_isr(void)
{
static long enet_ticks = 0;
static long enet_ticks;
enet_ticks++;
......@@ -281,9 +281,9 @@ void hw_watchdog_reset(void)
void enet_toggle_run_led(void)
{
unsigned char leds_state= inb(LED_LATCH_ADDRESS);
unsigned char leds_state = inb(LED_LATCH_ADDRESS);
if (leds_state & LED_RUN_BITMASK)
outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
else
outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
}
board/eNET/eNET_pci.c
浏览文件 @ 7708d8b3
......@@ -38,7 +38,7 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
CONFIG_SYS_THIRD_PCI_IRQ,
CONFIG_SYS_FORTH_PCI_IRQ
};
static int next_irq_index=0;
static int next_irq_index;
uchar tmp_pin;
int pin;
......@@ -47,9 +47,8 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
pin = tmp_pin;
pin -= 1; /* PCI config space use 1-based numbering */
if (pin == -1) {
if (pin == -1)
return; /* device use no irq */
}
/* map device number + pin to a pin on the sc520 */
switch (PCI_DEV(dev)) {
......@@ -69,19 +68,19 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
if (sc520_pci_ints[pin] == -1) {
/* re-route one interrupt for us */
if (next_irq_index > 3) {
if (next_irq_index > 3)
return;
}
if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
return;
}
next_irq_index++;
}
if (-1 != sc520_pci_ints[pin]) {
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
if (-1 != sc520_pci_ints[pin])
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
sc520_pci_ints[pin]);
}
printf("fixup_irq: device %d pin %c irq %d\n",
PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
}
......
board/eNET/eNET_start16.S
浏览文件 @ 7708d8b3
......@@ -30,6 +30,7 @@
#include "config.h"
#include "hardware.h"
#include <asm/arch/sc520.h>
#include <generated/asm-offsets.h>
.text
.section .start16, "ax"
......@@ -46,12 +47,12 @@ board_init16:
movw %ax, %ds
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi
movl $GENERATED_SC520_PAR14, %edi
movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi
movl $GENERATED_SC520_PAR15, %edi
movl $CONFIG_SYS_SC520_LLIO_PAR, %eax
movl %eax, (%di)
......
board/emk/top860/top860.c
浏览文件 @ 7708d8b3
......@@ -34,6 +34,7 @@
#include <common.h>
#include <commproc.h>
#include <mpc8xx.h>
#include <asm/io.h>
/*****************************************************************************
* UPM table for 60ns EDO RAM at 25 MHz bus/external clock
......@@ -87,7 +88,7 @@ phys_size_t initdram (int board_type)
*/
if ((ulong) initdram & 0xff000000) {
volatile uint *addr1, *addr2;
uint i, j;
uint i;
upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,
sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
......@@ -100,8 +101,8 @@ phys_size_t initdram (int board_type)
*/
addr1 = (volatile uint *) 0;
addr2 = (volatile uint *) 0x00400000;
for (i = 0, j = 0; i < 8; i++)
j = addr1[0];
for (i = 0; i < 8; i++)
in_be32(addr1);
/*
* Now check whether we got 4MB or 16MB populated
......
board/esd/pmc440/cmd_pmc440.c
浏览文件 @ 7708d8b3
......@@ -342,7 +342,8 @@ U_BOOT_CMD(
#if defined(CONFIG_PRAM)
#include <environment.h>
extern env_t *env_ptr;
#include <search.h>
#include <errno.h>
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
......@@ -351,6 +352,10 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
u32 param;
ulong *lptr;
env_t *envp;
char *res;
int len;
v = getenv("pram");
if (v)
pram = simple_strtoul(v, NULL, 10);
......@@ -384,7 +389,15 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/* env is first (4k aligned) */
nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
envp = (env_t *)nextbase;
res = (char *)envp->data;
len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
envp->crc = crc32(0, envp->data, ENV_SIZE);
*(--lptr) = CONFIG_ENV_SIZE; /* size */
*(--lptr) = base - nextbase; /* offset | type=0 */
......
board/esd/pmc440/pmc440.c
浏览文件 @ 7708d8b3
......@@ -574,8 +574,6 @@ void pci_target_init(struct pci_controller *hose)
/* No error reporting */
pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
if (!is_monarch()) {
/* Program the board's subsystem id/classcode */
pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
......@@ -617,21 +615,6 @@ void pci_master_init(struct pci_controller *hose)
static void wait_for_pci_ready(void)
{
int i;
char *s = getenv("pcidelay");
/*
* We have our own handling of the pcidelay variable.
* Using CONFIG_PCI_BOOTDELAY enables pausing for host
* and adapter devices. For adapter devices we do not
* want this.
*/
if (s) {
int ms = simple_strtoul(s, NULL, 10);
printf("PCI: Waiting for %d ms\n", ms);
for (i=0; i<ms; i++)
udelay(1000);
}
if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
while (1) {
......
board/freescale/common/Makefile
浏览文件 @ 7708d8b3
......@@ -34,6 +34,7 @@ COBJS-$(CONFIG_FSL_VIA) += cds_via.o
COBJS-$(CONFIG_FMAN_ENET) += fman.o
COBJS-$(CONFIG_FSL_PIXIS) += pixis.o
COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
COBJS-$(CONFIG_FSL_QIXIS) += qixis.o
COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o
......@@ -50,12 +51,14 @@ COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
COBJS-$(CONFIG_P3060QDS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
COBJS-$(CONFIG_P5020DS) += ics307_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
......
board/freescale/common/ics307_clk.c
浏览文件 @ 7708d8b3
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
......@@ -25,10 +25,15 @@
#include "ics307_clk.h"
#ifdef CONFIG_FSL_NGPIXIS
#if defined(CONFIG_FSL_NGPIXIS)
#include "ngpixis.h"
#define fpga_reg pixis
#elif defined(CONFIG_FSL_QIXIS)
#include "qixis.h"
#define fpga_reg ((struct qixis *)QIXIS_BASE)
#else
#include "pixis.h"
#define fpga_reg pixis
#endif
/* define for SYS CLK or CLK1Frequency */
......@@ -143,15 +148,15 @@ static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
unsigned long get_board_sys_clk(void)
{
return ics307_clk_freq(
in_8(&pixis->sclk[0]),
in_8(&pixis->sclk[1]),
in_8(&pixis->sclk[2]));
in_8(&fpga_reg->sclk[0]),
in_8(&fpga_reg->sclk[1]),
in_8(&fpga_reg->sclk[2]));
}
unsigned long get_board_ddr_clk(void)
{
return ics307_clk_freq(
in_8(&pixis->dclk[0]),
in_8(&pixis->dclk[1]),
in_8(&pixis->dclk[2]));
in_8(&fpga_reg->dclk[0]),
in_8(&fpga_reg->dclk[1]),
in_8(&fpga_reg->dclk[2]));
}
board/freescale/common/qixis.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/common/qixis.h 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/mpc8610hpcd/mpc8610hpcd.c
浏览文件 @ 7708d8b3
......@@ -235,12 +235,11 @@ void pci_init_board(void)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
struct fsl_pci_info pci_info;
u32 devdisr, pordevsr;
u32 devdisr;
int first_free_busno;
int pci_agent;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
first_free_busno = fsl_pcie_init_board(0);
......
board/freescale/p2020come/Makefile 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p2020come/ddr.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p2020come/law.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p2020come/p2020come.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p2020come/tlb.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p3060qds/Makefile 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p3060qds/ddr.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p3060qds/eth.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p3060qds/fixed_ddr.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p3060qds/p3060qds.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/freescale/p3060qds/p3060qds.h 0 → 100644
浏览文件 @ 7708d8b3
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __P3060QDS_H__
#define __P3060QDS_H__
#include <asm/fsl_ddr_sdram.h>
#include <asm/u-boot.h>
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
extern fixed_ddr_parm_t fixed_ddr_parm_0[];
#endif
board/freescale/p3060qds/p3060qds_qixis.h 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/gdsys/405ex/405ex.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/gdsys/405ex/405ex.h 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/gdsys/405ex/Makefile 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/gdsys/405ex/chip_config.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/gdsys/405ex/io64.c 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
board/gdsys/common/Makefile
浏览文件 @ 7708d8b3
此差异已折叠。
board/gdsys/common/miiphybb.c
浏览文件 @ 7708d8b3
此差异已折叠。
board/mpl/common/flash.c
浏览文件 @ 7708d8b3
此差异已折叠。
board/prodrive/alpr/fpga.c
浏览文件 @ 7708d8b3
此差异已折叠。
board/prodrive/alpr/nand.c
浏览文件 @ 7708d8b3
此差异已折叠。
board/sandburst/common/flash.c
浏览文件 @ 7708d8b3
此差异已折叠。
board/sbc405/strataflash.c
浏览文件 @ 7708d8b3
此差异已折叠。
boards.cfg
浏览文件 @ 7708d8b3
此差异已折叠。
common/cmd_bdinfo.c
浏览文件 @ 7708d8b3
此差异已折叠。
common/cmd_bootm.c
浏览文件 @ 7708d8b3
此差异已折叠。
common/image.c
浏览文件 @ 7708d8b3
此差异已折叠。
doc/README.p3060qds 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
drivers/block/fsl_sata.c
浏览文件 @ 7708d8b3
此差异已折叠。
drivers/block/fsl_sata.h
浏览文件 @ 7708d8b3
此差异已折叠。
drivers/block/sata_dwc.c
浏览文件 @ 7708d8b3
此差异已折叠。
drivers/input/i8042.c
浏览文件 @ 7708d8b3
此差异已折叠。
drivers/net/fm/fm.c
浏览文件 @ 7708d8b3
此差异已折叠。
drivers/qe/qe.c
浏览文件 @ 7708d8b3
此差异已折叠。
drivers/usb/host/sl811-hcd.c
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/MPC8569MDS.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/P1022DS.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/P1023RDS.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/P2020COME.h 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/P2041RDB.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/P3041DS.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/P3060QDS.h 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/P5020DS.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/PMC440.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/corenet_ds.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/eNET.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/io64.h 0 → 100644
浏览文件 @ 7708d8b3
此差异已折叠。
include/configs/p1_p2_rdb_pc.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/ddr_spd.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/gdsys_fpga.h
浏览文件 @ 7708d8b3
此差异已折叠。
include/image.h
浏览文件 @ 7708d8b3
此差异已折叠。
post/board/lwmon5/gdc.c
浏览文件 @ 7708d8b3
此差异已折叠。
tools/default_image.c
浏览文件 @ 7708d8b3
此差异已折叠。
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或