Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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