powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks

Signed-off-by: NChristophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: NHeiko Schocher <hs@denx.de>

arch/powerpc/cpu/mpc8xx/cpu.c

@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static char *cpu_warning = "\n         " \
 	"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
 
-static int check_CPU (long clock, uint pvr, uint immr)
+static int check_CPU(long clock, uint pvr, uint immr)
 {
 	char *id_str =
 	NULL;
@@ -73,22 +73,25 @@ static int check_CPU (long clock, uint pvr, uint immr)
 			id_str =
 		"PC866x"; /* Unknown chip from MPC866 family */
 		break;
-	case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
+	case 0x09000000:
+		pre = 'M'; mid = suf = ""; m = 1;
 		if (id_str == NULL)
 			id_str = "PC885"; /* 870/875/880/885 */
 		break;
 
-	default: suf = NULL; break;
+	default:
+		suf = NULL;
+		break;
 	}
 
 	if (id_str == NULL)
 		id_str = "PC86x";	/* Unknown 86x chip */
 	if (suf)
-		printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
+		printf("%c%s%sZPnn%s", pre, id_str, mid, suf);
 	else
-		printf ("unknown M%s (0x%08x)", id_str, k);
+		printf("unknown M%s (0x%08x)", id_str, k);
 
-	printf (" at %s MHz: ", strmhz (buf, clock));
+	printf(" at %s MHz: ", strmhz(buf, clock));
 
 	print_size(checkicache(), " I-Cache ");
 	print_size(checkdcache(), " D-Cache");
@@ -97,64 +100,63 @@ static int check_CPU (long clock, uint pvr, uint immr)
 
 	out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
 	if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
-		printf (" FEC present");
+		printf(" FEC present");
 
-	if (!m) {
-		puts (cpu_warning);
-	}
+	if (!m)
+		puts(cpu_warning);
 
-	putc ('\n');
+	putc('\n');
 
 	return 0;
 }
 
 /* ------------------------------------------------------------------------- */
 
-int checkcpu (void)
+int checkcpu(void)
 {
 	ulong clock = gd->cpu_clk;
-	uint immr = get_immr (0);	/* Return full IMMR contents */
-	uint pvr = get_pvr ();
+	uint immr = get_immr(0);	/* Return full IMMR contents */
+	uint pvr = get_pvr();
 
-	puts ("CPU:   ");
+	puts("CPU:   ");
 
-	return check_CPU (clock, pvr, immr);
+	return check_CPU(clock, pvr, immr);
 }
 
 /* ------------------------------------------------------------------------- */
 /* L1 i-cache                                                                */
 
-int checkicache (void)
+int checkicache(void)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	memctl8xx_t __iomem *memctl = &immap->im_memctl;
-	u32 cacheon = rd_ic_cst () & IDC_ENABLED;
+	u32 cacheon = rd_ic_cst() & IDC_ENABLED;
 	/* probe in flash memoryarea */
 	u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
 	u32 m;
 	u32 lines = -1;
 
-	wr_ic_cst (IDC_UNALL);
-	wr_ic_cst (IDC_INVALL);
-	wr_ic_cst (IDC_DISABLE);
+	wr_ic_cst(IDC_UNALL);
+	wr_ic_cst(IDC_INVALL);
+	wr_ic_cst(IDC_DISABLE);
 	__asm__ volatile ("isync");
 
-	while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
-		wr_ic_adr (k);
-		wr_ic_cst (IDC_LDLCK);
+	while (!((m = rd_ic_cst()) & IDC_CERR2)) {
+		wr_ic_adr(k);
+		wr_ic_cst(IDC_LDLCK);
 		__asm__ volatile ("isync");
 
 		lines++;
-		k += 0x10;				/* the number of bytes in a cacheline */
+		k += 0x10;	/* the number of bytes in a cacheline */
 	}
 
-	wr_ic_cst (IDC_UNALL);
-	wr_ic_cst (IDC_INVALL);
+	wr_ic_cst(IDC_UNALL);
+	wr_ic_cst(IDC_INVALL);
 
 	if (cacheon)
-		wr_ic_cst (IDC_ENABLE);
+		wr_ic_cst(IDC_ENABLE);
 	else
-		wr_ic_cst (IDC_DISABLE);
+		wr_ic_cst(IDC_DISABLE);
 
 	__asm__ volatile ("isync");
 
@@ -165,41 +167,41 @@ int checkicache (void)
 /* L1 d-cache                                                                */
 /* call with cache disabled                                                  */
 
-int checkdcache (void)
+int checkdcache(void)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	memctl8xx_t __iomem *memctl = &immap->im_memctl;
-	u32 cacheon = rd_dc_cst () & IDC_ENABLED;
+	u32 cacheon = rd_dc_cst() & IDC_ENABLED;
 	/* probe in flash memoryarea */
 	u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
 	u32 m;
 	u32 lines = -1;
 
-	wr_dc_cst (IDC_UNALL);
-	wr_dc_cst (IDC_INVALL);
-	wr_dc_cst (IDC_DISABLE);
+	wr_dc_cst(IDC_UNALL);
+	wr_dc_cst(IDC_INVALL);
+	wr_dc_cst(IDC_DISABLE);
 
-	while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
-		wr_dc_adr (k);
-		wr_dc_cst (IDC_LDLCK);
+	while (!((m = rd_dc_cst()) & IDC_CERR2)) {
+		wr_dc_adr(k);
+		wr_dc_cst(IDC_LDLCK);
 		lines++;
 		k += 0x10;	/* the number of bytes in a cacheline */
 	}
 
-	wr_dc_cst (IDC_UNALL);
-	wr_dc_cst (IDC_INVALL);
+	wr_dc_cst(IDC_UNALL);
+	wr_dc_cst(IDC_INVALL);
 
 	if (cacheon)
-		wr_dc_cst (IDC_ENABLE);
+		wr_dc_cst(IDC_ENABLE);
 	else
-		wr_dc_cst (IDC_DISABLE);
+		wr_dc_cst(IDC_DISABLE);
 
 	return lines << 4;
 };
 
 /* ------------------------------------------------------------------------- */
 
-void upmconfig (uint upm, uint * table, uint size)
+void upmconfig(uint upm, uint *table, uint size)
 {
 	uint i;
 	uint addr = 0;
@@ -215,7 +217,7 @@ void upmconfig (uint upm, uint * table, uint size)
 
 /* ------------------------------------------------------------------------- */
 
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	ulong msr, addr;
 
@@ -226,10 +228,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	/* Interrupts and MMU off */
 	__asm__ volatile ("mtspr    81, 0");
-	__asm__ volatile ("mfmsr    %0":"=r" (msr));
+	__asm__ volatile ("mfmsr    %0" : "=r" (msr));
 
 	msr &= ~0x1030;
-	__asm__ volatile ("mtmsr    %0"::"r" (msr));
+	__asm__ volatile ("mtmsr    %0" : : "r" (msr));
 
 	/*
 	 * Trying to execute the next instruction at a non-existing address
@@ -239,14 +241,15 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	addr = CONFIG_SYS_RESET_ADDRESS;
 #else
 	/*
-	 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
-	 * - sizeof (ulong) is usually a valid address. Better pick an address
-	 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
+	 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
+	 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
+	 * Better pick an address known to be invalid on your system and assign
+	 * it to CONFIG_SYS_RESET_ADDRESS.
 	 * "(ulong)-1" used to be a good choice for many systems...
 	 */
-	addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
+	addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
 #endif
-	((void (*)(void)) addr) ();
+	((void (*)(void)) addr)();
 	return 1;
 }
 
@@ -257,14 +260,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  *
  * See sections 14.2 and 14.6 of the User's Manual
  */
-unsigned long get_tbclk (void)
+unsigned long get_tbclk(void)
 {
-	uint immr = get_immr (0);	/* Return full IMMR contents */
+	uint immr = get_immr(0);	/* Return full IMMR contents */
 	immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
 	ulong oscclk, factor, pll;
 
 	if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
-		return (gd->cpu_clk / 16);
+		return gd->cpu_clk / 16;
 
 	pll = in_be32(&immap->im_clkrst.car_plprcr);
 
@@ -281,28 +284,28 @@ unsigned long get_tbclk (void)
 	 *	     (PDF + 1) * 2^S
 	 *
 	 */
-		factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
-			(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
+	factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
+		 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
 
 	oscclk = gd->cpu_clk / factor;
 
 	if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
 	    factor > 2)
-		return (oscclk / 4);
+		return oscclk / 4;
 
-	return (oscclk / 16);
+	return oscclk / 16;
 }
 
 /* ------------------------------------------------------------------------- */
 
 #if defined(CONFIG_WATCHDOG)
-void watchdog_reset (void)
+void watchdog_reset(void)
 {
-	int re_enable = disable_interrupts ();
+	int re_enable = disable_interrupts();
 
 	reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
 	if (re_enable)
-		enable_interrupts ();
+		enable_interrupts();
 }
 #endif /* CONFIG_WATCHDOG */
 

arch/powerpc/cpu/mpc8xx/cpu_init.c

@@ -29,7 +29,7 @@ void cpu_init_f(immap_t __iomem *immr)
 	out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
 
 #if defined(CONFIG_WATCHDOG)
-	reset_8xx_watchdog (immr);
+	reset_8xx_watchdog(immr);
 #endif /* CONFIG_WATCHDOG */
 
 	/* SIUMCR - contains debug pin configuration (11-6) */
@@ -182,7 +182,7 @@ void cpu_init_f(immap_t __iomem *immr)
 /*
  * initialize higher level parts of CPU like timers
  */
-int cpu_init_r (void)
+int cpu_init_r(void)
 {
-	return (0);
+	return 0;
 }

arch/powerpc/cpu/mpc8xx/fdt.c

@@ -15,13 +15,13 @@ DECLARE_GLOBAL_DATA_PTR;
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-		"timebase-frequency", get_tbclk(), 1);
+			     "timebase-frequency", get_tbclk(), 1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-		"bus-frequency", bd->bi_busfreq, 1);
+			     "bus-frequency", bd->bi_busfreq, 1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-		"clock-frequency", bd->bi_intfreq, 1);
+			     "clock-frequency", bd->bi_intfreq, 1);
 	do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
-		gd->arch.brg_clk, 1);
+			       gd->arch.brg_clk, 1);
 
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }

arch/powerpc/cpu/mpc8xx/fec.c

@@ -102,7 +102,7 @@ static struct ether_fcc_info_s
 #define PKT_MAXBLR_SIZE		1520
 
 #ifdef __GNUC__
-static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
+static char txbuf[DBUF_LENGTH] __aligned(8);
 #else
 #error txbuf must be aligned.
 #endif
@@ -117,28 +117,27 @@ static uint txIdx;	/* index of the current TX buffer */
   */
 
 struct common_buf_desc {
-    cbd_t rxbd[PKTBUFSRX];		/* Rx BD */
-    cbd_t txbd[TX_BUF_CNT];		/* Tx BD */
+	cbd_t rxbd[PKTBUFSRX];		/* Rx BD */
+	cbd_t txbd[TX_BUF_CNT];		/* Tx BD */
 };
 
 static struct common_buf_desc __iomem *rtx;
 
 static int fec_send(struct eth_device *dev, void *packet, int length);
-static int fec_recv(struct eth_device* dev);
-static int fec_init(struct eth_device* dev, bd_t * bd);
-static void fec_halt(struct eth_device* dev);
+static int fec_recv(struct eth_device *dev);
+static int fec_init(struct eth_device *dev, bd_t *bd);
+static void fec_halt(struct eth_device *dev);
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 static void __mii_init(void);
 #endif
 
 int fec_initialize(bd_t *bis)
 {
-	struct eth_device* dev;
+	struct eth_device *dev;
 	struct ether_fcc_info_s *efis;
 	int             i;
 
 	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
-
 		dev = malloc(sizeof(*dev));
 		if (dev == NULL)
 			hang();
@@ -147,12 +146,11 @@ int fec_initialize(bd_t *bis)
 
 		/* for FEC1 make sure that the name of the interface is the same
 		   as the old one for compatibility reasons */
-		if (i == 0) {
+		if (i == 0)
 			strcpy(dev->name, "FEC");
-		} else {
-			sprintf (dev->name, "FEC%d",
+		else
+			sprintf(dev->name, "FEC%d",
 				ether_fcc_info[i].ether_index + 1);
-		}
 
 		efis = &ether_fcc_info[i];
 
@@ -202,9 +200,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 		udelay(1);
 		j++;
 	}
-	if (j>=TOUT_LOOP) {
+	if (j >= TOUT_LOOP)
 		printf("TX not ready\n");
-	}
 
 	out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
 	out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
@@ -221,9 +218,9 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 		udelay(1);
 		j++;
 	}
-	if (j>=TOUT_LOOP) {
+	if (j >= TOUT_LOOP)
 		printf("TX timeout\n");
-	}
+
 	/* return only status bits */;
 	rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
 
@@ -232,7 +229,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 	return rc;
 }
 
-static int fec_recv (struct eth_device *dev)
+static int fec_recv(struct eth_device *dev)
 {
 	struct ether_fcc_info_s *efis = dev->priv;
 	fec_t __iomem *fecp =
@@ -436,7 +433,6 @@ static void fec_pin_init(int fecidx)
 
 #endif	/* CONFIG_ETHER_ON_FEC1 */
 	} else if (fecidx == 1) {
-
 #if defined(CONFIG_ETHER_ON_FEC2)
 
 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
@@ -467,7 +463,6 @@ static void fec_pin_init(int fecidx)
 #endif /* CONFIG_MPC885_FAMILY */
 
 #endif /* CONFIG_ETHER_ON_FEC2 */
-
 	}
 }
 
@@ -486,7 +481,7 @@ static int fec_reset(fec_t __iomem *fecp)
 	out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
 	for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
 	     (i < FEC_RESET_DELAY); ++i)
-		udelay (1);
+		udelay(1);
 
 	if (i == FEC_RESET_DELAY)
 		return -1;
@@ -494,7 +489,7 @@ static int fec_reset(fec_t __iomem *fecp)
 	return 0;
 }
 
-static int fec_init (struct eth_device *dev, bd_t * bd)
+static int fec_init(struct eth_device *dev, bd_t *bd)
 {
 	struct ether_fcc_info_s *efis = dev->priv;
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -512,7 +507,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 #endif
 
 	if (fec_reset(fecp) < 0)
-		printf ("FEC_RESET_DELAY timeout\n");
+		printf("FEC_RESET_DELAY timeout\n");
 
 	/* We use strictly polling mode only
 	 */
@@ -554,7 +549,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 	out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
 
 	/*
-	 * Setup Buffers and Buffer Desriptors
+	 * Setup Buffers and Buffer Descriptors
 	 */
 	rxIdx = 0;
 	txIdx = 0;
@@ -604,7 +599,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 	/*
 	 * Setup the pin configuration of the FEC
 	 */
-	fec_pin_init (efis->ether_index);
+	fec_pin_init(efis->ether_index);
 
 	rxIdx = 0;
 	txIdx = 0;
@@ -619,10 +614,10 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 		/*
 		 * wait for the PHY to wake up after reset
 		 */
-		efis->actual_phy_addr = mii_discover_phy (dev);
+		efis->actual_phy_addr = mii_discover_phy(dev);
 
 		if (efis->actual_phy_addr == -1) {
-			printf ("Unable to discover phy!\n");
+			printf("Unable to discover phy!\n");
 			return -1;
 		}
 #else
@@ -636,22 +631,20 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 	/*
 	 * adapt the RMII speed to the speed of the phy
 	 */
-	if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
-		fec_100Mbps (dev);
-	} else {
-		fec_10Mbps (dev);
-	}
+	if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
+		fec_100Mbps(dev);
+	else
+		fec_10Mbps(dev);
 #endif
 
 #if defined(CONFIG_MII)
 	/*
 	 * adapt to the half/full speed settings
 	 */
-	if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
-		fec_full_duplex (dev);
-	} else {
-		fec_half_duplex (dev);
-	}
+	if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
+		fec_full_duplex(dev);
+	else
+		fec_half_duplex(dev);
 #endif
 
 	/* And last, try to fill Rx Buffer Descriptors */
@@ -664,7 +657,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 }
 
 
-static void fec_halt(struct eth_device* dev)
+static void fec_halt(struct eth_device *dev)
 {
 	struct ether_fcc_info_s *efis = dev->priv;
 	fec_t __iomem *fecp =
@@ -686,10 +679,10 @@ static void fec_halt(struct eth_device* dev)
 	out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
 	for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
 	     (i < FEC_RESET_DELAY); ++i)
-		udelay (1);
+		udelay(1);
 
 	if (i == FEC_RESET_DELAY) {
-		printf ("FEC_RESET_DELAY timeout\n");
+		printf("FEC_RESET_DELAY timeout\n");
 		return;
 	}
 
@@ -744,7 +737,7 @@ mii_send(uint mii_cmd)
 	}
 	mii_reply = in_be32(&ep->fec_mii_data);		/* result from phy */
 	out_be32(&ep->fec_ievent, FEC_ENET_MII);	/* clear MII complete */
-	return (mii_reply & 0xffff);		/* data read from phy */
+	return mii_reply & 0xffff;		/* data read from phy */
 }
 #endif
 
@@ -776,9 +769,9 @@ static int mii_discover_phy(struct eth_device *dev)
 			}
 		}
 	}
-	if (phyaddr < 0) {
+	if (phyaddr < 0)
 		printf("No PHY device found.\n");
-	}
+
 	return phyaddr;
 }
 #endif	/* CONFIG_SYS_DISCOVER_PHY */
@@ -796,7 +789,7 @@ static void __mii_init(void)
 	fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
 
 	if (fec_reset(fecp) < 0)
-		printf ("FEC_RESET_DELAY timeout\n");
+		printf("FEC_RESET_DELAY timeout\n");
 
 	/* We use strictly polling mode only
 	 */
@@ -811,7 +804,7 @@ static void __mii_init(void)
 	out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
 }
 
-void mii_init (void)
+void mii_init(void)
 {
 	int i;
 

arch/powerpc/cpu/mpc8xx/immap.c

@@ -19,8 +19,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int
-do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_siuinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
@@ -37,8 +36,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-int
-do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_memcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	memctl8xx_t __iomem *memctl = &immap->im_memctl;
@@ -60,8 +58,7 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-int
-do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_carinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	car8xx_t __iomem *car = &immap->im_clkrst;
@@ -74,8 +71,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 static int counter;
 
-static void
-header(void)
+static void header(void)
 {
 	char *data = "\
        --------------------------------        --------------------------------\
@@ -93,27 +89,27 @@ header(void)
 		printf("%.79s\n", data);
 }
 
-static void binary (char *label, uint value, int nbits)
+static void binary(char *label, uint value, int nbits)
 {
 	uint mask = 1 << (nbits - 1);
 	int i, second = (counter++ % 2);
 
 	if (second)
-		putc (' ');
-	puts (label);
+		putc(' ');
+	puts(label);
 	for (i = 32 + 1; i != nbits; i--)
-		putc (' ');
+		putc(' ');
 
 	while (mask != 0) {
 		if (value & mask)
-			putc ('1');
+			putc('1');
 		else
-			putc ('0');
+			putc('0');
 		mask >>= 1;
 	}
 
 	if (second)
-		putc ('\n');
+		putc('\n');
 }
 
 #define PA_NBITS	16
@@ -123,8 +119,7 @@ static void binary (char *label, uint value, int nbits)
 #define PC_NBITS	12
 #define PD_NBITS	13
 
-int
-do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_iopinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	iop8xx_t __iomem *iop = &immap->im_ioport;
@@ -132,7 +127,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	uint __iomem *R;
 
 	counter = 0;
-	header ();
+	header();
 
 	/*
 	 * Ports A & B
@@ -149,7 +144,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	binary("PA_DAT", in_be16(l++), PA_NBITS);
 	binary("PB_DAT", in_be32(R++), PB_NBITS);
 
-	header ();
+	header();
 
 	/*
 	 * Ports C & D
@@ -168,7 +163,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	binary("PD_DAT", in_be16(r++), PD_NBITS);
 	binary("PC_INT", in_be16(l++), PC_NBITS);
 
-	header ();
+	header();
 	return 0;
 }
 
@@ -177,14 +172,13 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  * this needs a clean up for smaller tighter code
  * use *uint and set the address based on cmd + port
  */
-int
-do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_iopset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	uint rcode = 0;
 	iopin_t iopin;
-	static uint port = 0;
-	static uint pin = 0;
-	static uint value = 0;
+	static uint port;
+	static uint pin;
+	static uint value;
 	static enum {
 		DIR,
 		PAR,
@@ -195,7 +189,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	} cmd = DAT;
 
 	if (argc != 5) {
-		puts ("iopset PORT PIN CMD VALUE\n");
+		puts("iopset PORT PIN CMD VALUE\n");
 		return 1;
 	}
 	port = argv[1][0] - 'A';
@@ -203,7 +197,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		port -= 0x20;
 	if (port > 3)
 		rcode = 1;
-	pin = simple_strtol (argv[2], NULL, 10);
+	pin = simple_strtol(argv[2], NULL, 10);
 	if (pin > 31)
 		rcode = 1;
 
@@ -230,7 +224,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		cmd = INT;
 		break;
 	default:
-		printf ("iopset: unknown command %s\n", argv[3]);
+		printf("iopset: unknown command %s\n", argv[3]);
 		rcode = 1;
 	}
 	if (argv[4][0] == '1')
@@ -246,47 +240,46 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		switch (cmd) {
 		case DIR:
 			if (value)
-				iopin_set_out (&iopin);
+				iopin_set_out(&iopin);
 			else
-				iopin_set_in (&iopin);
+				iopin_set_in(&iopin);
 			break;
 		case PAR:
 			if (value)
-				iopin_set_ded (&iopin);
+				iopin_set_ded(&iopin);
 			else
-				iopin_set_gen (&iopin);
+				iopin_set_gen(&iopin);
 			break;
 		case SOR:
 			if (value)
-				iopin_set_opt2 (&iopin);
+				iopin_set_opt2(&iopin);
 			else
-				iopin_set_opt1 (&iopin);
+				iopin_set_opt1(&iopin);
 			break;
 		case ODR:
 			if (value)
-				iopin_set_odr (&iopin);
+				iopin_set_odr(&iopin);
 			else
-				iopin_set_act (&iopin);
+				iopin_set_act(&iopin);
 			break;
 		case DAT:
 			if (value)
-				iopin_set_high (&iopin);
+				iopin_set_high(&iopin);
 			else
-				iopin_set_low (&iopin);
+				iopin_set_low(&iopin);
 			break;
 		case INT:
 			if (value)
-				iopin_set_falledge (&iopin);
+				iopin_set_falledge(&iopin);
 			else
-				iopin_set_anyedge (&iopin);
+				iopin_set_anyedge(&iopin);
 			break;
 		}
-
 	}
 	return rcode;
 }
 
-static void prbrg (int n, uint val)
+static void prbrg(int n, uint val)
 {
 	uint extc = (val >> 14) & 3;
 	uint cd = (val & CPM_BRG_CD_MASK) >> 1;
@@ -294,26 +287,26 @@ static void prbrg (int n, uint val)
 
 	ulong clock = gd->cpu_clk;
 
-	printf ("BRG%d:", n);
+	printf("BRG%d:", n);
 
 	if (val & CPM_BRG_RST)
-		puts (" RESET");
+		puts(" RESET");
 	else
-		puts ("      ");
+		puts("      ");
 
 	if (val & CPM_BRG_EN)
-		puts ("  ENABLED");
+		puts("  ENABLED");
 	else
-		puts (" DISABLED");
+		puts(" DISABLED");
 
-	printf (" EXTC=%d", extc);
+	printf(" EXTC=%d", extc);
 
 	if (val & CPM_BRG_ATB)
-		puts (" ATB");
+		puts(" ATB");
 	else
-		puts ("    ");
+		puts("    ");
 
-	printf (" DIVIDER=%4d", cd);
+	printf(" DIVIDER=%4d", cd);
 	if (extc == 0 && cd != 0) {
 		uint baudrate;
 
@@ -322,21 +315,20 @@ static void prbrg (int n, uint val)
 		else
 			baudrate = clock / (cd + 1);
 
-		printf ("=%6d bps", baudrate);
+		printf("=%6d bps", baudrate);
 	} else {
-		puts ("           ");
+		puts("           ");
 	}
 
 	if (val & CPM_BRG_DIV16)
-		puts (" DIV16");
+		puts(" DIV16");
 	else
-		puts ("      ");
+		puts("      ");
 
-	putc ('\n');
+	putc('\n');
 }
 
-int
-do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_brginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	cpm8xx_t __iomem *cp = &immap->im_cpm;

arch/powerpc/cpu/mpc8xx/interrupts.c

@@ -25,24 +25,24 @@ struct interrupt_action {
 static struct interrupt_action cpm_vecs[CPMVEC_NR];
 static struct interrupt_action irq_vecs[NR_IRQS];
 
-static void cpm_interrupt_init (void);
-static void cpm_interrupt (void *regs);
+static void cpm_interrupt_init(void);
+static void cpm_interrupt(void *regs);
 
 /************************************************************************/
 
-int interrupt_init_cpu (unsigned *decrementer_count)
+int interrupt_init_cpu(unsigned *decrementer_count)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
-	*decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
+	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
 
 	/* disable all interrupts */
 	out_be32(&immr->im_siu_conf.sc_simask, 0);
 
 	/* Configure CPM interrupts */
-	cpm_interrupt_init ();
+	cpm_interrupt_init();
 
-	return (0);
+	return 0;
 }
 
 /************************************************************************/
@@ -50,7 +50,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 /*
  * Handle external interrupts
  */
-void external_interrupt (struct pt_regs *regs)
+void external_interrupt(struct pt_regs *regs)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	int irq;
@@ -88,10 +88,10 @@ void external_interrupt (struct pt_regs *regs)
 	}
 
 	if (irq_vecs[irq].handler != NULL) {
-		irq_vecs[irq].handler (irq_vecs[irq].arg);
+		irq_vecs[irq].handler(irq_vecs[irq].arg);
 	} else {
-		printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
-				irq, vec);
+		printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
+		       irq, vec);
 		/* turn off the bogus interrupt to avoid it from now */
 		simask &= ~v_bit;
 	}
@@ -106,7 +106,7 @@ void external_interrupt (struct pt_regs *regs)
 /*
  * CPM interrupt handler
  */
-static void cpm_interrupt (void *regs)
+static void cpm_interrupt(void *regs)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	uint vec;
@@ -123,7 +123,7 @@ static void cpm_interrupt (void *regs)
 		(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
 	} else {
 		clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
-		printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
+		printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
 	}
 	/*
 	 * After servicing the interrupt,
@@ -138,7 +138,7 @@ static void cpm_interrupt (void *regs)
  * to do is ACK it and return. This is a no-op function so we don't
  * need any special tests in the interrupt handler.
  */
-static void cpm_error_interrupt (void *dummy)
+static void cpm_error_interrupt(void *dummy)
 {
 }
 
@@ -146,37 +146,31 @@ static void cpm_error_interrupt (void *dummy)
 /*
  * Install and free an interrupt handler
  */
-void irq_install_handler (int vec, interrupt_handler_t * handler,
-						  void *arg)
+void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
 	if ((vec & CPMVEC_OFFSET) != 0) {
 		/* CPM interrupt */
 		vec &= 0xffff;
-		if (cpm_vecs[vec].handler != NULL) {
-			printf ("CPM interrupt 0x%x replacing 0x%x\n",
-				(uint) handler,
-				(uint) cpm_vecs[vec].handler);
-		}
+		if (cpm_vecs[vec].handler != NULL)
+			printf("CPM interrupt 0x%x replacing 0x%x\n",
+			       (uint)handler, (uint)cpm_vecs[vec].handler);
 		cpm_vecs[vec].handler = handler;
 		cpm_vecs[vec].arg = arg;
 		setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
 	} else {
 		/* SIU interrupt */
-		if (irq_vecs[vec].handler != NULL) {
-			printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
-				vec,
-				(uint) handler,
-				(uint) cpm_vecs[vec].handler);
-		}
+		if (irq_vecs[vec].handler != NULL)
+			printf("SIU interrupt %d 0x%x replacing 0x%x\n",
+			       vec, (uint)handler, (uint)cpm_vecs[vec].handler);
 		irq_vecs[vec].handler = handler;
 		irq_vecs[vec].arg = arg;
 		setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
 	}
 }
 
-void irq_free_handler (int vec)
+void irq_free_handler(int vec)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -196,7 +190,7 @@ void irq_free_handler (int vec)
 
 /************************************************************************/
 
-static void cpm_interrupt_init (void)
+static void cpm_interrupt_init(void)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	uint cicr;
@@ -214,14 +208,14 @@ static void cpm_interrupt_init (void)
 	/*
 	 * Install the error handler.
 	 */
-	irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
+	irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
 
 	setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
 
 	/*
 	 * Install the cpm interrupt handler
 	 */
-	irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
+	irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
 }
 
 /************************************************************************/
@@ -231,7 +225,7 @@ static void cpm_interrupt_init (void)
  * with interrupts disabled.
  * Trivial implementation - no need to be really accurate.
  */
-void timer_interrupt_cpu (struct pt_regs *regs)
+void timer_interrupt_cpu(struct pt_regs *regs)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 

arch/powerpc/cpu/mpc8xx/reginfo.c

@@ -20,7 +20,7 @@ void mpc8xx_reginfo(void)
 	 * other useful registers
 	 */
 
-	printf ("\nSystem Configuration registers\n"
+	printf("\nSystem Configuration registers\n"
 		"\tIMMR\t0x%08X\n", get_immr(0));
 
 	printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));

arch/powerpc/cpu/mpc8xx/serial.c

@@ -49,11 +49,11 @@ struct serialbuffer {
 
 static void serial_setdivisor(cpm8xx_t __iomem *cp)
 {
-	int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
+	int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate;
 
-	if(divisor/16>0x1000) {
+	if (divisor / 16 > 0x1000) {
 		/* bad divisor, assume 50MHz clock and 9600 baud */
-		divisor=(50*1000*1000 + 8*9600)/16/9600;
+		divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
 	}
 
 #ifdef CONFIG_SYS_BRGCLK_PRESCALE
@@ -72,7 +72,7 @@ static void serial_setdivisor(cpm8xx_t __iomem *cp)
  * as serial console interface.
  */
 
-static void smc_setbrg (void)
+static void smc_setbrg(void)
 {
 	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	cpm8xx_t __iomem *cp = &(im->im_cpm);
@@ -88,7 +88,7 @@ static void smc_setbrg (void)
 	serial_setdivisor(cp);
 }
 
-static int smc_init (void)
+static int smc_init(void)
 {
 	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	smc_t __iomem *sp;
@@ -161,7 +161,7 @@ static int smc_init (void)
 	out_8(&sp->smc_smce, 0xff);
 
 	/* Set up the baud rate generator */
-	smc_setbrg ();
+	smc_setbrg();
 
 	/* Make the first buffer the only buffer. */
 	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
@@ -185,18 +185,17 @@ static int smc_init (void)
 	/* Enable transmitter/receiver.	*/
 	setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
 
-	return (0);
+	return 0;
 }
 
-static void
-smc_putc(const char c)
+static void smc_putc(const char c)
 {
 	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
 	struct serialbuffer	__iomem *rtx;
 
 	if (c == '\n')
-		smc_putc ('\r');
+		smc_putc('\r');
 
 	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
 
@@ -206,19 +205,16 @@ smc_putc(const char c)
 	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
 
 	while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
-		WATCHDOG_RESET ();
+		WATCHDOG_RESET();
 }
 
-static void
-smc_puts (const char *s)
+static void smc_puts(const char *s)
 {
-	while (*s) {
-		smc_putc (*s++);
-	}
+	while (*s)
+		smc_putc(*s++);
 }
 
-static int
-smc_getc(void)
+static int smc_getc(void)
 {
 	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
@@ -230,7 +226,7 @@ smc_getc(void)
 
 	/* Wait for character to show up. */
 	while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
-		WATCHDOG_RESET ();
+		WATCHDOG_RESET();
 
 	/* the characters are read one by one,
 	 * use the rxindex to know the next char to deliver
@@ -245,11 +241,10 @@ smc_getc(void)
 		setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
 	}
 	out_be32(&rtx->rxindex, rxindex);
-	return(c);
+	return c;
 }
 
-static int
-smc_tstc(void)
+static int smc_tstc(void)
 {
 	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
@@ -260,8 +255,7 @@ smc_tstc(void)
 	return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
 }
 
-struct serial_device serial_smc_device =
-{
+struct serial_device serial_smc_device = {
 	.name	= "serial_smc",
 	.start	= smc_init,
 	.stop	= NULL,

arch/powerpc/cpu/mpc8xx/speed.c

@@ -16,29 +16,29 @@ void get_brgclk(uint sccr)
 {
 	uint divider = 0;
 
-	switch((sccr&SCCR_DFBRG11)>>11){
-		case 0:
-			divider = 1;
-			break;
-		case 1:
-			divider = 4;
-			break;
-		case 2:
-			divider = 16;
-			break;
-		case 3:
-			divider = 64;
-			break;
+	switch ((sccr & SCCR_DFBRG11) >> 11) {
+	case 0:
+		divider = 1;
+		break;
+	case 1:
+		divider = 4;
+		break;
+	case 2:
+		divider = 16;
+		break;
+	case 3:
+		divider = 64;
+		break;
 	}
-	gd->arch.brg_clk = gd->cpu_clk/divider;
+	gd->arch.brg_clk = gd->cpu_clk / divider;
 }
 
 /*
  * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
  */
-int get_clocks (void)
+int get_clocks(void)
 {
-	uint immr = get_immr (0);	/* Return full IMMR contents */
+	uint immr = get_immr(0);	/* Return full IMMR contents */
 	immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
 	uint sccr = in_be32(&immap->im_clkrst.car_sccr);
 	/*
@@ -59,5 +59,5 @@ int get_clocks (void)
 
 	get_brgclk(sccr);
 
-	return (0);
+	return 0;
 }

arch/powerpc/cpu/mpc8xx/spi.c

@@ -50,11 +50,7 @@
 /* -------------------
  * Function prototypes
  * ------------------- */
-void spi_init (void);
-
-ssize_t spi_read (uchar *, int, uchar *, int);
-ssize_t spi_write (uchar *, int, uchar *, int);
-ssize_t spi_xfer (size_t);
+ssize_t spi_xfer(size_t);
 
 /* -------------------
  * Variables
@@ -66,10 +62,10 @@ ssize_t spi_xfer (size_t);
  * Initially we place the RX and TX buffers at a fixed location in DPRAM!
  * ---------------------------------------------------------------------- */
 static uchar *rxbuf =
-  (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+	(uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
 			[CONFIG_SYS_SPI_INIT_OFFSET];
 static uchar *txbuf =
-  (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+	(uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
 			[CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
 
 /* **************************************************************************
@@ -81,7 +77,7 @@ static uchar *txbuf =
  *  return:      ---
  *
  * *********************************************************************** */
-void spi_init_f (void)
+void spi_init_f(void)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	cpm8xx_t __iomem *cp = &immr->im_cpm;
@@ -120,7 +116,7 @@ void spi_init_f (void)
 	 * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
 	 * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
 	 * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
-	 * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
+	 * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
 	 * ---------------------------------------------- */
 
 	clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
@@ -209,7 +205,7 @@ void spi_init_f (void)
  *  return:      ---
  *
  * *********************************************************************** */
-void spi_init_r (void)
+void spi_init_r(void)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	cpm8xx_t __iomem *cp = &immr->im_cpm;
@@ -224,8 +220,8 @@ void spi_init_r (void)
 	rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
 
 	/* Allocate memory for RX and TX buffers */
-	rxbuf = (uchar *) malloc (MAX_BUFFER);
-	txbuf = (uchar *) malloc (MAX_BUFFER);
+	rxbuf = (uchar *)malloc(MAX_BUFFER);
+	txbuf = (uchar *)malloc(MAX_BUFFER);
 
 	out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
 	out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
@@ -236,7 +232,7 @@ void spi_init_r (void)
 /****************************************************************************
  *  Function:    spi_write
  **************************************************************************** */
-ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
 {
 	int i;
 
@@ -253,14 +249,12 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
 		*txbuf = SPI_EEPROM_RDSR;	/* read status		*/
 		txbuf[1] = 0;
 		spi_xfer(2);
-		if (!(rxbuf[1] & 1)) {
+		if (!(rxbuf[1] & 1))
 			break;
-		}
 		udelay(1000);
 	}
-	if (i >= 1000) {
-		printf ("*** spi_write: Time out while writing!\n");
-	}
+	if (i >= 1000)
+		printf("*** spi_write: Time out while writing!\n");
 
 	return len;
 }
@@ -268,7 +262,7 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
 /****************************************************************************
  *  Function:    spi_read
  **************************************************************************** */
-ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
 {
 	memset(rxbuf, 0, MAX_BUFFER);
 	memset(txbuf, 0, MAX_BUFFER);
@@ -290,7 +284,7 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
 /****************************************************************************
  *  Function:    spi_xfer
  **************************************************************************** */
-ssize_t spi_xfer (size_t count)
+ssize_t spi_xfer(size_t count)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	cpm8xx_t __iomem *cp = &immr->im_cpm;
@@ -327,16 +321,15 @@ ssize_t spi_xfer (size_t count)
 	 * Wait for SPI transmit to get out
 	 * or time out (1 second = 1000 ms)
 	 * -------------------------------- */
-	for (tm=0; tm<1000; ++tm) {
+	for (tm = 0; tm < 1000; ++tm) {
 		if (in_8(&cp->cp_spie) & SPI_TXB)	/* Tx Buffer Empty */
 			break;
 		if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
 			break;
-		udelay (1000);
-	}
-	if (tm >= 1000) {
-		printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
+		udelay(1000);
 	}
+	if (tm >= 1000)
+		printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
 
 	/* Clear CS for device */
 	setbits_be32(&cp->cp_pbdat, 0x0001);

arch/powerpc/cpu/mpc8xx/traps.c

@@ -45,7 +45,8 @@ static void print_backtrace(unsigned long *sp)
 		if (cnt++ % 7 == 0)
 			printf("\n");
 		printf("%08lX ", i);
-		if (cnt > 32) break;
+		if (cnt > 32)
+			break;
 		sp = (unsigned long *)*sp;
 	}
 	printf("\n");
@@ -58,23 +59,19 @@ void show_regs(struct pt_regs *regs)
 	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
 	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
 	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
-	       regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
-	       regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
-	       regs->msr&MSR_IR ? 1 : 0,
-	       regs->msr&MSR_DR ? 1 : 0);
+	       regs->msr, regs->msr & MSR_EE ? 1 : 0,
+	       regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
+	       regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
+	       regs->msr & MSR_DR ? 1 : 0);
 
 	printf("\n");
 	for (i = 0;  i < 32;  i++) {
 		if ((i % 8) == 0)
-		{
 			printf("GPR%02d: ", i);
-		}
 
 		printf("%08lX ", regs->gpr[i]);
 		if ((i % 8) == 7)
-		{
 			printf("\n");
-		}
 	}
 }
 
@@ -83,37 +80,37 @@ static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+	panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
 }
 
 void MachineCheckException(struct pt_regs *regs)
 {
-	unsigned long fixup;
+	unsigned long fixup = search_exception_table(regs->nip);
 
 	/* Probing PCI using config cycles cause this exception
 	 * when a device is not present.  Catch it and return to
 	 * the PCI exception handler.
 	 */
-	if ((fixup = search_exception_table(regs->nip)) != 0) {
+	if (fixup != 0) {
 		regs->nip = fixup;
 		return;
 	}
 
 	printf("Machine check in kernel mode.\n");
 	printf("Caused by (from msr): ");
-	printf("regs %p ",regs);
-	switch( regs->msr & 0x000F0000) {
-	case (0x80000000>>12):
+	printf("regs %p ", regs);
+	switch (regs->msr & 0x000F0000) {
+	case (0x80000000 >> 12):
 		printf("Machine check signal - probably due to mm fault\n"
 			"with mmu off\n");
 		break;
-	case (0x80000000>>13):
+	case (0x80000000 >> 13):
 		printf("Transfer error ack signal\n");
 		break;
-	case (0x80000000>>14):
+	case (0x80000000 >> 14):
 		printf("Data parity signal\n");
 		break;
-	case (0x80000000>>15):
+	case (0x80000000 >> 15):
 		printf("Address parity signal\n");
 		break;
 	default:
@@ -155,8 +152,8 @@ void UnknownException(struct pt_regs *regs)
 
 void DebugException(struct pt_regs *regs)
 {
-  printf("Debugger trap at @ %lx\n", regs->nip );
-  show_regs(regs);
+	printf("Debugger trap at @ %lx\n", regs->nip);
+	show_regs(regs);
 }
 
 /* Probe an address by reading.  If not present, return -1, otherwise

arch/powerpc/include/asm/iopin_8xx.h

@@ -27,8 +27,7 @@ typedef struct {
 #define IOPIN_PORTC	2
 #define IOPIN_PORTD	3
 
-static __inline__ void
-iopin_set_high(iopin_t *iopin)
+static inline void iopin_set_high(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -51,8 +50,7 @@ iopin_set_high(iopin_t *iopin)
 	}
 }
 
-static __inline__ void
-iopin_set_low(iopin_t *iopin)
+static inline void iopin_set_low(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -75,8 +73,7 @@ iopin_set_low(iopin_t *iopin)
 	}
 }
 
-static __inline__ uint
-iopin_is_high(iopin_t *iopin)
+static inline uint iopin_is_high(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -100,8 +97,7 @@ iopin_is_high(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ uint
-iopin_is_low(iopin_t *iopin)
+static inline uint iopin_is_low(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -125,8 +121,7 @@ iopin_is_low(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ void
-iopin_set_out(iopin_t *iopin)
+static inline void iopin_set_out(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -149,8 +144,7 @@ iopin_set_out(iopin_t *iopin)
 	}
 }
 
-static __inline__ void
-iopin_set_in(iopin_t *iopin)
+static inline void iopin_set_in(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -173,8 +167,7 @@ iopin_set_in(iopin_t *iopin)
 	}
 }
 
-static __inline__ uint
-iopin_is_out(iopin_t *iopin)
+static inline uint iopin_is_out(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -198,8 +191,7 @@ iopin_is_out(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ uint
-iopin_is_in(iopin_t *iopin)
+static inline uint iopin_is_in(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -223,8 +215,7 @@ iopin_is_in(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ void
-iopin_set_odr(iopin_t *iopin)
+static inline void iopin_set_odr(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -239,8 +230,7 @@ iopin_set_odr(iopin_t *iopin)
 	}
 }
 
-static __inline__ void
-iopin_set_act(iopin_t *iopin)
+static inline void iopin_set_act(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -255,8 +245,7 @@ iopin_set_act(iopin_t *iopin)
 	}
 }
 
-static __inline__ uint
-iopin_is_odr(iopin_t *iopin)
+static inline uint iopin_is_odr(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -272,8 +261,7 @@ iopin_is_odr(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ uint
-iopin_is_act(iopin_t *iopin)
+static inline uint iopin_is_act(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -289,8 +277,7 @@ iopin_is_act(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ void
-iopin_set_ded(iopin_t *iopin)
+static inline void iopin_set_ded(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -313,8 +300,7 @@ iopin_set_ded(iopin_t *iopin)
 	}
 }
 
-static __inline__ void
-iopin_set_gen(iopin_t *iopin)
+static inline void iopin_set_gen(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -337,8 +323,7 @@ iopin_set_gen(iopin_t *iopin)
 	}
 }
 
-static __inline__ uint
-iopin_is_ded(iopin_t *iopin)
+static inline uint iopin_is_ded(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -362,8 +347,7 @@ iopin_is_ded(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ uint
-iopin_is_gen(iopin_t *iopin)
+static inline uint iopin_is_gen(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -387,8 +371,7 @@ iopin_is_gen(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ void
-iopin_set_opt2(iopin_t *iopin)
+static inline void iopin_set_opt2(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -399,8 +382,7 @@ iopin_set_opt2(iopin_t *iopin)
 	}
 }
 
-static __inline__ void
-iopin_set_opt1(iopin_t *iopin)
+static inline void iopin_set_opt1(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -411,8 +393,7 @@ iopin_set_opt1(iopin_t *iopin)
 	}
 }
 
-static __inline__ uint
-iopin_is_opt2(iopin_t *iopin)
+static inline uint iopin_is_opt2(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -424,8 +405,7 @@ iopin_is_opt2(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ uint
-iopin_is_opt1(iopin_t *iopin)
+static inline uint iopin_is_opt1(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -437,8 +417,7 @@ iopin_is_opt1(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ void
-iopin_set_falledge(iopin_t *iopin)
+static inline void iopin_set_falledge(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -449,8 +428,7 @@ iopin_set_falledge(iopin_t *iopin)
 	}
 }
 
-static __inline__ void
-iopin_set_anyedge(iopin_t *iopin)
+static inline void iopin_set_anyedge(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -461,8 +439,7 @@ iopin_set_anyedge(iopin_t *iopin)
 	}
 }
 
-static __inline__ uint
-iopin_is_falledge(iopin_t *iopin)
+static inline uint iopin_is_falledge(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 
@@ -474,8 +451,7 @@ iopin_is_falledge(iopin_t *iopin)
 	return 0;
 }
 
-static __inline__ uint
-iopin_is_anyedge(iopin_t *iopin)
+static inline uint iopin_is_anyedge(iopin_t *iopin)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 

include/commproc.h

@@ -7,7 +7,7 @@
  *
  * This file contains structures and information for the communication
  * processor channels.  Some CPM control and status is available
- * throught the MPC8xx internal memory map.  See immap.h for details.
+ * through the MPC8xx internal memory map.  See immap.h for details.
  * This file only contains what I need for the moment, not the total
  * CPM capabilities.  I (or someone else) will add definitions as they
  * are needed.  -- Dan
@@ -81,7 +81,7 @@ typedef struct cpm_buf_desc {
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
 #define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
 #define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
-#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
+#define BD_SC_CM	((ushort)0x0200)	/* Continuous mode */
 #define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
 #define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
 #define BD_SC_BR	((ushort)0x0020)	/* Break received */
@@ -582,8 +582,8 @@ typedef struct spi {
 #define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
 #define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
 
-#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x)	((x) &0xF)
+#define SPMODE_LEN(x)	((((x) - 1) & 0xF) << 4)
+#define SPMODE_PM(x)	((x) & 0xF)
 
 /* HDLC parameter RAM.
 */
@@ -672,7 +672,7 @@ typedef struct hdlc_pram_s {
 #define CPMVEC_PIO_PC4		((ushort)0x01 | CPMVEC_OFFSET)
 #define CPMVEC_ERROR		((ushort)0x00 | CPMVEC_OFFSET)
 
-extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
+void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
 
 /* CPM interrupt configuration vector.
 */
@@ -680,7 +680,7 @@ extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
 #define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
 #define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
 #define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
-#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrrupt */
+#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrupt */
 #define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
 #define CICR_IEN		((uint)0x00000080)	/* Int. enable */
 #define CICR_SPS		((uint)0x00000001)	/* SCC Spread */