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体验新版 GitCode,发现更多精彩内容 >>
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70bd39d7
编写于
1月 03, 2020
作者:
T
Tom Rini
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差异文件
Merge branch '2020-01-03-master-imports'
- Fixes for host tools with musl C library - Two fixes for TI K3 platforms
上级
4b75aa5a
40109f4d
变更
7
隐藏空白更改
内联
并排
Showing
7 changed file
with
34 addition
and
4 deletion
+34
-4
arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
+3
-3
arch/arm/mach-k3/am6_init.c
arch/arm/mach-k3/am6_init.c
+1
-0
arch/arm/mach-k3/common.c
arch/arm/mach-k3/common.c
+25
-0
arch/arm/mach-k3/common.h
arch/arm/mach-k3/common.h
+1
-0
arch/arm/mach-k3/j721e_init.c
arch/arm/mach-k3/j721e_init.c
+1
-0
include/compiler.h
include/compiler.h
+1
-1
include/u-boot/crc.h
include/u-boot/crc.h
+2
-0
未找到文件。
arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
浏览文件 @
70bd39d7
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.
1
.0
* This file was generated on
09/06
/2019
* This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.
2
.0
* This file was generated on
10/09
/2019
*/
#define DDRSS_PLL_FHS_CNT 10
...
...
@@ -283,7 +283,7 @@
#define DDRSS_CTL_271_DATA 0x1FFF1000
#define DDRSS_CTL_272_DATA 0x01FF0000
#define DDRSS_CTL_273_DATA 0x000101FF
#define DDRSS_CTL_274_DATA 0x
F
FFF0B00
#define DDRSS_CTL_274_DATA 0x
0
FFF0B00
#define DDRSS_CTL_275_DATA 0x01010001
#define DDRSS_CTL_276_DATA 0x01010101
#define DDRSS_CTL_277_DATA 0x01180101
...
...
arch/arm/mach-k3/am6_init.c
浏览文件 @
70bd39d7
...
...
@@ -82,6 +82,7 @@ void board_init_f(ulong dummy)
ctrl_mmr_unlock
();
#ifdef CONFIG_CPU_V7R
disable_linefill_optimization
();
setup_k3_mpu_regions
();
#endif
...
...
arch/arm/mach-k3/common.c
浏览文件 @
70bd39d7
...
...
@@ -244,3 +244,28 @@ void board_prep_linux(bootm_headers_t *images)
CONFIG_SYS_CACHELINE_SIZE
));
}
#endif
#ifdef CONFIG_CPU_V7R
void
disable_linefill_optimization
(
void
)
{
u32
actlr
;
/*
* On K3 devices there are 2 conditions where R5F can deadlock:
* 1.When software is performing series of store operations to
* cacheable write back/write allocate memory region and later
* on software execute barrier operation (DSB or DMB). R5F may
* hang at the barrier instruction.
* 2.When software is performing a mix of load and store operations
* within a tight loop and store operations are all writing to
* cacheable write back/write allocates memory regions, R5F may
* hang at one of the load instruction.
*
* To avoid the above two conditions disable linefill optimization
* inside Cortex R5F.
*/
asm
(
"mrc p15, 0, %0, c1, c0, 1"
:
"=r"
(
actlr
));
actlr
|=
(
1
<<
13
);
/* Set DLFO bit */
asm
(
"mcr p15, 0, %0, c1, c0, 1"
:
:
"r"
(
actlr
));
}
#endif
arch/arm/mach-k3/common.h
浏览文件 @
70bd39d7
...
...
@@ -16,3 +16,4 @@
void
setup_k3_mpu_regions
(
void
);
int
early_console_init
(
void
);
void
disable_linefill_optimization
(
void
);
arch/arm/mach-k3/j721e_init.c
浏览文件 @
70bd39d7
...
...
@@ -87,6 +87,7 @@ void board_init_f(ulong dummy)
ctrl_mmr_unlock
();
#ifdef CONFIG_CPU_V7R
disable_linefill_optimization
();
setup_k3_mpu_regions
();
#endif
...
...
include/compiler.h
浏览文件 @
70bd39d7
...
...
@@ -46,7 +46,6 @@
# include <byteswap.h>
#elif defined(__MACH__) || defined(__FreeBSD__)
# include <machine/endian.h>
typedef
unsigned
long
ulong
;
#endif
#ifdef __FreeBSD__
# include <sys/endian.h>
/* htole32 and friends */
...
...
@@ -66,6 +65,7 @@ typedef uint8_t __u8;
typedef
uint16_t
__u16
;
typedef
uint32_t
__u32
;
typedef
unsigned
int
uint
;
typedef
unsigned
long
ulong
;
#define uswap_16(x) \
((((x) & 0xff00) >> 8) | \
...
...
include/u-boot/crc.h
浏览文件 @
70bd39d7
...
...
@@ -8,6 +8,8 @@
#ifndef _UBOOT_CRC_H
#define _UBOOT_CRC_H
#include <compiler.h>
/* 'uint*' definitions */
/**
* crc8() - Calculate and return CRC-8 of the data
*
...
...
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