nand: arasan_nfc: Fixed NAND write issue

In commit 2453c695 ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0xFFFF and the same macro is used in nand write and so that getting
nand write error.
This patch reverted this macro to the 0xFFFF0000 and used
ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function
which is equal to 0xFFFF.
Signed-off-by: NVipul Kumar <vipulk@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

drivers/mtd/nand/arasan_nfc.c

@@ -86,7 +86,7 @@ struct arasan_nand_command_format {
 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK		0x70000000
 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT		28
 
-#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK		0xFFFF
+#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK		0xFFFF0000
 #define ARASAN_NAND_MEM_ADDR1_COL_MASK		0xFFFF
 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT	16
 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK		0xFF
@@ -796,7 +796,7 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
 	writel(reg_val, &arasan_nand_base->cmd_reg);
 
 	page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
-		ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
+		ARASAN_NAND_MEM_ADDR1_COL_MASK;
 	column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
 	writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
 	       &arasan_nand_base->memadr_reg1);