Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

MAINTAINERS

@@ -138,6 +138,10 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Alex Dubov <oakad@yahoo.com>
+
+	mpq101		MPC8548
+
 Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX

board/mercury/mpq101/Makefile

+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mercury/mpq101/law.c

+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO (set elsewhere) 512M
+ * 0xe000_0000     0xe000_ffff     CCSR    (set elsewhere) 1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+		LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/mercury/mpq101/mpq101.c

+/*
+ * (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init(void)
+{
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+int checkboard(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+	putc('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t fixed_sdram(void)
+{
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
+	} else {
+		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	}
+
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+
+	asm("sync;isync");
+	udelay(500);
+
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	asm("sync; isync");
+	udelay(500);
+
+	return ((phys_size_t)1) << CONFIG_SYS_SDRAM_SIZE_LOG;
+}
+
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+
+#endif

board/mercury/mpq101/tlb.c

+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000,
+		      CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);

board/mercury/mpq101/u-boot.lds

+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+#include <config.h>
+
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  /* To simplify mass deployment, environment precedes the monitor text in the
+   * same flash sector.
+   */
+  .ppcenv CONFIG_ENV_ADDR : { common/env_embedded.o (.ppcenv) }
+  .text      :
+  {
+    *(.text*)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg RESET_VECTOR_ADDRESS - 0xffc :
+  {
+    arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec RESET_VECTOR_ADDRESS :
+  {
+    KEEP(*(.resetvec))
+  } :text = 0xffff
+
+  . = RESET_VECTOR_ADDRESS + 0x4;
+
+  /*
+   * Make sure that the bss segment isn't linked at 0x0, otherwise its
+   * address won't be updated during relocation fixups.  Note that
+   * this is a temporary fix.  Code to dynamically the fixup the bss
+   * location will be added in the future.  When the bss relocation
+   * fixup code is present this workaround should be removed.
+   */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+  . |= 0x10;
+#endif
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}

boards.cfg

@@ -496,6 +496,7 @@ P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020,SPIFLASH
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
+mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M

include/configs/P1022DS.h

@@ -151,7 +151,7 @@
 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB | 0x6ff7)
 
 #define PIXIS_LBMAP_SWITCH	7
-#define PIXIS_LBMAP_MASK	0xE0
+#define PIXIS_LBMAP_MASK	0xF0
 #define PIXIS_LBMAP_ALTBANK	0x20
 
 #define CONFIG_SYS_INIT_RAM_LOCK

include/configs/mpq101.h

+/*
+ * Copyright 2011 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+# define CONFIG_PHYS_64BIT
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      /* BOOKE */
+#define CONFIG_E500       /* BOOKE e500 family */
+#define CONFIG_MPC85xx    /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    /* MPC8548 specific */
+#define CONFIG_MPQ101     /* MPQ101 board specific */
+
+#define CONFIG_SYS_SRIO   /* enable serial RapidIO */
+#define CONFIG_TSEC_ENET  /* tsec ethernet support */
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW    /* Use common FSL init code */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE   /* toggle L2 cache */
+#define CONFIG_BTB        /* toggle branch predition */
+
+#define CONFIG_PANIC_HANG
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_ADDR_MAP
+# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+
+#define CONFIG_SYS_CLK_FREQ      33000000 /* sysclk for MPC85xx */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_CCSRBAR_PHYS   0xfe0000000ull
+#else
+# define CONFIG_SYS_CCSRBAR_PHYS   CONFIG_SYS_CCSRBAR
+#endif
+
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE        0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* Fixed 512MB DDR2 parameters */
+#define CONFIG_SYS_SDRAM_SIZE_LOG    29 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS      0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG    0x80014102
+#define CONFIG_SYS_DDR_TIMING_3      0x00010000
+#define CONFIG_SYS_DDR_TIMING_0      0x00260802
+#define CONFIG_SYS_DDR_TIMING_1      0x5c47a432
+#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
+#define CONFIG_SYS_DDR_TIMING_2      0x03984cce
+#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
+#define CONFIG_SYS_DDR_MODE_1        0x00400442
+#define CONFIG_SYS_DDR_MODE_1_PERF   0x00480432
+#define CONFIG_SYS_DDR_MODE_2        0x00000000
+#define CONFIG_SYS_DDR_MODE_2_PERF   0x00000000
+#define CONFIG_SYS_DDR_INTERVAL      0x08200100
+#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
+#define CONFIG_SYS_DDR_CLK_CTRL      0x03800000
+#define CONFIG_SYS_DDR_CONTROL       0xc3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2      0x04400000
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START     0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END       0x0ffffffc
+
+/*
+ * RAM definitions
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR   0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE   0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+				    - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN     (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN      (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 128M, using the CFI driver.
+ */
+#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
+#else
+# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xf8001801 */
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+			       | BR_PS_32 | BR_V)
+
+/* 0xf8006ff7 */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
+			       | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+			       | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
+			       | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FLASH_SHOW_PROGRESS     45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      512  /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+/*
+ * Environment parameters
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_USE_PPCENV
+#define ENV_IS_EMBEDDED
+#define CONFIG_ENV_SECT_SIZE 0x40000   /* 256K */
+#define CONFIG_ENV_SIZE      0x800
+
+/* Environment at the start of flash sector, before text. */
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_TEXT_BASE    0xfffc0800
+#define CONFIG_SYS_LDSCRIPT     "board/mercury/mpq101/u-boot.lds"
+
+/*
+ * Cypress CY7C67200 USB controller on the Local Bus.
+ * Not supported by u-boot at present.
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
+
+#ifdef CONFIG_PHYS_64BIT
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
+#else
+# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
+#endif
+
+/* 0xf0001001 */
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
+			       | BR_PS_16 | BR_V)
+
+/* fffff002 */
+#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
+			       | OR_GPCM_BCTLD | OR_GPCM_EHTR)
+
+/*
+ * Serial Ports
+ */
+#define CONFIG_CONS_INDEX           2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE   {300, 600, 1200, 2400, 4800, 9600, \
+				     19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1     (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2     (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C buses and peripherals
+ */
+#define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C        /* I2C with hardware support*/
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED   400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE   0x7f
+#define CONFIG_SYS_I2C_OFFSET  0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C RTC - M41T81 */
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR     0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* I2C EEPROM - 24C256 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR            0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
+#define CONFIG_SYS_EEPROM_BUS_NUM             1
+
+/*
+ * RapidIO MMU
+ */
+#ifdef CONFIG_SYS_SRIO
+# define CONFIG_SRIO1
+# define CONFIG_SYS_SRIO1_MEM_VIRT  0xc0000000
+# define CONFIG_SYS_SRIO1_MEM_SIZE  0x20000000 /* 512M */
+
+# ifdef CONFIG_PHYS_64BIT
+#  define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
+# else
+#  define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
+# endif
+#endif
+
+/*
+ * Ethernet
+ */
+#ifdef CONFIG_TSEC_ENET
+
+# ifndef CONFIG_NET_MULTI
+#  define CONFIG_NET_MULTI
+# endif
+
+# define CONFIG_MII                /* MII PHY management */
+# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+
+# define CONFIG_TSEC1
+# define CONFIG_TSEC1_NAME       "eTSEC0"
+# define TSEC1_PHY_ADDR          0x10
+# define TSEC1_PHYIDX            0
+# define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC2
+# define CONFIG_TSEC2_NAME       "eTSEC1"
+# define TSEC2_PHY_ADDR          0x11
+# define TSEC2_PHYIDX            0
+# define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC3
+# define CONFIG_TSEC3_NAME       "eTSEC2"
+# define TSEC3_PHY_ADDR          0x12
+# define TSEC3_PHYIDX            0
+# define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+# define CONFIG_TSEC4
+# define CONFIG_TSEC4_NAME       "eTSEC3"
+# define TSEC4_PHY_ADDR          0x13
+# define TSEC4_PHYIDX            0
+# define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+# define CONFIG_ETHPRIME         "eTSEC0"
+# define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_FIT         /* new uImage format support */
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+# define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
+#endif
+
+#define CONFIG_LOADS_ECHO            /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+#define CONFIG_SYS_LONGHELP          /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING       /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE         /* add autocompletion support */
+
+#define CONFIG_SYS_LOAD_ADDR         0x2000000    /* default load address */
+#define CONFIG_SYS_PROMPT            "MPQ-101=> " /* Monitor Command Prompt */
+
+/* Console I/O Buffer Size */
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024
+#else
+# define CONFIG_SYS_CBSIZE 256
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+# define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Basic Environment Configuration
+ */
+#define CONFIG_BAUDRATE  115200
+#define CONFIG_BOOTDELAY 5            /* -1 disables auto-boot */
+
+/*default location for tftp and bootm*/
+#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR
+
+#endif /* __CONFIG_H */