ARM: DRA7: Change configuration to prevent DDR reset control from EMIF

DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF controller should not be the master of the reset
signal and an external entity might be in control of things.

The default configuration of Linux on TI evms involve not powering off
the voltage rails (due to various reasons including reliability concerns)
and must not allow DDR reset to be controlled by EMIF. On platforms
where external entity might control the reset signal, this configuration
will be a "dont care".

Fixes: 536d8747 ("ARM: DRA7: Update DDR IO registers")
Tested-by: NKeerthy <j-keerthy@ti.com>
Acked-by: NBrad Griffis <bgriffis@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

arch/arm/cpu/armv7/omap5/hw_data.c

@@ -602,8 +602,8 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 	.ctrl_ddrio_0 = 0x00094A40,
 	.ctrl_ddrio_1 = 0x04A52000,
 	.ctrl_ddrio_2 = 0x84210000,
-	.ctrl_emif_sdram_config_ext = 0x0001C127,
-	.ctrl_emif_sdram_config_ext_final = 0x0001C127,
+	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
+	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
 	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };
 
@@ -614,8 +614,8 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
 	.ctrl_ddrio_0 = 0x00094A40,
 	.ctrl_ddrio_1 = 0x04A52000,
 	.ctrl_ddrio_2 = 0x84210000,
-	.ctrl_emif_sdram_config_ext = 0x0001C127,
-	.ctrl_emif_sdram_config_ext_final = 0x0001C127,
+	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
+	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
 	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };