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65994d04
编写于
3月 05, 2015
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge
git://git.denx.de/u-boot-socfpga
上级
65f3151f
053ae0a3
变更
18
隐藏空白更改
内联
并排
Showing
18 changed file
with
1371 addition
and
149 deletion
+1371
-149
arch/arm/Kconfig
arch/arm/Kconfig
+5
-0
arch/arm/dts/Makefile
arch/arm/dts/Makefile
+4
-1
arch/arm/dts/socfpga_arria5.dtsi
arch/arm/dts/socfpga_arria5.dtsi
+34
-0
arch/arm/dts/socfpga_arria5_socdk.dts
arch/arm/dts/socfpga_arria5_socdk.dts
+74
-0
arch/arm/dts/socfpga_cyclone5_socdk.dts
arch/arm/dts/socfpga_cyclone5_socdk.dts
+79
-0
board/altera/socfpga/Kconfig
board/altera/socfpga/Kconfig
+16
-0
board/altera/socfpga/Makefile
board/altera/socfpga/Makefile
+1
-1
board/altera/socfpga/iocsr_config.c
board/altera/socfpga/iocsr_config.c
+688
-0
board/altera/socfpga/iocsr_config.h
board/altera/socfpga/iocsr_config.h
+13
-4
board/altera/socfpga/pinmux_config.c
board/altera/socfpga/pinmux_config.c
+309
-94
board/altera/socfpga/pinmux_config.h
board/altera/socfpga/pinmux_config.h
+7
-7
board/altera/socfpga/pll_config.h
board/altera/socfpga/pll_config.h
+11
-23
board/altera/socfpga/socfpga.c
board/altera/socfpga/socfpga.c
+0
-17
configs/socfpga_arria5_defconfig
configs/socfpga_arria5_defconfig
+8
-0
configs/socfpga_cyclone5_defconfig
configs/socfpga_cyclone5_defconfig
+5
-0
include/configs/socfpga_arria5.h
include/configs/socfpga_arria5.h
+107
-0
include/configs/socfpga_common.h
include/configs/socfpga_common.h
+1
-2
include/configs/socfpga_cyclone5.h
include/configs/socfpga_cyclone5.h
+9
-0
未找到文件。
arch/arm/Kconfig
浏览文件 @
65994d04
...
...
@@ -584,6 +584,11 @@ config TARGET_CM_FX6
select CPU_V7
select SUPPORT_SPL
config TARGET_SOCFPGA_ARRIA5
bool "Support socfpga_arria5"
select CPU_V7
select SUPPORT_SPL
config TARGET_SOCFPGA_CYCLONE5
bool "Support socfpga_cyclone5"
select CPU_V7
...
...
arch/arm/dts/Makefile
浏览文件 @
65994d04
...
...
@@ -49,7 +49,10 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc770-xm013.dtb
dtb-$(CONFIG_AM33XX)
+=
am335x-boneblack.dtb
dtb-$(CONFIG_SOCFPGA)
+=
socfpga_cyclone5_socrates.dtb
dtb-$(CONFIG_SOCFPGA)
+=
\
socfpga_arria5_socdk.dtb
\
socfpga_cyclone5_socdk.dtb
\
socfpga_cyclone5_socrates.dtb
targets
+=
$
(
dtb-y
)
...
...
arch/arm/dts/socfpga_arria5.dtsi
0 → 100644
浏览文件 @
65994d04
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/* First 4KB has trampoline code for secondary cores. */
/memreserve/ 0x00000000 0x0001000;
#include "socfpga.dtsi"
/ {
soc {
clkmgr@ffd04000 {
clocks {
osc1 {
clock-frequency = <25000000>;
};
};
};
mmc0: dwmmc0@ff704000 {
num-slots = <1>;
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
};
sysmgr@ffd08000 {
cpu1-start-addr = <0xffd080c4>;
};
};
};
arch/arm/dts/socfpga_arria5_socdk.dts
0 → 100644
浏览文件 @
65994d04
/*
*
Copyright
(
C
)
2013
Altera
Corporation
<
www
.
altera
.
com
>
*
*
SPDX
-
License
-
Identifier
:
GPL
-
2.0
+
*/
#
include
"socfpga_arria5.dtsi"
/
{
model
=
"Altera SOCFPGA Arria V SoC Development Kit"
;
compatible
=
"altr,socfpga-arria5"
,
"altr,socfpga"
;
chosen
{
bootargs
=
"console=ttyS0,115200"
;
};
memory
{
name
=
"memory"
;
device_type
=
"memory"
;
reg
=
<
0x0
0x40000000
>;
/*
1
GB
*/
};
aliases
{
/*
this
allow
the
ethaddr
uboot
environmnet
variable
contents
*
to
be
added
to
the
gmac1
device
tree
blob
.
*/
ethernet0
=
&
gmac1
;
};
regulator_3_3v
:
3
-
3
-
v
-
regulator
{
compatible
=
"regulator-fixed"
;
regulator
-
name
=
"3.3V"
;
regulator
-
min
-
microvolt
=
<
3300000
>;
regulator
-
max
-
microvolt
=
<
3300000
>;
};
};
&
gmac1
{
status
=
"okay"
;
phy
-
mode
=
"rgmii"
;
rxd0
-
skew
-
ps
=
<
0
>;
rxd1
-
skew
-
ps
=
<
0
>;
rxd2
-
skew
-
ps
=
<
0
>;
rxd3
-
skew
-
ps
=
<
0
>;
txen
-
skew
-
ps
=
<
0
>;
txc
-
skew
-
ps
=
<
2600
>;
rxdv
-
skew
-
ps
=
<
0
>;
rxc
-
skew
-
ps
=
<
2000
>;
};
&
i2c0
{
status
=
"okay"
;
eeprom
@
51
{
compatible
=
"atmel,24c32"
;
reg
=
<
0x51
>;
pagesize
=
<
32
>;
};
rtc
@
68
{
compatible
=
"dallas,ds1339"
;
reg
=
<
0x68
>;
};
};
&
mmc0
{
vmmc
-
supply
=
<&
regulator_3_3v
>;
vqmmc
-
supply
=
<&
regulator_3_3v
>;
};
&
usb1
{
status
=
"okay"
;
};
arch/arm/dts/socfpga_cyclone5_socdk.dts
0 → 100644
浏览文件 @
65994d04
/*
*
Copyright
(
C
)
2012
Altera
Corporation
<
www
.
altera
.
com
>
*
*
SPDX
-
License
-
Identifier
:
GPL
-
2.0
+
*/
#
include
"socfpga_cyclone5.dtsi"
/
{
model
=
"Altera SOCFPGA Cyclone V SoC Development Kit"
;
compatible
=
"altr,socfpga-cyclone5"
,
"altr,socfpga"
;
chosen
{
bootargs
=
"console=ttyS0,115200"
;
};
memory
{
name
=
"memory"
;
device_type
=
"memory"
;
reg
=
<
0x0
0x40000000
>;
/*
1
GB
*/
};
aliases
{
/*
this
allow
the
ethaddr
uboot
environmnet
variable
contents
*
to
be
added
to
the
gmac1
device
tree
blob
.
*/
ethernet0
=
&
gmac1
;
};
regulator_3_3v
:
3
-
3
-
v
-
regulator
{
compatible
=
"regulator-fixed"
;
regulator
-
name
=
"3.3V"
;
regulator
-
min
-
microvolt
=
<
3300000
>;
regulator
-
max
-
microvolt
=
<
3300000
>;
};
};
&
gmac1
{
status
=
"okay"
;
phy
-
mode
=
"rgmii"
;
rxd0
-
skew
-
ps
=
<
0
>;
rxd1
-
skew
-
ps
=
<
0
>;
rxd2
-
skew
-
ps
=
<
0
>;
rxd3
-
skew
-
ps
=
<
0
>;
txen
-
skew
-
ps
=
<
0
>;
txc
-
skew
-
ps
=
<
2600
>;
rxdv
-
skew
-
ps
=
<
0
>;
rxc
-
skew
-
ps
=
<
2000
>;
};
&
gpio1
{
status
=
"okay"
;
};
&
i2c0
{
status
=
"okay"
;
eeprom
@
51
{
compatible
=
"atmel,24c32"
;
reg
=
<
0x51
>;
pagesize
=
<
32
>;
};
rtc
@
68
{
compatible
=
"dallas,ds1339"
;
reg
=
<
0x68
>;
};
};
&
mmc0
{
cd
-
gpios
=
<&
portb
18
0
>;
vmmc
-
supply
=
<&
regulator_3_3v
>;
vqmmc
-
supply
=
<&
regulator_3_3v
>;
};
&
usb1
{
status
=
"okay"
;
};
board/altera/socfpga/Kconfig
浏览文件 @
65994d04
...
...
@@ -13,3 +13,19 @@ config SYS_CONFIG_NAME
default "socfpga_cyclone5"
endif
if TARGET_SOCFPGA_ARRIA5
config SYS_BOARD
default "socfpga"
config SYS_VENDOR
default "altera"
config SYS_SOC
default "socfpga"
config SYS_CONFIG_NAME
default "socfpga_arria5"
endif
board/altera/socfpga/Makefile
浏览文件 @
65994d04
...
...
@@ -6,5 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y
:=
socfpga
_cyclone5
.o
obj-y
:=
socfpga.o
obj-$(CONFIG_SPL_BUILD)
+=
pinmux_config.o iocsr_config.o
board/altera/socfpga/iocsr_config.c
浏览文件 @
65994d04
...
...
@@ -8,6 +8,7 @@
#include <iocsr_config.h>
#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
const
unsigned
long
iocsr_scan_chain0_table
[((
CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
/
32
)
+
1
)]
=
{
0x00000000
,
...
...
@@ -655,3 +656,690 @@ const unsigned long iocsr_scan_chain3_table[((
0x0000001F
,
0x00004100
,
};
#endif
/* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
const
unsigned
long
iocsr_scan_chain0_table
[((
CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
/
32
)
+
1
)]
=
{
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00008000
,
0x00060180
,
0x18060000
,
0x18000060
,
0x00018060
,
0x06018060
,
0x00004000
,
0x0C0300C0
,
0x0C030000
,
0x00000030
,
0x00000000
,
0x00000000
,
0x00002000
,
0x00000000
,
0x00000000
,
0x06000000
,
0x00006018
,
0x01806018
,
0x00001000
,
0x0000C030
,
0x04000000
,
0x03000000
,
0x0000300C
,
0x00000000
,
0x00000800
,
0x00006018
,
0x01806000
,
0x01800000
,
0x00000006
,
0x00001806
,
0x00000400
,
0x0000300C
,
0x00C03000
,
0x00C00000
,
0x00000003
,
0x00000C03
,
0x00000200
,
};
const
unsigned
long
iocsr_scan_chain1_table
[((
CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH
/
32
)
+
1
)]
=
{
0x00100000
,
0x300C0000
,
0x300000C0
,
0x000000C0
,
0x000300C0
,
0x00008000
,
0x00060180
,
0x18060000
,
0x18000000
,
0x00000060
,
0x00018060
,
0x00004000
,
0x000300C0
,
0x10000000
,
0x0C000000
,
0x00000030
,
0x0000C030
,
0x00002000
,
0x06018060
,
0x06018000
,
0x01FE0000
,
0xF8000000
,
0x00000007
,
0x00001000
,
0x0000C030
,
0x0300C000
,
0x03000000
,
0x0000300C
,
0x0000300C
,
0x00000800
,
0x00006018
,
0x01806000
,
0x01800000
,
0x00000006
,
0x00002000
,
0x00000400
,
0x0000300C
,
0x01000000
,
0x00000000
,
0x00000004
,
0x00000C03
,
0x00000200
,
0x00001806
,
0x00800000
,
0x00000000
,
0x00000002
,
0x00000800
,
0x00000100
,
0x00001000
,
0x00400000
,
0xC0300000
,
0x00000000
,
0x00000400
,
0x00000080
,
};
const
unsigned
long
iocsr_scan_chain2_table
[((
CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH
/
32
)
+
1
)]
=
{
0x00100000
,
0x40000000
,
0x00000000
,
0x00000100
,
0x00040000
,
0x00008000
,
0x18060180
,
0x20000000
,
0x00000000
,
0x00000080
,
0x00020000
,
0x00004000
,
0x00040000
,
0x10000000
,
0x00000000
,
0x00000000
,
0x00010000
,
0x00002000
,
0x10038060
,
0x00000000
,
0x00000000
,
0x00000020
,
0x01806018
,
0x00001000
,
0x00010000
,
0x04000000
,
0x03000000
,
0x0000801C
,
0x00004000
,
0x00000800
,
0x01806018
,
0x02000000
,
0x00000000
,
0x00000008
,
0x00002000
,
0x00000400
,
0x00C0300C
,
0x00C03000
,
0x00C00003
,
0x00000C03
,
0x00300C03
,
0x00000200
,
0x00601806
,
0x80601800
,
0x80600001
,
0x80000601
,
0x00180601
,
0x00000100
,
};
const
unsigned
long
iocsr_scan_chain3_table
[((
CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
/
32
)
+
1
)]
=
{
0x2C820D80
,
0x082000FF
,
0x0A804001
,
0x07900000
,
0x08020000
,
0x00100000
,
0x0A800000
,
0x07900000
,
0x08020000
,
0x00100000
,
0xC8800000
,
0x00003001
,
0x00C00722
,
0x00000000
,
0x00000021
,
0x82000004
,
0x05400000
,
0x03C80000
,
0x04010000
,
0x00080000
,
0x05400000
,
0x03C80000
,
0x05400000
,
0x03C80000
,
0xE4400000
,
0x00001800
,
0x00600391
,
0x800E4400
,
0x00000001
,
0x40000002
,
0x02A00000
,
0x01E40000
,
0x02A00000
,
0x01E40000
,
0x02A00000
,
0x01E40000
,
0x02A00000
,
0x01E40000
,
0x72200000
,
0x80000C00
,
0x003001C8
,
0xC0072200
,
0x1C880000
,
0x20000300
,
0x00040000
,
0x50670000
,
0x00000050
,
0x24590000
,
0x00001000
,
0xA0000034
,
0x0D000001
,
0x906808A2
,
0xA2834024
,
0x05141A00
,
0x808A20D0
,
0x34024906
,
0x01A00A28
,
0xA20D0000
,
0x24906808
,
0x00A28340
,
0xD000001A
,
0x06808A20
,
0x10040000
,
0x00200000
,
0x10040000
,
0x00200000
,
0x15000000
,
0x0F200000
,
0x15000000
,
0x0F200000
,
0x01FE0000
,
0x00000000
,
0x01800E44
,
0x00391000
,
0x007F8006
,
0x00000000
,
0x0A800001
,
0x07900000
,
0x0A800000
,
0x07900000
,
0x0A800000
,
0x07900000
,
0x08020000
,
0x00100000
,
0xC8800000
,
0x00003001
,
0x00C00722
,
0x00000FF0
,
0x72200000
,
0x80000C00
,
0x05400000
,
0x02480000
,
0x04000000
,
0x00080000
,
0x05400000
,
0x03C80000
,
0x05400000
,
0x03C80000
,
0x6A1C0000
,
0x00001800
,
0x00600391
,
0x800E4400
,
0x1A870001
,
0x40000600
,
0x02A00040
,
0x01E40000
,
0x02A00000
,
0x01E40000
,
0x02A00000
,
0x01E40000
,
0x02A00000
,
0x01E40000
,
0x72200000
,
0x80000C00
,
0x003001C8
,
0xC0072200
,
0x1C880000
,
0x20000300
,
0x00040000
,
0x50670000
,
0x00000050
,
0x24590000
,
0x00001000
,
0xA0000034
,
0x0D000001
,
0x906808A2
,
0xA2834024
,
0x05141A00
,
0x808A20D0
,
0x34024906
,
0x01A00040
,
0xA20D0002
,
0x24906808
,
0x00A28340
,
0xD005141A
,
0x06808A20
,
0x10040000
,
0x00200000
,
0x10040000
,
0x00200000
,
0x15000000
,
0x0F200000
,
0x15000000
,
0x0F200000
,
0x01FE0000
,
0x00000000
,
0x01800E44
,
0x00391000
,
0x007F8006
,
0x00000000
,
0x99300001
,
0x34343400
,
0xAA0D4000
,
0x01C3A810
,
0xAA0D4000
,
0x01C3A808
,
0xAA0D4000
,
0x01C3A810
,
0x00040100
,
0x00000800
,
0x00000000
,
0x00001208
,
0x00482000
,
0x01000000
,
0x00000000
,
0x00410482
,
0x0006A000
,
0x0001B400
,
0x00020000
,
0x00000400
,
0x0002A000
,
0x0001E400
,
0x5506A000
,
0x00E1D404
,
0x00000000
,
0xC880090C
,
0x00003001
,
0x90400000
,
0x00000000
,
0x2020C243
,
0x2A835000
,
0x0070EA04
,
0x2A835000
,
0x0070EA02
,
0x2A835000
,
0x0070EA04
,
0x00010040
,
0x00000200
,
0x00000000
,
0x00000482
,
0x00120800
,
0x00002000
,
0x80000000
,
0x00104120
,
0x00000200
,
0xAC055F80
,
0xFFFFFFFF
,
0x14F3690D
,
0x1A041414
,
0x00D00000
,
0x14864000
,
0x59647A05
,
0xBA28A3D8
,
0xF511451E
,
0x0341D348
,
0x821A0000
,
0x0000D000
,
0x04510680
,
0xD859647A
,
0x1EBA28A3
,
0x48F51145
,
0x000341D3
,
0x00080200
,
0x00001000
,
0x00080200
,
0x00001000
,
0x000A8000
,
0x00075000
,
0x541A8000
,
0x03875011
,
0x10000000
,
0x00000000
,
0x0080C000
,
0x41000000
,
0x00003FC2
,
0x00820000
,
0xAA0D4000
,
0x01C3A810
,
0xAA0D4000
,
0x01C3A808
,
0xAA0D4000
,
0x01C3A810
,
0x00040100
,
0x00000800
,
0x00000000
,
0x00001208
,
0x00482000
,
0x00008000
,
0x00000000
,
0x00410482
,
0x0006A000
,
0x0001B400
,
0x00020000
,
0x00000400
,
0x00020080
,
0x00000400
,
0x5506A000
,
0x00E1D404
,
0x00000000
,
0x0000090C
,
0x00000010
,
0x90400000
,
0x00000000
,
0x2020C243
,
0x2A835000
,
0x0070EA04
,
0x2A835000
,
0x0070EA02
,
0x2A835000
,
0x0070EA04
,
0x00015000
,
0x0000F200
,
0x00000000
,
0x00000482
,
0x00120800
,
0x00600391
,
0x80000000
,
0x00104120
,
0x00000200
,
0xAC055F80
,
0xFFFFFFFF
,
0x14F3690D
,
0x1A041414
,
0x00D00000
,
0x14864000
,
0x59647A05
,
0xBA28A3D8
,
0xF511451E
,
0x8341D348
,
0x821A0124
,
0x0000D000
,
0x00000680
,
0xD859647A
,
0x1EBA28A3
,
0x48F51145
,
0x000341D3
,
0x00080200
,
0x00001000
,
0x00080200
,
0x00001000
,
0x000A8000
,
0x00075000
,
0x541A8000
,
0x03875011
,
0x10000000
,
0x00000000
,
0x0080C000
,
0x41000000
,
0x04000002
,
0x00820000
,
0xAA0D4000
,
0x01C3A810
,
0xAA0D4000
,
0x01C3A808
,
0xAA0D4000
,
0x01C3A810
,
0x00040100
,
0x00000800
,
0x00000000
,
0x00001208
,
0x00482000
,
0x00008000
,
0x00000000
,
0x00410482
,
0x0006A000
,
0x0001B400
,
0x00020000
,
0x00000400
,
0x0002A000
,
0x0001E400
,
0x5506A000
,
0x00E1D404
,
0x00000000
,
0xC880090C
,
0x00003001
,
0x90400000
,
0x00000000
,
0x2020C243
,
0x2A835000
,
0x0070EA04
,
0x2A835000
,
0x0070EA02
,
0x2A835000
,
0x0070EA04
,
0x00010040
,
0x00000200
,
0x00000000
,
0x00000482
,
0x00120800
,
0x00002000
,
0x80000000
,
0x00104120
,
0x00000200
,
0xAC055F80
,
0xFFFFFFFF
,
0x14F3690D
,
0x1A041414
,
0x00D00000
,
0x14864000
,
0x59647A05
,
0xBA28A3D8
,
0xF511451E
,
0x0341D348
,
0x821A0000
,
0x0000D000
,
0x00000680
,
0xD859647A
,
0x1EBA28A3
,
0x48F51145
,
0x000341D3
,
0x00080200
,
0x00001000
,
0x00080200
,
0x00001000
,
0x000A8000
,
0x00075000
,
0x541A8000
,
0x03875011
,
0x10000000
,
0x00000000
,
0x0080C000
,
0x41000000
,
0x04000002
,
0x00820000
,
0xAA0D4000
,
0x01C3A810
,
0xAA0D4000
,
0x01C3A808
,
0xAA0D4000
,
0x01C3A810
,
0x00040100
,
0x00000800
,
0x00000000
,
0x00001208
,
0x00482000
,
0x00008000
,
0x00000000
,
0x00410482
,
0x0006A000
,
0x0001B400
,
0x00020000
,
0x00000400
,
0x00020080
,
0x00000400
,
0x5506A000
,
0x00E1D404
,
0x00000000
,
0x0000090C
,
0x00000010
,
0x90400000
,
0x00000000
,
0x2020C243
,
0x2A835000
,
0x0070EA04
,
0x2A835000
,
0x0070EA02
,
0x2A835000
,
0x0070EA04
,
0x00010040
,
0x00000200
,
0x00000000
,
0x00000482
,
0x00120800
,
0x00400000
,
0x80000000
,
0x00104120
,
0x00000200
,
0xAC055F80
,
0xFFFFFFFF
,
0x14F1690D
,
0x1A041414
,
0x00D00000
,
0x14864000
,
0x59647A05
,
0xBA28A3D8
,
0xF511451E
,
0x0341D348
,
0x821A0000
,
0x0000D000
,
0x00000680
,
0xD859647A
,
0x1EBA28A3
,
0x48F51145
,
0x000341D3
,
0x00080200
,
0x00001000
,
0x00080200
,
0x00001000
,
0x000A8000
,
0x00075000
,
0x541A8000
,
0x03875011
,
0x10000000
,
0x00000000
,
0x0080C000
,
0x41000000
,
0x04000002
,
0x00820000
,
0x00481800
,
0x001A1A1A
,
0x085506A0
,
0x0000E1D4
,
0x045506A0
,
0x0000E1D4
,
0x085506A0
,
0x8000E1D4
,
0x00000200
,
0x00000004
,
0x04000000
,
0x00000009
,
0x00002410
,
0x00000040
,
0x41000000
,
0x00002082
,
0x00000350
,
0x000000DA
,
0x00000100
,
0x40000002
,
0x00000100
,
0x00000002
,
0x022A8350
,
0x000070EA
,
0x86000000
,
0x08000004
,
0x00000000
,
0x00482000
,
0x21800000
,
0x00101061
,
0x021541A8
,
0x00003875
,
0x011541A8
,
0x00003875
,
0x021541A8
,
0x20003875
,
0x00000080
,
0x00000001
,
0x41000000
,
0x00000002
,
0x00FF0904
,
0x00000000
,
0x90400000
,
0x00000820
,
0xC0000001
,
0xFFD602AF
,
0x86FFFFFF
,
0x0A0A78B4
,
0x000D020A
,
0x00006800
,
0x028A4320
,
0xEC2CB23D
,
0x8F5D1451
,
0xA47A88A2
,
0x0001A0E9
,
0x00410D00
,
0x40000068
,
0x3D000003
,
0x51EC2CB2
,
0xA28F5D14
,
0xE9A47A88
,
0x000001A0
,
0x00000401
,
0x00000008
,
0x00000401
,
0x00000008
,
0x00000540
,
0x000003A8
,
0x08AA0D40
,
0x8001C3A8
,
0x0000007F
,
0x00000000
,
0x00004060
,
0xE1208000
,
0x0000001F
,
0x00004100
,
};
#endif
/* CONFIG_TARGET_SOCFPGA_ARRIA5 */
board/altera/socfpga/iocsr_config.h
浏览文件 @
65994d04
...
...
@@ -9,9 +9,18 @@
#ifndef _PRELOADER_IOCSR_CONFIG_H_
#define _PRELOADER_IOCSR_CONFIG_H_
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
#endif
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337)
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528)
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
#endif
#endif
/*_PRELOADER_IOCSR_CONFIG_H_*/
board/altera/socfpga/pinmux_config.c
浏览文件 @
65994d04
...
...
@@ -2,102 +2,103 @@
#include "pinmux_config.h"
#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
/* pin mux configuration data */
unsigned
long
sys_mgr_init_table
[
CONFIG_HPS_PINMUX_NUM
]
=
{
0
,
/* EMACIO0 - Unused
*/
2
,
/* EMACIO1 - USB
*/
2
,
/* EMACIO2 - USB
*/
2
,
/* EMACIO3 - USB
*/
2
,
/* EMACIO4 - USB
*/
2
,
/* EMACIO5 - USB
*/
2
,
/* EMACIO6 - USB
*/
2
,
/* EMACIO7 - USB
*/
2
,
/* EMACIO8 - USB
*/
0
,
/* EMACIO9 - Unused
*/
2
,
/* EMACIO10 - USB
*/
2
,
/* EMACIO11 - USB
*/
2
,
/* EMACIO12 - USB
*/
2
,
/* EMACIO13 - USB
*/
0
,
/* EMACIO14
- N/A
*/
0
,
/* EMACIO15
- N/A
*/
0
,
/* EMACIO16
- N/A
*/
0
,
/* EMACIO17
- N/A
*/
0
,
/* EMACIO18
- N/A
*/
0
,
/* EMACIO19
- N/A
*/
3
,
/* FLASHIO0
- SDMMC
*/
3
,
/* FLASHIO1 - SDMMC
*/
3
,
/* FLASHIO2
- SDMMC
*/
3
,
/* FLASHIO3
- SDMMC
*/
0
,
/* FLASHIO4 - SDMMC
*/
0
,
/* FLASHIO5 - SDMMC
*/
0
,
/* FLASHIO6 - SDMMC
*/
0
,
/* FLASHIO7 - SDMMC
*/
0
,
/* FLASHIO8
- SDMMC
*/
3
,
/* FLASHIO9
- SDMMC
*/
3
,
/* FLASHIO10
- SDMMC
*/
3
,
/* FLASHIO11
- SDMMC
*/
3
,
/* GENERALIO0 - TRACE
*/
3
,
/* GENERALIO1 - TRACE
*/
3
,
/* GENERALIO2 - TRACE
*/
3
,
/* GENERALIO3 - TRACE
*/
3
,
/* GENERALIO4 - TRACE
*/
3
,
/* GENERALIO5 - TRACE
*/
3
,
/* GENERALIO6 - TRACE
*/
3
,
/* GENERALIO7 - TRACE
*/
3
,
/* GENERALIO8 - TRACE
*/
3
,
/* GENERALIO9 - SPIM0
*/
3
,
/* GENERALIO10 - SPIM
0 */
3
,
/* GENERALIO11 - SPIM0
*/
3
,
/* GENERALIO12 - SPIM0
*/
2
,
/* GENERALIO13
- CAN0
*/
2
,
/* GENERALIO14
- CAN0
*/
3
,
/* GENERALIO15 - I2C0
*/
3
,
/* GENERALIO16 - I2C0
*/
2
,
/* GENERALIO17 - UART0
*/
2
,
/* GENERALIO18 - UART0
*/
0
,
/* GENERALIO19
- N/A
*/
0
,
/* GENERALIO20
- N/A
*/
0
,
/* GENERALIO21
- N/A
*/
0
,
/* GENERALIO22
- N/A
*/
0
,
/* GENERALIO23
- N/A
*/
0
,
/* GENERALIO24
- N/A
*/
0
,
/* GENERALIO25
- N/A
*/
0
,
/* GENERALIO26
- N/A
*/
0
,
/* GENERALIO27
- N/A
*/
0
,
/* GENERALIO28
- N/A
*/
0
,
/* GENERALIO29
- N/A
*/
0
,
/* GENERALIO30
- N/A
*/
0
,
/* GENERALIO31
- N/A
*/
2
,
/* MIXED1IO0 - EMAC
*/
2
,
/* MIXED1IO1 - EMAC
*/
2
,
/* MIXED1IO2 - EMAC
*/
2
,
/* MIXED1IO3 - EMAC
*/
2
,
/* MIXED1IO4 - EMAC
*/
2
,
/* MIXED1IO5 - EMAC
*/
2
,
/* MIXED1IO6 - EMAC
*/
2
,
/* MIXED1IO7 - EMAC
*/
2
,
/* MIXED1IO8 - EMAC
*/
2
,
/* MIXED1IO9 - EMAC
*/
2
,
/* MIXED1IO10 - EMAC
*/
2
,
/* MIXED1IO11 - EMAC
*/
2
,
/* MIXED1IO12 - EMAC
*/
2
,
/* MIXED1IO13 - EMAC
*/
0
,
/* MIXED1IO14
- Unused
*/
3
,
/* MIXED1IO15 - QSPI
*/
3
,
/* MIXED1IO16 - QSPI
*/
3
,
/* MIXED1IO17 - QSPI
*/
3
,
/* MIXED1IO18 - QSPI
*/
3
,
/* MIXED1IO19 - QSPI
*/
3
,
/* MIXED1IO20 - QSPI
*/
0
,
/* MIXED1IO21
- GPIO
*/
0
,
/* MIXED2IO0
- N/A
*/
0
,
/* MIXED2IO1
- N/A
*/
0
,
/* MIXED2IO2
- N/A
*/
0
,
/* MIXED2IO3
- N/A
*/
0
,
/* MIXED2IO4
- N/A
*/
0
,
/* MIXED2IO5
- N/A
*/
0
,
/* MIXED2IO6
- N/A
*/
0
,
/* MIXED2IO7
- N/A
*/
3
,
/* EMACIO0
*/
3
,
/* EMACIO1
*/
3
,
/* EMACIO2
*/
3
,
/* EMACIO3
*/
3
,
/* EMACIO4
*/
3
,
/* EMACIO5
*/
3
,
/* EMACIO6
*/
3
,
/* EMACIO7
*/
3
,
/* EMACIO8
*/
3
,
/* EMACIO9
*/
3
,
/* EMACIO10
*/
3
,
/* EMACIO11
*/
3
,
/* EMACIO12
*/
3
,
/* EMACIO13
*/
0
,
/* EMACIO14 */
0
,
/* EMACIO15 */
0
,
/* EMACIO16 */
0
,
/* EMACIO17 */
0
,
/* EMACIO18 */
0
,
/* EMACIO19 */
3
,
/* FLASHIO0 */
0
,
/* FLASHIO1
*/
3
,
/* FLASHIO2 */
3
,
/* FLASHIO3 */
3
,
/* FLASHIO4
*/
3
,
/* FLASHIO5
*/
3
,
/* FLASHIO6
*/
3
,
/* FLASHIO7
*/
0
,
/* FLASHIO8 */
3
,
/* FLASHIO9 */
3
,
/* FLASHIO10 */
3
,
/* FLASHIO11 */
0
,
/* GENERALIO0
*/
1
,
/* GENERALIO1
*/
1
,
/* GENERALIO2
*/
0
,
/* GENERALIO3
*/
0
,
/* GENERALIO4
*/
1
,
/* GENERALIO5
*/
1
,
/* GENERALIO6
*/
1
,
/* GENERALIO7
*/
1
,
/* GENERALIO8
*/
0
,
/* GENERALIO9
*/
0
,
/* GENERALIO1
0 */
0
,
/* GENERALIO11
*/
0
,
/* GENERALIO12
*/
2
,
/* GENERALIO13 */
2
,
/* GENERALIO14 */
0
,
/* GENERALIO15
*/
0
,
/* GENERALIO16
*/
0
,
/* GENERALIO17
*/
0
,
/* GENERALIO18
*/
0
,
/* GENERALIO19 */
0
,
/* GENERALIO20 */
0
,
/* GENERALIO21 */
0
,
/* GENERALIO22 */
0
,
/* GENERALIO23 */
0
,
/* GENERALIO24 */
0
,
/* GENERALIO25 */
0
,
/* GENERALIO26 */
0
,
/* GENERALIO27 */
0
,
/* GENERALIO28 */
0
,
/* GENERALIO29 */
0
,
/* GENERALIO30 */
0
,
/* GENERALIO31 */
0
,
/* MIXED1IO0
*/
1
,
/* MIXED1IO1
*/
1
,
/* MIXED1IO2
*/
1
,
/* MIXED1IO3
*/
1
,
/* MIXED1IO4
*/
0
,
/* MIXED1IO5
*/
0
,
/* MIXED1IO6
*/
0
,
/* MIXED1IO7
*/
1
,
/* MIXED1IO8
*/
1
,
/* MIXED1IO9
*/
1
,
/* MIXED1IO10
*/
1
,
/* MIXED1IO11
*/
0
,
/* MIXED1IO12
*/
0
,
/* MIXED1IO13
*/
0
,
/* MIXED1IO14 */
1
,
/* MIXED1IO15
*/
1
,
/* MIXED1IO16
*/
1
,
/* MIXED1IO17
*/
1
,
/* MIXED1IO18
*/
0
,
/* MIXED1IO19
*/
0
,
/* MIXED1IO20
*/
0
,
/* MIXED1IO21 */
0
,
/* MIXED2IO0 */
0
,
/* MIXED2IO1 */
0
,
/* MIXED2IO2 */
0
,
/* MIXED2IO3 */
0
,
/* MIXED2IO4 */
0
,
/* MIXED2IO5 */
0
,
/* MIXED2IO6 */
0
,
/* MIXED2IO7 */
0
,
/* GPLINMUX48 */
0
,
/* GPLINMUX49 */
0
,
/* GPLINMUX50 */
...
...
@@ -212,3 +213,217 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
0
,
/* USB0USEFPGA */
0
/* SPIM0USEFPGA */
};
#endif
/* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
/* pin mux configuration data */
unsigned
long
sys_mgr_init_table
[
CONFIG_HPS_PINMUX_NUM
]
=
{
0
,
/* EMACIO0 */
2
,
/* EMACIO1 */
2
,
/* EMACIO2 */
2
,
/* EMACIO3 */
2
,
/* EMACIO4 */
2
,
/* EMACIO5 */
2
,
/* EMACIO6 */
2
,
/* EMACIO7 */
2
,
/* EMACIO8 */
0
,
/* EMACIO9 */
2
,
/* EMACIO10 */
2
,
/* EMACIO11 */
2
,
/* EMACIO12 */
2
,
/* EMACIO13 */
3
,
/* EMACIO14 */
3
,
/* EMACIO15 */
3
,
/* EMACIO16 */
3
,
/* EMACIO17 */
3
,
/* EMACIO18 */
3
,
/* EMACIO19 */
3
,
/* FLASHIO0 */
0
,
/* FLASHIO1 */
3
,
/* FLASHIO2 */
3
,
/* FLASHIO3 */
0
,
/* FLASHIO4 */
0
,
/* FLASHIO5 */
0
,
/* FLASHIO6 */
0
,
/* FLASHIO7 */
0
,
/* FLASHIO8 */
3
,
/* FLASHIO9 */
3
,
/* FLASHIO10 */
3
,
/* FLASHIO11 */
3
,
/* GENERALIO0 */
3
,
/* GENERALIO1 */
3
,
/* GENERALIO2 */
3
,
/* GENERALIO3 */
3
,
/* GENERALIO4 */
3
,
/* GENERALIO5 */
3
,
/* GENERALIO6 */
3
,
/* GENERALIO7 */
3
,
/* GENERALIO8 */
0
,
/* GENERALIO9 */
0
,
/* GENERALIO10 */
0
,
/* GENERALIO11 */
0
,
/* GENERALIO12 */
0
,
/* GENERALIO13 */
0
,
/* GENERALIO14 */
3
,
/* GENERALIO15 */
3
,
/* GENERALIO16 */
2
,
/* GENERALIO17 */
2
,
/* GENERALIO18 */
0
,
/* GENERALIO19 */
0
,
/* GENERALIO20 */
0
,
/* GENERALIO21 */
0
,
/* GENERALIO22 */
3
,
/* GENERALIO23 */
3
,
/* GENERALIO24 */
0
,
/* GENERALIO25 */
0
,
/* GENERALIO26 */
0
,
/* GENERALIO27 */
0
,
/* GENERALIO28 */
0
,
/* GENERALIO29 */
0
,
/* GENERALIO30 */
0
,
/* GENERALIO31 */
0
,
/* MIXED1IO0 */
0
,
/* MIXED1IO1 */
0
,
/* MIXED1IO2 */
0
,
/* MIXED1IO3 */
0
,
/* MIXED1IO4 */
0
,
/* MIXED1IO5 */
0
,
/* MIXED1IO6 */
0
,
/* MIXED1IO7 */
0
,
/* MIXED1IO8 */
0
,
/* MIXED1IO9 */
0
,
/* MIXED1IO10 */
0
,
/* MIXED1IO11 */
0
,
/* MIXED1IO12 */
0
,
/* MIXED1IO13 */
0
,
/* MIXED1IO14 */
3
,
/* MIXED1IO15 */
3
,
/* MIXED1IO16 */
3
,
/* MIXED1IO17 */
3
,
/* MIXED1IO18 */
3
,
/* MIXED1IO19 */
3
,
/* MIXED1IO20 */
0
,
/* MIXED1IO21 */
3
,
/* MIXED2IO0 */
3
,
/* MIXED2IO1 */
3
,
/* MIXED2IO2 */
3
,
/* MIXED2IO3 */
3
,
/* MIXED2IO4 */
3
,
/* MIXED2IO5 */
3
,
/* MIXED2IO6 */
3
,
/* MIXED2IO7 */
0
,
/* GPLINMUX48 */
0
,
/* GPLINMUX49 */
0
,
/* GPLINMUX50 */
0
,
/* GPLINMUX51 */
0
,
/* GPLINMUX52 */
0
,
/* GPLINMUX53 */
0
,
/* GPLINMUX54 */
0
,
/* GPLINMUX55 */
0
,
/* GPLINMUX56 */
0
,
/* GPLINMUX57 */
0
,
/* GPLINMUX58 */
0
,
/* GPLINMUX59 */
0
,
/* GPLINMUX60 */
0
,
/* GPLINMUX61 */
0
,
/* GPLINMUX62 */
0
,
/* GPLINMUX63 */
0
,
/* GPLINMUX64 */
0
,
/* GPLINMUX65 */
0
,
/* GPLINMUX66 */
0
,
/* GPLINMUX67 */
0
,
/* GPLINMUX68 */
0
,
/* GPLINMUX69 */
0
,
/* GPLINMUX70 */
1
,
/* GPLMUX0 */
1
,
/* GPLMUX1 */
1
,
/* GPLMUX2 */
1
,
/* GPLMUX3 */
1
,
/* GPLMUX4 */
1
,
/* GPLMUX5 */
1
,
/* GPLMUX6 */
1
,
/* GPLMUX7 */
1
,
/* GPLMUX8 */
1
,
/* GPLMUX9 */
1
,
/* GPLMUX10 */
1
,
/* GPLMUX11 */
1
,
/* GPLMUX12 */
1
,
/* GPLMUX13 */
1
,
/* GPLMUX14 */
1
,
/* GPLMUX15 */
1
,
/* GPLMUX16 */
1
,
/* GPLMUX17 */
1
,
/* GPLMUX18 */
1
,
/* GPLMUX19 */
1
,
/* GPLMUX20 */
1
,
/* GPLMUX21 */
1
,
/* GPLMUX22 */
1
,
/* GPLMUX23 */
1
,
/* GPLMUX24 */
1
,
/* GPLMUX25 */
1
,
/* GPLMUX26 */
1
,
/* GPLMUX27 */
1
,
/* GPLMUX28 */
1
,
/* GPLMUX29 */
1
,
/* GPLMUX30 */
1
,
/* GPLMUX31 */
1
,
/* GPLMUX32 */
1
,
/* GPLMUX33 */
1
,
/* GPLMUX34 */
1
,
/* GPLMUX35 */
1
,
/* GPLMUX36 */
1
,
/* GPLMUX37 */
1
,
/* GPLMUX38 */
1
,
/* GPLMUX39 */
1
,
/* GPLMUX40 */
1
,
/* GPLMUX41 */
1
,
/* GPLMUX42 */
1
,
/* GPLMUX43 */
1
,
/* GPLMUX44 */
1
,
/* GPLMUX45 */
1
,
/* GPLMUX46 */
1
,
/* GPLMUX47 */
1
,
/* GPLMUX48 */
1
,
/* GPLMUX49 */
1
,
/* GPLMUX50 */
1
,
/* GPLMUX51 */
1
,
/* GPLMUX52 */
1
,
/* GPLMUX53 */
1
,
/* GPLMUX54 */
1
,
/* GPLMUX55 */
1
,
/* GPLMUX56 */
1
,
/* GPLMUX57 */
1
,
/* GPLMUX58 */
1
,
/* GPLMUX59 */
1
,
/* GPLMUX60 */
1
,
/* GPLMUX61 */
1
,
/* GPLMUX62 */
1
,
/* GPLMUX63 */
1
,
/* GPLMUX64 */
1
,
/* GPLMUX65 */
1
,
/* GPLMUX66 */
1
,
/* GPLMUX67 */
1
,
/* GPLMUX68 */
1
,
/* GPLMUX69 */
1
,
/* GPLMUX70 */
0
,
/* NANDUSEFPGA */
0
,
/* UART0USEFPGA */
0
,
/* RGMII1USEFPGA */
0
,
/* SPIS0USEFPGA */
0
,
/* CAN0USEFPGA */
0
,
/* I2C0USEFPGA */
0
,
/* SDMMCUSEFPGA */
0
,
/* QSPIUSEFPGA */
0
,
/* SPIS1USEFPGA */
0
,
/* RGMII0USEFPGA */
0
,
/* UART1USEFPGA */
0
,
/* CAN1USEFPGA */
0
,
/* USB1USEFPGA */
0
,
/* I2C3USEFPGA */
0
,
/* I2C2USEFPGA */
0
,
/* I2C1USEFPGA */
0
,
/* SPIM1USEFPGA */
0
,
/* USB0USEFPGA */
0
/* SPIM0USEFPGA */
};
#endif
/* CONFIG_TARGET_SOCFPGA_ARRIA5 */
board/altera/socfpga/pinmux_config.h
浏览文件 @
65994d04
...
...
@@ -7,21 +7,21 @@
* State of enabling for which IP connected out through the muxing.
* Value 1 mean the IP connection is muxed out
*/
#define CONFIG_HPS_EMAC0 (
0
)
#define CONFIG_HPS_EMAC1 (
1
)
#define CONFIG_HPS_EMAC0 (
1
)
#define CONFIG_HPS_EMAC1 (
0
)
#define CONFIG_HPS_USB0 (0)
#define CONFIG_HPS_USB1 (1)
#define CONFIG_HPS_NAND (0)
#define CONFIG_HPS_SDMMC (1)
#define CONFIG_HPS_QSPI (
1
)
#define CONFIG_HPS_QSPI (
0
)
#define CONFIG_HPS_UART0 (1)
#define CONFIG_HPS_UART1 (0)
#define CONFIG_HPS_TRACE (
1
)
#define CONFIG_HPS_TRACE (
0
)
#define CONFIG_HPS_I2C0 (1)
#define CONFIG_HPS_I2C1 (0)
#define CONFIG_HPS_I2C2 (0)
#define CONFIG_HPS_I2C3 (0)
#define CONFIG_HPS_SPIM0 (
1
)
#define CONFIG_HPS_SPIM0 (
0
)
#define CONFIG_HPS_SPIM1 (0)
#define CONFIG_HPS_SPIS0 (0)
#define CONFIG_HPS_SPIS1 (0)
...
...
@@ -29,10 +29,10 @@
#define CONFIG_HPS_CAN1 (0)
/* IP attribute value (which affected by pin muxing configuration) */
#define CONFIG_HPS_SDMMC_BUSWIDTH (
4
)
#define CONFIG_HPS_SDMMC_BUSWIDTH (
8
)
/* 1 if the pins are connected out */
#define CONFIG_HPS_QSPI_CS0 (
1
)
#define CONFIG_HPS_QSPI_CS0 (
0
)
#define CONFIG_HPS_QSPI_CS1 (0)
#define CONFIG_HPS_QSPI_CS2 (0)
#define CONFIG_HPS_QSPI_CS3 (0)
...
...
board/altera/socfpga/pll_config.h
浏览文件 @
65994d04
...
...
@@ -16,9 +16,9 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (
3
)
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (
3
)
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (1
2
)
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (
511
)
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (
511
)
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (1
5
)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
...
...
@@ -36,7 +36,7 @@
/* Peripheral PLL */
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (
7
9)
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (
3
9)
/*
* To tell where is the VCOs source:
* 0 = EOSC1
...
...
@@ -45,13 +45,13 @@
*/
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (
3
)
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (
511
)
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (
51
1)
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (
9
)
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (
511
)
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (
0
)
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (
4
)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
...
...
@@ -66,15 +66,8 @@
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
/* SDRAM PLL */
#ifdef CONFIG_SOCFPGA_ARRIA5
/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
* This if..else... is not required if generated by tools */
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127)
#else
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
#endif
/* CONFIG_SOCFPGA_ARRIA5 */
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
/*
* To tell where is the VCOs source:
...
...
@@ -94,17 +87,12 @@
/* Info for driver */
#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
#define CONFIG_HPS_CLK_OSC2_HZ
0
#define CONFIG_HPS_CLK_OSC2_HZ
(25000000)
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000)
#else
#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
#endif
#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666)
#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
...
...
board/altera/socfpga/socfpga
_cyclone5
.c
→
board/altera/socfpga/socfpga.c
浏览文件 @
65994d04
...
...
@@ -18,23 +18,6 @@
DECLARE_GLOBAL_DATA_PTR
;
/*
* Print Board information
*/
int
checkboard
(
void
)
{
puts
(
"BOARD: Altera SoCFPGA Cyclone5 Board
\n
"
);
return
0
;
}
/*
* Initialization function which happen at early stage of c code
*/
int
board_early_init_f
(
void
)
{
return
0
;
}
/*
* Miscellaneous platform dependent initialisations
*/
...
...
configs/socfpga_arria5_defconfig
0 → 100644
浏览文件 @
65994d04
CONFIG_SPL=y
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_SOCFPGA_ARRIA5=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
configs/socfpga_cyclone5_defconfig
浏览文件 @
65994d04
CONFIG_SPL=y
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
include/configs/socfpga_arria5.h
0 → 100644
浏览文件 @
65994d04
/*
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
#define __CONFIG_SOCFPGA_ARRIA5_H__
#include <asm/arch/socfpga_base_addrs.h>
#include "../../board/altera/socfpga/pinmux_config.h"
#include "../../board/altera/socfpga/iocsr_config.h"
#include "../../board/altera/socfpga/pll_config.h"
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#include <config_cmd_default.h>
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DFU
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_USB
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_REGEX
/* Enable regular expression support */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000
/* 1GiB on SoCDK */
/* Booting Linux */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "zImage"
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_BOOTCOMMAND "run ramboot"
#else
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
#endif
#define CONFIG_LOADADDR 0x8000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER "Altera"
/* Extra Environment */
#define CONFIG_HOSTNAME socfpga_arria5
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
"fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
" root=${mmcroot} rw rootwait;" \
"bootz ${loadaddr} - ${fdt_addr}\0" \
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
"qspiroot=/dev/mtdblock0\0" \
"qspirootfstype=jffs2\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
"bootm ${loadaddr} - ${fdt_addr}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#endif
/* __CONFIG_SOCFPGA_ARRIA5_H__ */
include/configs/socfpga_common.h
浏览文件 @
65994d04
...
...
@@ -19,8 +19,7 @@
* High level configuration
*/
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CLOCKS
...
...
include/configs/socfpga_cyclone5.h
浏览文件 @
65994d04
...
...
@@ -21,6 +21,7 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DFU
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
...
...
@@ -33,6 +34,8 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_USB
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_REGEX
/* Enable regular expression support */
...
...
@@ -66,6 +69,12 @@
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER "Altera"
/* Extra Environment */
#define CONFIG_HOSTNAME socfpga_cyclone5
...
...
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