Merge tag 'uniphier-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier

UniPhier SoC updates for v2020.10

 - remove workaround for Cortex-A72

 - increase U-Boot proper size to 2MB

 - sync DT with Linux

 - add system bus controller driver

 - improve serial driver

 - add reset assertion to Denali NAND driver

arch/arm/dts/uniphier-ld11-global.dts

@@ -30,6 +30,7 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {

arch/arm/dts/uniphier-ld11-ref.dts

@@ -29,6 +29,7 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {

arch/arm/dts/uniphier-ld11.dtsi

@@ -129,6 +129,8 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 39 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi0>;
@@ -140,11 +142,13 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006100 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 216 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi1>;
-			clocks = <&peri_clk 11>;
-			resets = <&peri_rst 11>;
+			clocks = <&peri_clk 12>;
+			resets = <&peri_rst 12>;
 		};
 
 		serial0: serial@54006800 {
@@ -566,6 +570,14 @@
 			};
 		};
 
+		xdmac: dma-controller@5fc10000 {
+			compatible = "socionext,uniphier-xdmac";
+			reg = <0x5fc10000 0x5300>;
+			interrupts = <0 188 4>;
+			dma-channels = <16>;
+			#dma-cells = <2>;
+		};
+
 		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-ld11-aidet";
 			reg = <0x5fc20000 0x200>;

arch/arm/dts/uniphier-ld20-global.dts

@@ -30,6 +30,7 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {

arch/arm/dts/uniphier-ld20-ref.dts

@@ -29,6 +29,7 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {

arch/arm/dts/uniphier-ld20.dtsi

@@ -234,6 +234,8 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 39 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi0>;
@@ -245,33 +247,39 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006100 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 216 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi1>;
-			clocks = <&peri_clk 11>;
-			resets = <&peri_rst 11>;
+			clocks = <&peri_clk 12>;
+			resets = <&peri_rst 12>;
 		};
 
 		spi2: spi@54006200 {
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006200 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 229 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi2>;
-			clocks = <&peri_clk 11>;
-			resets = <&peri_rst 11>;
+			clocks = <&peri_clk 13>;
+			resets = <&peri_rst 13>;
 		};
 
 		spi3: spi@54006300 {
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006300 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 230 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi3>;
-			clocks = <&peri_clk 11>;
-			resets = <&peri_rst 11>;
+			clocks = <&peri_clk 14>;
+			resets = <&peri_rst 14>;
 		};
 
 		serial0: serial@54006800 {
@@ -664,6 +672,14 @@
 			};
 		};
 
+		xdmac: dma-controller@5fc10000 {
+			compatible = "socionext,uniphier-xdmac";
+			reg = <0x5fc10000 0x5300>;
+			interrupts = <0 188 4>;
+			dma-channels = <16>;
+			#dma-cells = <2>;
+		};
+
 		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-ld20-aidet";
 			reg = <0x5fc20000 0x200>;

arch/arm/dts/uniphier-ld4.dtsi

@@ -67,6 +67,8 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 39 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi0>;

arch/arm/dts/uniphier-ld6b-ref.dts

@@ -29,6 +29,7 @@
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
 		i2c6 = &i2c6;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {

arch/arm/dts/uniphier-pro4-ace.dts

@@ -26,6 +26,7 @@
 		i2c3 = &i2c3;
 		i2c5 = &i2c5;
 		i2c6 = &i2c6;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {

arch/arm/dts/uniphier-pro4-ref.dts

@@ -30,6 +30,7 @@
 		i2c5 = &i2c5;
 		i2c6 = &i2c6;
 		usb0 = &usb0;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {

arch/arm/dts/uniphier-pro4.dtsi

@@ -75,6 +75,8 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 39 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi0>;
@@ -426,6 +428,14 @@
 			};
 		};
 
+		xdmac: dma-controller@5fc10000 {
+			compatible = "socionext,uniphier-xdmac";
+			reg = <0x5fc10000 0x5300>;
+			interrupts = <0 188 4>;
+			dma-channels = <16>;
+			#dma-cells = <2>;
+		};
+
 		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-pro4-aidet";
 			reg = <0x5fc20000 0x200>;

arch/arm/dts/uniphier-pro5.dtsi

@@ -160,6 +160,8 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 39 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi0>;
@@ -171,11 +173,13 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006100 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 216 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi1>;
-			clocks = <&peri_clk 11>;
-			resets = <&peri_rst 11>;
+			clocks = <&peri_clk 11>;	/* common with spi0 */
+			resets = <&peri_rst 12>;
 		};
 
 		serial0: serial@54006800 {
@@ -408,6 +412,14 @@
 			};
 		};
 
+		xdmac: dma-controller@5fc10000 {
+			compatible = "socionext,uniphier-xdmac";
+			reg = <0x5fc10000 0x5300>;
+			interrupts = <0 188 4>;
+			dma-channels = <16>;
+			#dma-cells = <2>;
+		};
+
 		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-pro5-aidet";
 			reg = <0x5fc20000 0x200>;

arch/arm/dts/uniphier-pxs2-gentil.dts

@@ -26,6 +26,7 @@
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
 		i2c6 = &i2c6;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {

arch/arm/dts/uniphier-pxs2-vodka.dts

@@ -24,6 +24,7 @@
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
 		i2c6 = &i2c6;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {

arch/arm/dts/uniphier-pxs2.dtsi

@@ -173,6 +173,8 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 39 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi0>;
@@ -184,11 +186,13 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006100 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 216 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi1>;
-			clocks = <&peri_clk 11>;
-			resets = <&peri_rst 11>;
+			clocks = <&peri_clk 12>;
+			resets = <&peri_rst 12>;
 		};
 
 		serial0: serial@54006800 {
@@ -508,6 +512,14 @@
 			};
 		};
 
+		xdmac: dma-controller@5fc10000 {
+			compatible = "socionext,uniphier-xdmac";
+			reg = <0x5fc10000 0x5300>;
+			interrupts = <0 188 4>;
+			dma-channels = <16>;
+			#dma-cells = <2>;
+		};
+
 		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-pxs2-aidet";
 			reg = <0x5fc20000 0x200>;

arch/arm/dts/uniphier-pxs3-ref.dts

@@ -27,6 +27,10 @@
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
 		i2c6 = &i2c6;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		ethernet0 = &eth0;
+		ethernet1 = &eth1;
 	};
 
 	memory@80000000 {
@@ -39,6 +43,14 @@
 	interrupts = <4 8>;
 };
 
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
 &serial0 {
 	status = "okay";
 };
@@ -116,3 +128,19 @@
 &nand {
 	status = "okay";
 };
+
+&pinctrl_ether_rgmii {
+	tx {
+		pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
+		       "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL";
+		drive-strength = <9>;
+	};
+};
+
+&pinctrl_ether1_rgmii {
+	tx {
+		pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1",
+		       "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL";
+		drive-strength = <9>;
+	};
+};

arch/arm/dts/uniphier-pxs3.dtsi

@@ -7,6 +7,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	compatible = "socionext,uniphier-pxs3";
@@ -42,6 +43,7 @@
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu1: cpu@1 {
@@ -51,6 +53,7 @@
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu2: cpu@2 {
@@ -60,6 +63,7 @@
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu@3 {
@@ -69,6 +73,7 @@
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 	};
 
@@ -136,6 +141,37 @@
 			     <1 10 4>;
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <250>;	/* 250ms */
+			polling-delay = <1000>;		/* 1000ms */
+			thermal-sensors = <&pvtctl>;
+
+			trips {
+				cpu_crit: cpu-crit {
+					temperature = <110000>;	/* 110C */
+					hysteresis = <2000>;
+					type = "critical";
+				};
+				cpu_alert: cpu-alert {
+					temperature = <100000>;	/* 100C */
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -157,6 +193,8 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 39 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi0>;
@@ -168,11 +206,13 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006100 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 216 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi1>;
-			clocks = <&peri_clk 11>;
-			resets = <&peri_rst 11>;
+			clocks = <&peri_clk 12>;
+			resets = <&peri_rst 12>;
 		};
 
 		serial0: serial@54006800 {
@@ -462,6 +502,14 @@
 			};
 		};
 
+		xdmac: dma-controller@5fc10000 {
+			compatible = "socionext,uniphier-xdmac";
+			reg = <0x5fc10000 0x5300>;
+			interrupts = <0 188 4>;
+			dma-channels = <16>;
+			#dma-cells = <2>;
+		};
+
 		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-pxs3-aidet";
 			reg = <0x5fc20000 0x200>;
@@ -496,6 +544,13 @@
 			watchdog {
 				compatible = "socionext,uniphier-wdt";
 			};
+
+			pvtctl: pvtctl {
+				compatible = "socionext,uniphier-pxs3-thermal";
+				interrupts = <0 3 4>;
+				#thermal-sensor-cells = <0>;
+				socionext,tmod-calibration = <0x0f22 0x68ee>;
+			};
 		};
 
 		eth0: ethernet@65000000 {

arch/arm/dts/uniphier-sld8.dtsi

@@ -67,6 +67,8 @@
 			compatible = "socionext,uniphier-scssi";
 			status = "disabled";
 			reg = <0x54006000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			interrupts = <0 39 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_spi0>;

arch/arm/mach-uniphier/Kconfig

@@ -3,24 +3,15 @@ if ARCH_UNIPHIER
 config SYS_CONFIG_NAME
 	default "uniphier"
 
-config ARCH_UNIPHIER_32BIT
-	bool
-	select ARCH_SUPPORT_PSCI
-	select ARMV7_NONSEC
-	select CPU_V7A
-	select CPU_V7_HAS_NONSEC
-
 choice
         prompt "UniPhier SoC select"
-        default ARCH_UNIPHIER_V7_MULTI
-
-config ARCH_UNIPHIER_LD4_SLD8
-	bool "UniPhier LD4/sLD8 SoCs"
-	select ARCH_UNIPHIER_32BIT
 
 config ARCH_UNIPHIER_V7_MULTI
-	bool "UniPhier Pro4/Pro5/PXs2/LD6b SoCs"
-	select ARCH_UNIPHIER_32BIT
+	bool "UniPhier V7 SoCs"
+	select ARCH_SUPPORT_PSCI
+	select ARMV7_NONSEC
+	select CPU_V7A
+	select CPU_V7_HAS_NONSEC
 
 config ARCH_UNIPHIER_V8_MULTI
 	bool "UniPhier V8 SoCs"
@@ -32,32 +23,38 @@ endchoice
 
 config ARCH_UNIPHIER_LD4
 	bool "Enable UniPhier LD4 SoC support"
-	depends on ARCH_UNIPHIER_LD4_SLD8
+	depends on ARCH_UNIPHIER_V7_MULTI
+	depends on !SPL || SPL_TEXT_BASE = 0x00040000
 	default y
 
 config ARCH_UNIPHIER_SLD8
 	bool "Enable UniPhier sLD8 SoC support"
-	depends on ARCH_UNIPHIER_LD4_SLD8
+	depends on ARCH_UNIPHIER_V7_MULTI
+	depends on !SPL || SPL_TEXT_BASE = 0x00040000
 	default y
 
 config ARCH_UNIPHIER_PRO4
 	bool "Enable UniPhier Pro4 SoC support"
 	depends on ARCH_UNIPHIER_V7_MULTI
+	depends on !SPL || SPL_TEXT_BASE = 0x00100000
 	default y
 
 config ARCH_UNIPHIER_PRO5
 	bool "Enable UniPhier Pro5 SoC support"
 	depends on ARCH_UNIPHIER_V7_MULTI
+	depends on !SPL || SPL_TEXT_BASE = 0x00100000
 	default y
 
 config ARCH_UNIPHIER_PXS2
 	bool "Enable UniPhier Pxs2 SoC support"
 	depends on ARCH_UNIPHIER_V7_MULTI
+	depends on !SPL || SPL_TEXT_BASE = 0x00100000
 	default y
 
 config ARCH_UNIPHIER_LD6B
 	bool "Enable UniPhier LD6b SoC support"
 	depends on ARCH_UNIPHIER_V7_MULTI
+	depends on !SPL || SPL_TEXT_BASE = 0x00100000
 	default y
 
 config ARCH_UNIPHIER_LD11
@@ -78,7 +75,7 @@ config ARCH_UNIPHIER_PXS3
 
 config CACHE_UNIPHIER
 	bool "Enable the UniPhier L2 cache controller"
-	depends on ARCH_UNIPHIER_32BIT
+	depends on ARCH_UNIPHIER_V7_MULTI
 	default y
 	select SYS_CACHE_SHIFT_7
 	help
@@ -86,6 +83,7 @@ config CACHE_UNIPHIER
 
 config MICRO_SUPPORT_CARD
 	bool "Use Micro Support Card"
+	depends on UNIPHIER_SYSTEM_BUS
 	help
 	  This option provides support for the expansion board, available
 	  on some UniPhier reference boards.
@@ -118,5 +116,5 @@ config CMD_DDRMPHY_DUMP
 	  training; it is useful for the evaluation of DDR Multi PHY training.
 
 config SYS_SOC
-	default "uniphier-v7" if ARCH_UNIPHIER_LD4_SLD8 || ARCH_UNIPHIER_V7_MULTI
+	default "uniphier-v7" if ARCH_UNIPHIER_V7_MULTI
 endif

arch/arm/mach-uniphier/Makefile

@@ -22,12 +22,10 @@ endif
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
 obj-y += pinctrl-glue.o
 obj-$(CONFIG_MMC) += mmc-first-dev.o
-obj-$(CONFIG_NAND_DENALI) += nand-reset.o
 obj-y += fdt-fixup.o
 
 endif
 
-obj-y += sbc/
 obj-y += soc-info.o
 obj-y += boot-device/
 obj-y += clk/

arch/arm/mach-uniphier/arm64/Makefile

 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y += mem_map.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += lowlevel_init.o

arch/arm/mach-uniphier/arm64/lowlevel_init.S

-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Socionext Inc.
- */
-
-#include <linux/linkage.h>
-
-ENTRY(lowlevel_init)
-	/* LD20 needs the following code to boot.  I do not know why. */
-	mrs	x0, sctlr_el1
-	msr	sctlr_el1, x0
-	ret
-ENDPROC(lowlevel_init)

arch/arm/mach-uniphier/board_init.c

@@ -13,6 +13,33 @@
 #include "micro-support-card.h"
 #include "soc-info.h"
 
+#define PC0CTRL				0x598000c0
+
+#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8)
+static void uniphier_ld4_sbc_init(void)
+{
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+}
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || \
+    defined(CONFIG_ARCH_UNIPHIER_LD6B) || \
+    defined(CONFIG_ARCH_UNIPHIER_LD11) || \
+    defined(CONFIG_ARCH_UNIPHIER_LD20) || \
+    defined(CONFIG_ARCH_UNIPHIER_PXS3)
+static void uniphier_pxs2_sbc_init(void)
+{
+	/* necessary for ROM boot ?? */
+	/* system bus output enable */
+	writel(0x17, PC0CTRL);
+}
+#endif
+
 #ifdef CONFIG_ARCH_UNIPHIER_LD20
 static void uniphier_ld20_misc_init(void)
 {
@@ -45,7 +72,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
 	{
 		.soc_id = UNIPHIER_PRO4_ID,
-		.sbc_init = uniphier_sbc_init_savepin,
 		.pll_init = uniphier_pro4_pll_init,
 		.clk_init = uniphier_pro4_clk_init,
 	},
@@ -60,7 +86,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
 	{
 		.soc_id = UNIPHIER_PRO5_ID,
-		.sbc_init = uniphier_sbc_init_savepin,
 		.clk_init = uniphier_pro5_clk_init,
 	},
 #endif
@@ -81,7 +106,7 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
 	{
 		.soc_id = UNIPHIER_LD11_ID,
-		.sbc_init = uniphier_ld11_sbc_init,
+		.sbc_init = uniphier_pxs2_sbc_init,
 		.pll_init = uniphier_ld11_pll_init,
 		.clk_init = uniphier_ld11_clk_init,
 	},
@@ -89,7 +114,7 @@ static const struct uniphier_initdata uniphier_initdata[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 	{
 		.soc_id = UNIPHIER_LD20_ID,
-		.sbc_init = uniphier_ld11_sbc_init,
+		.sbc_init = uniphier_pxs2_sbc_init,
 		.pll_init = uniphier_ld20_pll_init,
 		.clk_init = uniphier_ld20_clk_init,
 		.misc_init = uniphier_ld20_misc_init,
@@ -118,7 +143,8 @@ int board_init(void)
 		return -EINVAL;
 	}
 
-	initdata->sbc_init();
+	if (initdata->sbc_init)
+		initdata->sbc_init();
 
 	support_card_init();
 
@@ -137,14 +163,6 @@ int board_init(void)
 	if (initdata->misc_init)
 		initdata->misc_init();
 
-	led_puts("U3");
-
-	support_card_late_init();
-
-	led_puts("U4");
-
-	uniphier_nand_reset_assert();
-
 	led_puts("Uboo");
 
 	return 0;

arch/arm/mach-uniphier/boot-device/boot-device.c

@@ -14,11 +14,18 @@
 #include <linux/log2.h>
 
 #include "../init.h"
-#include "../sbc/sbc-regs.h"
 #include "../sg-regs.h"
 #include "../soc-info.h"
 #include "boot-device.h"
 
+#define SBBASE0			0x58c00100
+#define SBBASE_BANK_ENABLE		BIT(0)
+
+static int uniphier_sbc_boot_is_swapped(void)
+{
+	return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
+}
+
 struct uniphier_boot_device_info {
 	unsigned int soc_id;
 	unsigned int boot_device_sel_shift;

arch/arm/mach-uniphier/init.h

@@ -34,34 +34,6 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
 
-#if defined(CONFIG_MICRO_SUPPORT_CARD)
-void uniphier_sbc_init_admulti(void);
-void uniphier_sbc_init_savepin(void);
-void uniphier_ld4_sbc_init(void);
-void uniphier_pxs2_sbc_init(void);
-void uniphier_ld11_sbc_init(void);
-#else
-static inline void uniphier_sbc_init_admulti(void)
-{
-}
-
-static inline void uniphier_sbc_init_savepin(void)
-{
-}
-
-static inline void uniphier_ld4_sbc_init(void)
-{
-}
-
-static inline void uniphier_pxs2_sbc_init(void)
-{
-}
-
-static inline void uniphier_ld11_sbc_init(void)
-{
-}
-#endif
-
 void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
 
 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
@@ -103,13 +75,6 @@ int uniphier_have_internal_stm(void);
 int uniphier_boot_from_backend(void);
 int uniphier_pin_init(const char *pinconfig_name);
 
-#ifdef CONFIG_NAND_DENALI
-void uniphier_nand_reset_assert(void);
-#else
-static inline void uniphier_nand_reset_assert(void)
-{
-}
-#endif
 #ifdef CONFIG_ARM64
 void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size);
 #else

arch/arm/mach-uniphier/micro-support-card.c

@@ -5,8 +5,7 @@
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  */
 
-#include <config.h>
-#include <dm/of.h>
+#include <dm.h>
 #include <fdt_support.h>
 #include <linux/ctype.h>
 #include <linux/delay.h>
@@ -91,6 +90,17 @@ static int support_card_show_revision(void)
 
 void support_card_init(void)
 {
+	struct udevice *dev;
+	int ret;
+
+	/* The system bus must be initialized for access to the support card. */
+	ret = uclass_get_device_by_driver(UCLASS_SIMPLE_BUS,
+					  DM_GET_DRIVER(uniphier_system_bus_driver),
+					  &dev);
+	if (ret)
+		return;
+
+	/* Check DT to see if this board has the support card. */
 	support_card_detect();
 
 	if (!support_card_found)
@@ -107,102 +117,6 @@ void support_card_init(void)
 	support_card_show_revision();
 }
 
-#if defined(CONFIG_MTD_NOR_FLASH)
-
-#include <mtd/cfi_flash.h>
-
-struct memory_bank {
-	phys_addr_t base;
-	unsigned long size;
-};
-
-static int mem_is_flash(const struct memory_bank *mem)
-{
-	const int loop = 128;
-	u32 *scratch_addr;
-	u32 saved_value;
-	int ret = 1;
-	int i;
-
-	/* just in case, use the tail of the memory bank */
-	scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
-				   sizeof(u32) * loop, MAP_NOCACHE);
-
-	for (i = 0; i < loop; i++, scratch_addr++) {
-		saved_value = readl(scratch_addr);
-		writel(~saved_value, scratch_addr);
-		if (readl(scratch_addr) != saved_value) {
-			/* We assume no memory or SRAM here. */
-			writel(saved_value, scratch_addr);
-			ret = 0;
-			break;
-		}
-	}
-
-	unmap_physmem(scratch_addr, MAP_NOCACHE);
-
-	return ret;
-}
-
-/* {address, size} */
-static const struct memory_bank memory_banks[] = {
-	{0x42000000, 0x01f00000},
-};
-
-static const struct memory_bank
-*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
-
-phys_addr_t cfi_flash_bank_addr(int i)
-{
-	return flash_banks_list[i]->base;
-}
-
-unsigned long cfi_flash_bank_size(int i)
-{
-	return flash_banks_list[i]->size;
-}
-
-static void detect_num_flash_banks(void)
-{
-	const struct memory_bank *memory_bank, *end;
-
-	cfi_flash_num_flash_banks = 0;
-
-	memory_bank = memory_banks;
-	end = memory_bank + ARRAY_SIZE(memory_banks);
-
-	for (; memory_bank < end; memory_bank++) {
-		if (cfi_flash_num_flash_banks >=
-		    CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
-			break;
-
-		if (mem_is_flash(memory_bank)) {
-			flash_banks_list[cfi_flash_num_flash_banks] =
-								memory_bank;
-
-			debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
-			      (unsigned long)memory_bank->base,
-			      (unsigned long)memory_bank->size);
-			cfi_flash_num_flash_banks++;
-		}
-	}
-
-	debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
-}
-#else /* CONFIG_MTD_NOR_FLASH */
-static void detect_num_flash_banks(void)
-{
-};
-#endif /* CONFIG_MTD_NOR_FLASH */
-
-void support_card_late_init(void)
-{
-	if (!support_card_found)
-		return;
-
-	detect_num_flash_banks();
-}
-
 static const u8 ledval_num[] = {
 	0x7e, /* 0 */
 	0x0c, /* 1 */

arch/arm/mach-uniphier/nand-reset.c

-// SPDX-License-Identifier: GPL-2.0 or later
-/*
- * Copyright (C) 2020 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- */
-
-#include <linux/errno.h>
-#include <dm.h>
-#include <dm/uclass-internal.h>
-#include <reset.h>
-
-#include "init.h"
-
-/*
- * Assert the Denali NAND controller reset if found.
- *
- * On LD4, the bootstrap process starts running after power-on reset regardless
- * of the boot mode, here the pin-mux is not necessarily set up for NAND, then
- * the controller is stuck. Assert the controller reset here, and should be
- * deasserted in the driver after the pin-mux is correctly handled. For other
- * SoCs, the bootstrap runs only when the boot mode selects ONFi, but it is yet
- * effective when the boot swap is on. So, the reset should be asserted anyway.
- */
-void uniphier_nand_reset_assert(void)
-{
-	struct udevice *dev;
-	struct reset_ctl_bulk resets;
-	int ret;
-
-	ret = uclass_find_first_device(UCLASS_MTD, &dev);
-	if (ret || !dev)
-		return;
-
-	/* make sure this is the Denali NAND controller */
-	if (strcmp(dev->driver->name, "denali-nand-dt"))
-		return;
-
-	ret = reset_get_bulk(dev, &resets);
-	if (ret)
-		return;
-
-	reset_assert_bulk(&resets);
-}

arch/arm/mach-uniphier/sbc/Makefile

-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y					+= sbc-boot.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y					+= sbc.o
-
-obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= sbc-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= sbc-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= sbc-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= sbc-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= sbc-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= sbc-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS3)	+= sbc-pxs2.o
-endif

arch/arm/mach-uniphier/sbc/sbc-boot.c

-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright (C) 2011-2014 Panasonic Corporation
-// Copyright (C) 2015-2019 Socionext Inc.
-
-#include <linux/io.h>
-
-#include "sbc-regs.h"
-
-int uniphier_sbc_boot_is_swapped(void)
-{
-	return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
-}

arch/arm/mach-uniphier/sbc/sbc-ld11.c

-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016-2017 Socionext Inc.
- */
-
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "sbc-regs.h"
-
-void uniphier_ld11_sbc_init(void)
-{
-	if (!uniphier_sbc_is_enabled())
-		return;
-
-	uniphier_sbc_init_savepin();
-
-	/* necessary for ROM boot ?? */
-	/* system bus output enable */
-	writel(0x17, PC0CTRL);
-
-	/* pins for NAND and System Bus are multiplexed */
-	if (spl_boot_device() != BOOT_DEVICE_NAND)
-		uniphier_pin_init("system-bus");
-}

arch/arm/mach-uniphier/sbc/sbc-ld4.c

-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015-2017 Socionext Inc.
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "sbc-regs.h"
-
-void uniphier_ld4_sbc_init(void)
-{
-	u32 tmp;
-
-	if (!uniphier_sbc_is_enabled())
-		return;
-
-	uniphier_sbc_init_savepin();
-
-	/* system bus output enable */
-	tmp = readl(PC0CTRL);
-	tmp &= 0xfffffcff;
-	writel(tmp, PC0CTRL);
-}

arch/arm/mach-uniphier/sbc/sbc-pxs2.c

-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016-2017 Socionext Inc.
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "sbc-regs.h"
-
-void uniphier_pxs2_sbc_init(void)
-{
-	if (!uniphier_sbc_is_enabled())
-		return;
-
-	uniphier_sbc_init_savepin();
-
-	/* necessary for ROM boot ?? */
-	/* system bus output enable */
-	writel(0x17, PC0CTRL);
-
-	uniphier_pin_init("system-bus");	/* PXs3 */
-}

arch/arm/mach-uniphier/sbc/sbc-regs.h

-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * UniPhier SBC (System Bus Controller) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
- */
-
-#ifndef ARCH_SBC_REGS_H
-#define ARCH_SBC_REGS_H
-
-#define	SBBASE_BASE		0x58c00100
-#define	SBBASE(x)		(SBBASE_BASE + (x) * 0x10)
-
-#define	SBBASE0			(SBBASE(0))
-#define	SBBASE1			(SBBASE(1))
-#define	SBBASE2			(SBBASE(2))
-#define	SBBASE3			(SBBASE(3))
-#define	SBBASE4			(SBBASE(4))
-#define	SBBASE5			(SBBASE(5))
-#define	SBBASE6			(SBBASE(6))
-#define	SBBASE7			(SBBASE(7))
-
-#define	SBBASE_BANK_ENABLE	(0x00000001)
-
-#define	SBCTRL_BASE		0x58c00200
-#define	SBCTRL(x, y)		(SBCTRL_BASE + (x) * 0x10 + (y) * 4)
-
-#define	SBCTRL00		SBCTRL(0, 0)
-#define	SBCTRL01		SBCTRL(0, 1)
-#define	SBCTRL02		SBCTRL(0, 2)
-#define	SBCTRL03		SBCTRL(0, 3)
-#define	SBCTRL04		(SBCTRL_BASE + 0x100)
-
-#define	SBCTRL10		SBCTRL(1, 0)
-#define	SBCTRL11		SBCTRL(1, 1)
-#define	SBCTRL12		SBCTRL(1, 2)
-#define	SBCTRL13		SBCTRL(1, 3)
-#define	SBCTRL14		(SBCTRL_BASE + 0x110)
-
-#define	SBCTRL20		SBCTRL(2, 0)
-#define	SBCTRL21		SBCTRL(2, 1)
-#define	SBCTRL22		SBCTRL(2, 2)
-#define	SBCTRL23		SBCTRL(2, 3)
-#define	SBCTRL24		(SBCTRL_BASE + 0x120)
-
-#define	SBCTRL30		SBCTRL(3, 0)
-#define	SBCTRL31		SBCTRL(3, 1)
-#define	SBCTRL32		SBCTRL(3, 2)
-#define	SBCTRL33		SBCTRL(3, 3)
-#define	SBCTRL34		(SBCTRL_BASE + 0x130)
-
-#define	SBCTRL40		SBCTRL(4, 0)
-#define	SBCTRL41		SBCTRL(4, 1)
-#define	SBCTRL42		SBCTRL(4, 2)
-#define	SBCTRL43		SBCTRL(4, 3)
-#define	SBCTRL44		(SBCTRL_BASE + 0x140)
-
-#define	SBCTRL50		SBCTRL(5, 0)
-#define	SBCTRL51		SBCTRL(5, 1)
-#define	SBCTRL52		SBCTRL(5, 2)
-#define	SBCTRL53		SBCTRL(5, 3)
-#define	SBCTRL54		(SBCTRL_BASE + 0x150)
-
-#define	SBCTRL60		SBCTRL(6, 0)
-#define	SBCTRL61		SBCTRL(6, 1)
-#define	SBCTRL62		SBCTRL(6, 2)
-#define	SBCTRL63		SBCTRL(6, 3)
-#define	SBCTRL64		(SBCTRL_BASE + 0x160)
-
-#define	SBCTRL70		SBCTRL(7, 0)
-#define	SBCTRL71		SBCTRL(7, 1)
-#define	SBCTRL72		SBCTRL(7, 2)
-#define	SBCTRL73		SBCTRL(7, 3)
-#define	SBCTRL74		(SBCTRL_BASE + 0x170)
-
-#define PC0CTRL				0x598000c0
-
-int uniphier_sbc_boot_is_swapped(void);
-int uniphier_sbc_is_enabled(void);
-
-#endif	/* ARCH_SBC_REGS_H */

arch/arm/mach-uniphier/sbc/sbc.c

-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015-2017 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- */
-
-#include <linux/io.h>
-#include <asm/global_data.h>
-
-#include "../init.h"
-#include "sbc-regs.h"
-
-#define SBCTRL0_ADMULTIPLX_PERI_VALUE	0x33120000
-#define SBCTRL1_ADMULTIPLX_PERI_VALUE	0x03005500
-#define SBCTRL2_ADMULTIPLX_PERI_VALUE	0x14000020
-
-#define SBCTRL0_ADMULTIPLX_MEM_VALUE	0x33120000
-#define SBCTRL1_ADMULTIPLX_MEM_VALUE	0x03005500
-#define SBCTRL2_ADMULTIPLX_MEM_VALUE	0x14000010
-
-/* slower but LED works */
-#define SBCTRL0_SAVEPIN_PERI_VALUE	0x55450000
-#define SBCTRL1_SAVEPIN_PERI_VALUE	0x07168d00
-#define SBCTRL2_SAVEPIN_PERI_VALUE	0x34000009
-#define SBCTRL4_SAVEPIN_PERI_VALUE	0x02110110
-
-/* faster but LED does not work */
-#define SBCTRL0_SAVEPIN_MEM_VALUE	0x55450000
-#define SBCTRL1_SAVEPIN_MEM_VALUE	0x06057700
-/* NOR flash needs more wait counts than SRAM */
-#define SBCTRL2_SAVEPIN_MEM_VALUE	0x34000009
-#define SBCTRL4_SAVEPIN_MEM_VALUE	0x02110210
-
-int uniphier_sbc_is_enabled(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	const void *fdt = gd->fdt_blob;
-	int offset;
-
-	offset = fdt_node_offset_by_compatible(fdt, 0,
-					       "socionext,uniphier-system-bus");
-	if (offset < 0)
-		return 0;
-
-	return fdtdec_get_is_enabled(fdt, offset);
-}
-
-static void __uniphier_sbc_init(int savepin)
-{
-	/*
-	 * Only CS1 is connected to support card.
-	 * BKSZ[1:0] should be set to "01".
-	 */
-	if (savepin) {
-		writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
-		writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
-		writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
-		writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-	} else {
-		writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
-		writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
-		writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
-	}
-
-	if (uniphier_sbc_boot_is_swapped()) {
-		/*
-		 * Boot Swap On: boot from external NOR/SRAM
-		 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
-		 *
-		 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
-		 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
-		 */
-		writel(0x0000bc01, SBBASE0);
-	} else {
-		/*
-		 * Boot Swap Off: boot from mask ROM
-		 * 0x40000000-0x41ffffff: mask ROM
-		 * 0x42000000-0x43efffff: memory bank (31MB)
-		 * 0x43f00000-0x43ffffff: peripherals (1MB)
-		 */
-		writel(0x0000be01, SBBASE0); /* dummy */
-		writel(0x0200be01, SBBASE1);
-	}
-}
-
-void uniphier_sbc_init_admulti(void)
-{
-	__uniphier_sbc_init(0);
-}
-
-void uniphier_sbc_init_savepin(void)
-{
-	__uniphier_sbc_init(1);
-}

configs/uniphier_ld4_sld8_defconfig

@@ -8,7 +8,6 @@ CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_SPL=y
-CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
 CONFIG_MICRO_SUPPORT_CARD=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
@@ -18,7 +17,6 @@ CONFIG_LOGLEVEL=6
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_CMD_CONFIG=y
-CONFIG_CMD_IMLS=y
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -45,8 +43,6 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_MTD=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_DENALI_DT=y
 CONFIG_SPL_NAND_DENALI=y

configs/uniphier_v7_defconfig

@@ -17,7 +17,6 @@ CONFIG_LOGLEVEL=6
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_CMD_CONFIG=y
-CONFIG_CMD_IMLS=y
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -45,8 +44,6 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_MTD=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_DENALI_DT=y
 CONFIG_SPL_NAND_DENALI=y

configs/uniphier_v8_defconfig

@@ -14,7 +14,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot"
 CONFIG_LOGLEVEL=6
 CONFIG_CMD_CONFIG=y
-CONFIG_CMD_IMLS=y
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -45,8 +44,6 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_CADENCE=y
 CONFIG_MTD=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_DENALI_DT=y
 CONFIG_SNI_AVE=y

drivers/Kconfig

@@ -10,6 +10,8 @@ source "drivers/ata/Kconfig"
 
 source "drivers/axi/Kconfig"
 
+source "drivers/bus/Kconfig"
+
 source "drivers/block/Kconfig"
 
 source "drivers/bootcount/Kconfig"

drivers/Makefile

@@ -74,6 +74,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 
 obj-y += adc/
 obj-y += ata/
+obj-y += bus/
 obj-$(CONFIG_DM_DEMO) += demo/
 obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/

drivers/bus/Kconfig

+# SPDX-License-Identifier: GPL-2.0
+#
+# Bus Devices
+#
+
+menu "Bus devices"
+
+config UNIPHIER_SYSTEM_BUS
+	bool "UniPhier System Bus driver"
+	depends on ARCH_UNIPHIER
+	default y
+	help
+	  Support for UniPhier System Bus, a simple external bus.  This is
+	  needed to use on-board devices connected to UniPhier SoCs.
+
+endmenu

drivers/bus/Makefile

+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the bus drivers.
+#
+
+obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o

drivers/bus/uniphier-system-bus.c

+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <linux/types.h>
+#include <dm.h>
+
+/* System Bus Controller registers */
+#define UNIPHIER_SBC_BASE	0x100	/* base address of bank0 space */
+#define    UNIPHIER_SBC_BASE_BE		BIT(0)	/* bank_enable */
+#define UNIPHIER_SBC_CTRL0	0x200	/* timing parameter 0 of bank0 */
+#define UNIPHIER_SBC_CTRL1	0x204	/* timing parameter 1 of bank0 */
+#define UNIPHIER_SBC_CTRL2	0x208	/* timing parameter 2 of bank0 */
+#define UNIPHIER_SBC_CTRL3	0x20c	/* timing parameter 3 of bank0 */
+#define UNIPHIER_SBC_CTRL4	0x300	/* timing parameter 4 of bank0 */
+
+#define UNIPHIER_SBC_STRIDE	0x10	/* register stride to next bank */
+
+#if 1
+/* slower but LED works */
+#define SBCTRL0_VALUE	0x55450000
+#define SBCTRL1_VALUE	0x07168d00
+#define SBCTRL2_VALUE	0x34000009
+#define SBCTRL4_VALUE	0x02110110
+
+#else
+/* faster but LED does not work */
+#define SBCTRL0_VALUE	0x55450000
+#define SBCTRL1_VALUE	0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_VALUE	0x34000009
+#define SBCTRL4_VALUE	0x02110210
+#endif
+
+void uniphier_system_bus_set_reg(void __iomem *membase)
+{
+	void __iomem *bank0_base = membase;
+	void __iomem *bank1_base = membase + UNIPHIER_SBC_STRIDE;
+
+	/*
+	 * Only CS1 is connected to support card.
+	 * BKSZ[1:0] should be set to "01".
+	 */
+	writel(SBCTRL0_VALUE, bank1_base + UNIPHIER_SBC_CTRL0);
+	writel(SBCTRL1_VALUE, bank1_base + UNIPHIER_SBC_CTRL1);
+	writel(SBCTRL2_VALUE, bank1_base + UNIPHIER_SBC_CTRL2);
+	writel(SBCTRL4_VALUE, bank1_base + UNIPHIER_SBC_CTRL4);
+
+	if (readl(bank1_base + UNIPHIER_SBC_BASE) & UNIPHIER_SBC_BASE_BE) {
+		/*
+		 * Boot Swap On: boot from external NOR/SRAM
+		 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+		 *
+		 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+		 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+		 */
+		writel(0x0000bc01, bank0_base + UNIPHIER_SBC_BASE);
+	} else {
+		/*
+		 * Boot Swap Off: boot from mask ROM
+		 * 0x40000000-0x41ffffff: mask ROM
+		 * 0x42000000-0x43efffff: memory bank (31MB)
+		 * 0x43f00000-0x43ffffff: peripherals (1MB)
+		 */
+		writel(0x0000be01, bank0_base + UNIPHIER_SBC_BASE); /* dummy */
+		writel(0x0200be01, bank0_base + UNIPHIER_SBC_BASE);
+	}
+}
+
+static int uniphier_system_bus_probe(struct udevice *dev)
+{
+	fdt_addr_t base;
+	void __iomem *membase;
+
+	base = dev_read_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	membase = devm_ioremap(dev, base, SZ_1K);
+	if (!membase)
+		return -ENOMEM;
+
+	uniphier_system_bus_set_reg(membase);
+
+	return 0;
+}
+
+static const struct udevice_id uniphier_system_bus_match[] = {
+	{ .compatible = "socionext,uniphier-system-bus" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_system_bus_driver) = {
+	.name	= "uniphier-system-bus",
+	.id	= UCLASS_SIMPLE_BUS,
+	.of_match = uniphier_system_bus_match,
+	.probe = uniphier_system_bus_probe,
+};

drivers/mtd/nand/raw/denali.c

@@ -1220,6 +1220,17 @@ static int denali_multidev_fixup(struct denali_nand_info *denali)
 	return 0;
 }
 
+int denali_wait_reset_complete(struct denali_nand_info *denali)
+{
+	u32 irq_status;
+
+	irq_status = denali_wait_for_irq(denali, INTR__RST_COMP);
+	if (!(irq_status & INTR__RST_COMP))
+		return -EIO;
+
+	return 0;
+}
+
 int denali_init(struct denali_nand_info *denali)
 {
 	struct nand_chip *chip = &denali->nand;

drivers/mtd/nand/raw/denali.h

@@ -321,6 +321,7 @@ struct denali_nand_info {
 #define DENALI_CAP_DMA_64BIT			BIT(1)
 
 int denali_calc_ecc_bytes(int step_size, int strength);
+int denali_wait_reset_complete(struct denali_nand_info *denali);
 int denali_init(struct denali_nand_info *denali);
 
 #endif /* __DENALI_H__ */

drivers/mtd/nand/raw/denali_dt.c

@@ -148,6 +148,8 @@ static int denali_dt_probe(struct udevice *dev)
 	if (ret) {
 		dev_warn(dev, "Can't get reset: %d\n", ret);
 	} else {
+		reset_assert_bulk(&resets);
+		udelay(2);
 		reset_deassert_bulk(&resets);
 
 		/*
@@ -155,7 +157,11 @@ static int denali_dt_probe(struct udevice *dev)
 		 * kicked (bootstrap process). The driver must wait until it is
 		 * finished. Otherwise, it will result in unpredictable behavior.
 		 */
-		udelay(200);
+		ret = denali_wait_reset_complete(denali);
+		if (ret) {
+			dev_err(denali->dev, "reset not completed.\n");
+			return ret;
+		}
 	}
 
 	return denali_init(denali);

drivers/serial/serial_uniphier.c

@@ -7,6 +7,8 @@
 
 #include <common.h>
 #include <dm.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
 #include <linux/bug.h>
 #include <linux/io.h>
 #include <linux/serial_reg.h>
@@ -15,77 +17,72 @@
 #include <serial.h>
 #include <fdtdec.h>
 
-/*
- * Note: Register map is slightly different from that of 16550.
- */
-struct uniphier_serial {
-	u32 rx;			/* In:  Receive buffer */
-#define tx rx			/* Out: Transmit buffer */
-	u32 ier;		/* Interrupt Enable Register */
-	u32 iir;		/* In: Interrupt ID Register */
-	u32 char_fcr;		/* Charactor / FIFO Control Register */
-	u32 lcr_mcr;		/* Line/Modem Control Register */
-#define LCR_SHIFT	8
-#define LCR_MASK	(0xff << (LCR_SHIFT))
-	u32 lsr;		/* In: Line Status Register */
-	u32 msr;		/* In: Modem Status Register */
-	u32 __rsv0;
-	u32 __rsv1;
-	u32 dlr;		/* Divisor Latch Register */
-};
+#define UNIPHIER_UART_REGSHIFT		2
+
+#define UNIPHIER_UART_RX		(0 << (UNIPHIER_UART_REGSHIFT))
+#define UNIPHIER_UART_TX		UNIPHIER_UART_RX
+/* bit[15:8] = CHAR, bit[7:0] = FCR */
+#define UNIPHIER_UART_CHAR_FCR		(3 << (UNIPHIER_UART_REGSHIFT))
+#define   UNIPHIER_UART_FCR_MASK		GENMASK(7, 0)
+/* bit[15:8] = LCR, bit[7:0] = MCR */
+#define UNIPHIER_UART_LCR_MCR		(4 << (UNIPHIER_UART_REGSHIFT))
+#define   UNIPHIER_UART_LCR_MASK		GENMASK(15, 8)
+#define UNIPHIER_UART_LSR		(5 << (UNIPHIER_UART_REGSHIFT))
+/* Divisor Latch Register */
+#define UNIPHIER_UART_DLR		(9 << (UNIPHIER_UART_REGSHIFT))
 
 struct uniphier_serial_priv {
-	struct uniphier_serial __iomem *membase;
+	void __iomem *membase;
 	unsigned int uartclk;
 };
 
-#define uniphier_serial_port(dev)	\
-	((struct uniphier_serial_priv *)dev_get_priv(dev))->membase
-
 static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
 {
 	struct uniphier_serial_priv *priv = dev_get_priv(dev);
-	struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
-	const unsigned int mode_x_div = 16;
+	static const unsigned int mode_x_div = 16;
 	unsigned int divisor;
 
 	divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate);
 
-	writel(divisor, &port->dlr);
+	/* flush the trasmitter before changing hw setting */
+	while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT))
+		;
+
+	writel(divisor, priv->membase + UNIPHIER_UART_DLR);
 
 	return 0;
 }
 
 static int uniphier_serial_getc(struct udevice *dev)
 {
-	struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
+	struct uniphier_serial_priv *priv = dev_get_priv(dev);
 
-	if (!(readl(&port->lsr) & UART_LSR_DR))
+	if (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_DR))
 		return -EAGAIN;
 
-	return readl(&port->rx);
+	return readl(priv->membase + UNIPHIER_UART_RX);
 }
 
 static int uniphier_serial_putc(struct udevice *dev, const char c)
 {
-	struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
+	struct uniphier_serial_priv *priv = dev_get_priv(dev);
 
-	if (!(readl(&port->lsr) & UART_LSR_THRE))
+	if (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_THRE))
 		return -EAGAIN;
 
-	writel(c, &port->tx);
+	writel(c, priv->membase + UNIPHIER_UART_TX);
 
 	return 0;
 }
 
 static int uniphier_serial_pending(struct udevice *dev, bool input)
 {
-	struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
+	struct uniphier_serial_priv *priv = dev_get_priv(dev);
 
 	if (input)
-		return readl(&port->lsr) & UART_LSR_DR;
+		return readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_DR;
 	else
-		return !(readl(&port->lsr) & UART_LSR_THRE);
+		return !(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_THRE);
 }
 
 /*
@@ -113,7 +110,6 @@ static const struct uniphier_serial_clk_data uniphier_serial_clk_data[] = {
 static int uniphier_serial_probe(struct udevice *dev)
 {
 	struct uniphier_serial_priv *priv = dev_get_priv(dev);
-	struct uniphier_serial __iomem *port;
 	const struct uniphier_serial_clk_data *clk_data;
 	ofnode root_node;
 	fdt_addr_t base;
@@ -123,12 +119,10 @@ static int uniphier_serial_probe(struct udevice *dev)
 	if (base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	port = devm_ioremap(dev, base, SZ_64);
-	if (!port)
+	priv->membase = devm_ioremap(dev, base, SZ_64);
+	if (!priv->membase)
 		return -ENOMEM;
 
-	priv->membase = port;
-
 	root_node = ofnode_path("/");
 	clk_data = uniphier_serial_clk_data;
 	while (clk_data->compatible) {
@@ -143,10 +137,20 @@ static int uniphier_serial_probe(struct udevice *dev)
 
 	priv->uartclk = clk_data->clk_rate;
 
-	tmp = readl(&port->lcr_mcr);
-	tmp &= ~LCR_MASK;
-	tmp |= UART_LCR_WLEN8 << LCR_SHIFT;
-	writel(tmp, &port->lcr_mcr);
+	/* flush the trasmitter empty before changing hw setting */
+	while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT))
+		;
+
+	/* enable FIFO */
+	tmp = readl(priv->membase + UNIPHIER_UART_CHAR_FCR);
+	tmp &= ~UNIPHIER_UART_FCR_MASK;
+	tmp |= FIELD_PREP(UNIPHIER_UART_FCR_MASK, UART_FCR_ENABLE_FIFO);
+	writel(tmp, priv->membase + UNIPHIER_UART_CHAR_FCR);
+
+	tmp = readl(priv->membase + UNIPHIER_UART_LCR_MCR);
+	tmp &= ~UNIPHIER_UART_LCR_MASK;
+	tmp |= FIELD_PREP(UNIPHIER_UART_LCR_MASK, UART_LCR_WLEN8);
+	writel(tmp, priv->membase + UNIPHIER_UART_LCR_MCR);
 
 	return 0;
 }

include/configs/uniphier.h

@@ -41,32 +41,12 @@
 
 #define CONFIG_ARMV7_PSCI_1_0
 
-/*-----------------------------------------------------------------------
- * MMU and Cache Setting
- *----------------------------------------------------------------------*/
-
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 
 #define CONFIG_TIMESTAMP
 
-/* FLASH related */
-
-#define CONFIG_SYS_MAX_FLASH_SECT	256
 #define CONFIG_SYS_MONITOR_BASE		0
-#define CONFIG_SYS_MONITOR_LEN		0x000d0000	/* 832KB */
-#define CONFIG_SYS_FLASH_BASE		0
-
-/*
- * flash_toggle does not work for our support card.
- * We need to use flash_status_poll.
- */
-#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
-
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
-
-/* serial console configuration */
+#define CONFIG_SYS_MONITOR_LEN		0x00200000	/* 2MB */
 
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 /* Boot Argument Buffer Size */
@@ -221,7 +201,7 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)
 
 /* only for SPL */
-#define CONFIG_SPL_STACK		(0x00200000)
+#define CONFIG_SPL_STACK		(0x00100000)
 
 #define CONFIG_SYS_NAND_U_BOOT_OFFS		0x20000