Merge branch 'master' of git://git.denx.de/u-boot-net

cmd/Kconfig

@@ -1219,6 +1219,7 @@ config CMD_DNS
 
 config CMD_LINK_LOCAL
 	bool "linklocal"
+	select LIB_RAND
 	help
 	  Acquire a network IP address using the link-local protocol
 

drivers/net/Kconfig

@@ -362,6 +362,16 @@ config MPC8XX_FEC
 	  This driver implements support for the Fast Ethernet Controller
 	  on MPC8XX
 
+config SNI_AVE
+	bool "Socionext AVE Ethernet support"
+	depends on DM_ETH && ARCH_UNIPHIER
+	select PHYLIB
+	select SYSCON
+	select REGMAP
+	help
+	  This driver implements support for the Socionext AVE Ethernet
+	  controller, as found on the Socionext UniPhier family.
+
 config ETHER_ON_FEC1
 	bool "FEC1"
 	depends on MPC8XX_FEC

drivers/net/Makefile

@@ -70,3 +70,4 @@ obj-$(CONFIG_VSC9953) += vsc9953.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
 obj-$(CONFIG_FSL_PFE) += pfe_eth/
+obj-$(CONFIG_SNI_AVE) += sni_ave.o

drivers/net/cpsw.c

@@ -910,8 +910,22 @@ out:
 	return ret;
 }
 
+static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
+{
+	int timeout = CPDMA_TIMEOUT;
+
+	/* reap completed packets */
+	while (timeout-- &&
+	       (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
+		;
+
+	return timeout;
+}
+
 static void _cpsw_halt(struct cpsw_priv *priv)
 {
+	cpsw_reap_completed_packets(priv);
+
 	writel(0, priv->dma_regs + CPDMA_TXCONTROL);
 	writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 
@@ -925,18 +939,12 @@ static void _cpsw_halt(struct cpsw_priv *priv)
 
 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 {
-	void *buffer;
-	int len;
-	int timeout = CPDMA_TIMEOUT;
+	int timeout;
 
 	flush_dcache_range((unsigned long)packet,
 			   (unsigned long)packet + ALIGN(length, PKTALIGN));
 
-	/* first reap completed packets */
-	while (timeout-- &&
-		(cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0))
-		;
-
+	timeout = cpsw_reap_completed_packets(priv);
 	if (timeout == -1) {
 		printf("cpdma_process timeout\n");
 		return -ETIMEDOUT;

drivers/net/designware.c

@@ -280,6 +280,15 @@ int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
 
 	writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
 
+	/*
+	 * When a MII PHY is used, we must set the PS bit for the DMA
+	 * reset to succeed.
+	 */
+	if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
+		writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
+	else
+		writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
+
 	start = get_timer(0);
 	while (readl(&dma_p->busmode) & DMAMAC_SRST) {
 		if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {

drivers/net/mvgbe.c

@@ -15,6 +15,7 @@
 #include <net.h>
 #include <malloc.h>
 #include <miiphy.h>
+#include <wait_bit.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/types.h>
@@ -40,10 +41,24 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
 
 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+static int smi_wait_ready(struct mvgbe_device *dmvgbe)
+{
+	int ret;
+
+	ret = wait_for_bit_le32(&MVGBE_SMI_REG, MVGBE_PHY_SMI_BUSY_MASK, false,
+				MVGBE_PHY_SMI_TIMEOUT_MS, false);
+	if (ret) {
+		printf("Error: SMI busy timeout\n");
+		return ret;
+	}
+
+	return 0;
+}
+
 /*
  * smi_reg_read - miiphy_read callback function.
  *
- * Returns 16bit phy register value, or 0xffff on error
+ * Returns 16bit phy register value, or -EFAULT on error
  */
 static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
 			int reg_ofs)
@@ -74,16 +89,9 @@ static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
 		return -EFAULT;
 	}
 
-	timeout = MVGBE_PHY_SMI_TIMEOUT;
 	/* wait till the SMI is not busy */
-	do {
-		/* read smi register */
-		smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
-		if (timeout-- == 0) {
-			printf("Err..(%s) SMI busy timeout\n", __func__);
-			return -EFAULT;
-		}
-	} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
+	if (smi_wait_ready(dmvgbe) < 0)
+		return -EFAULT;
 
 	/* fill the phy address and regiser offset and read opcode */
 	smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
@@ -119,10 +127,9 @@ static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
 }
 
 /*
- * smi_reg_write - imiiphy_write callback function.
+ * smi_reg_write - miiphy_write callback function.
  *
- * Returns 0 if write succeed, -EINVAL on bad parameters
- * -ETIME on timeout
+ * Returns 0 if write succeed, -EFAULT on error
  */
 static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
 			 int reg_ofs, u16 data)
@@ -131,7 +138,6 @@ static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
 	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 	struct mvgbe_registers *regs = dmvgbe->regs;
 	u32 smi_reg;
-	u32 timeout;
 
 	/* Phyadr write request*/
 	if (phy_adr == MV_PHY_ADR_REQUEST &&
@@ -147,19 +153,12 @@ static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
 	}
 	if (reg_ofs > PHYREG_MASK) {
 		printf("Err..(%s) Invalid register offset\n", __func__);
-		return -EINVAL;
+		return -EFAULT;
 	}
 
 	/* wait till the SMI is not busy */
-	timeout = MVGBE_PHY_SMI_TIMEOUT;
-	do {
-		/* read smi register */
-		smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
-		if (timeout-- == 0) {
-			printf("Err..(%s) SMI busy timeout\n", __func__);
-			return -ETIME;
-		}
-	} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
+	if (smi_wait_ready(dmvgbe) < 0)
+		return -EFAULT;
 
 	/* fill the phy addr and reg offset and write opcode and data */
 	smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);

drivers/net/mvgbe.h

@@ -216,6 +216,7 @@
 
 /* SMI register fields */
 #define MVGBE_PHY_SMI_TIMEOUT		10000
+#define MVGBE_PHY_SMI_TIMEOUT_MS	1000
 #define MVGBE_PHY_SMI_DATA_OFFS		0	/* Data */
 #define MVGBE_PHY_SMI_DATA_MASK		(0xffff << MVGBE_PHY_SMI_DATA_OFFS)
 #define MVGBE_PHY_SMI_DEV_ADDR_OFFS	16	/* PHY device address */

drivers/net/mvneta.c

@@ -1025,6 +1025,8 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
 	if (rxq->descs == NULL)
 		return -ENOMEM;
 
+	WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
+
 	rxq->last_desc = rxq->size - 1;
 
 	/* Set Rx descriptors queue starting address */
@@ -1061,6 +1063,8 @@ static int mvneta_txq_init(struct mvneta_port *pp,
 	if (txq->descs == NULL)
 		return -ENOMEM;
 
+	WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
+
 	txq->last_desc = txq->size - 1;
 
 	/* Set maximum bandwidth for enabled TXQs */
@@ -1694,18 +1698,20 @@ static int mvneta_probe(struct udevice *dev)
 	 * be active. Make this area DMA safe by disabling the D-cache
 	 */
 	if (!buffer_loc.tx_descs) {
+		u32 size;
+
 		/* Align buffer area for descs and rx_buffers to 1MiB */
 		bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
 		mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
 						DCACHE_OFF);
 		buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
+		size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
+				ARCH_DMA_MINALIGN);
 		buffer_loc.rx_descs = (struct mvneta_rx_desc *)
-			((phys_addr_t)bd_space +
-			 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
-		buffer_loc.rx_buffers = (phys_addr_t)
-			(bd_space +
-			 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
-			 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
+			((phys_addr_t)bd_space + size);
+		size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
+				ARCH_DMA_MINALIGN);
+		buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
 	}
 
 	pp->base = (void __iomem *)pdata->iobase;

drivers/net/phy/cortina.c

@@ -284,6 +284,38 @@ int cs4340_startup(struct phy_device *phydev)
 	return 0;
 }
 
+int cs4223_phy_init(struct phy_device *phydev)
+{
+	int reg_value;
+
+	reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS);
+	if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) {
+		printf("%s CS4223 Firmware not present in EERPOM\n", __func__);
+		return -ENOSYS;
+	}
+
+	return 0;
+}
+
+int cs4223_config(struct phy_device *phydev)
+{
+	return cs4223_phy_init(phydev);
+}
+
+int cs4223_probe(struct phy_device *phydev)
+{
+	phydev->flags = PHY_FLAG_BROKEN_RESET;
+	return 0;
+}
+
+int cs4223_startup(struct phy_device *phydev)
+{
+	phydev->link = 1;
+	phydev->speed = SPEED_10000;
+	phydev->duplex = DUPLEX_FULL;
+	return 0;
+}
+
 struct phy_driver cs4340_driver = {
 	.name = "Cortina CS4315/CS4340",
 	.uid = PHY_UID_CS4340,
@@ -298,9 +330,23 @@ struct phy_driver cs4340_driver = {
 	.shutdown = &gen10g_shutdown,
 };
 
+struct phy_driver cs4223_driver = {
+	.name = "Cortina CS4223",
+	.uid = PHY_UID_CS4223,
+	.mask = 0x0ffff00f,
+	.features = PHY_10G_FEATURES,
+	.mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
+		 MDIO_DEVS_AN),
+	.config = &cs4223_config,
+	.probe	= &cs4223_probe,
+	.startup = &cs4223_startup,
+	.shutdown = &gen10g_shutdown,
+};
+
 int phy_cortina_init(void)
 {
 	phy_register(&cs4340_driver);
+	phy_register(&cs4223_driver);
 	return 0;
 }
 
@@ -319,7 +365,7 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 		return -EIO;
 	*phy_id |= (phy_reg & 0xffff);
 
-	if (*phy_id == PHY_UID_CS4340)
+	if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223))
 		return 0;
 
 	/*

drivers/net/phy/mv88e61xx.c

@@ -705,6 +705,31 @@ unforce:
 	return res;
 }
 
+static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
+{
+	int val;
+
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+	if (val < 0)
+		return val;
+
+	val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
+		 PORT_REG_PHYS_CTRL_FC_VALUE);
+	val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
+	       PORT_REG_PHYS_CTRL_PCS_AN_RST |
+	       PORT_REG_PHYS_CTRL_FC_FORCE |
+	       PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
+	       PORT_REG_PHYS_CTRL_DUPLEX_FORCE |
+	       PORT_REG_PHYS_CTRL_SPD1000;
+
+	if (port == CONFIG_MV88E61XX_CPU_PORT)
+		val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
+		       PORT_REG_PHYS_CTRL_LINK_FORCE;
+
+	return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+				   val);
+}
+
 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
 {
 	int val;
@@ -748,6 +773,11 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
 			if (val < 0)
 				return val;
 		}
+	} else {
+		val = mv88e61xx_fixed_port_setup(phydev,
+						 CONFIG_MV88E61XX_CPU_PORT);
+		if (val < 0)
+			return val;
 	}
 
 	return 0;
@@ -810,27 +840,6 @@ static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
 	return 0;
 }
 
-static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
-{
-	int val;
-
-	val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
-	if (val < 0)
-		return val;
-
-	val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
-		 PORT_REG_PHYS_CTRL_FC_VALUE);
-	val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
-	       PORT_REG_PHYS_CTRL_PCS_AN_RST |
-	       PORT_REG_PHYS_CTRL_FC_FORCE |
-	       PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
-	       PORT_REG_PHYS_CTRL_DUPLEX_FORCE |
-	       PORT_REG_PHYS_CTRL_SPD1000;
-
-	return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
-				   val);
-}
-
 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
 {
 	int val;

drivers/net/sunxi_emac.c

@@ -334,8 +334,8 @@ static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
 	enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
 	enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);
 
-	writel(enetaddr_hi, &regs->mac_a1);
-	writel(enetaddr_lo, &regs->mac_a0);
+	writel(enetaddr_hi, &regs->mac_a0);
+	writel(enetaddr_lo, &regs->mac_a1);
 
 	return 0;
 }

drivers/net/tsec.c

@@ -796,8 +796,9 @@ int tsec_probe(struct udevice *dev)
 
 	parent = ofnode_get_parent(phandle_args.node);
 	if (ofnode_valid(parent)) {
-		int reg = ofnode_read_u32_default(parent, "reg", 0);
-		priv->phyregs_sgmii = (struct tsec_mii_mng *)(reg + 0x520);
+		int reg = ofnode_get_addr_index(parent, 0);
+
+		priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
 	} else {
 		debug("No parent node for PHY?\n");
 		return -ENOENT;

drivers/net/vsc9953.c

@@ -2468,6 +2468,139 @@ void vsc9953_default_configuration(void)
 		debug("VSC9953: failed to set default aggregation code mode\n");
 }
 
+static void vcap_entry2cache_init(u32 target, u32 entry_words)
+{
+	int i;
+
+	for (i = 0; i < entry_words; i++) {
+		out_le32((unsigned int *)(VSC9953_OFFSET +
+				VSC9953_VCAP_CACHE_ENTRY_DAT(target, i)), 0x00);
+		out_le32((unsigned int *)(VSC9953_OFFSET +
+				VSC9953_VCAP_CACHE_MASK_DAT(target, i)), 0xFF);
+	}
+
+	out_le32((unsigned int *)(VSC9953_OFFSET +
+				VSC9953_VCAP_CACHE_TG_DAT(target)), 0x00);
+	out_le32((unsigned int *)(VSC9953_OFFSET +
+				  VSC9953_VCAP_CFG_MV_CFG(target)),
+		 VSC9953_VCAP_CFG_MV_CFG_SIZE(entry_words));
+}
+
+static void vcap_action2cache_init(u32 target, u32 action_words,
+				   u32 counter_words)
+{
+	int i;
+
+	for (i = 0; i < action_words; i++)
+		out_le32((unsigned int *)(VSC9953_OFFSET +
+			       VSC9953_VCAP_CACHE_ACTION_DAT(target, i)), 0x00);
+
+	for (i = 0; i < counter_words; i++)
+		out_le32((unsigned int *)(VSC9953_OFFSET +
+				  VSC9953_VCAP_CACHE_CNT_DAT(target, i)), 0x00);
+}
+
+static int vcap_cmd(u32 target, u16 ix, int cmd, int sel, int entry_count)
+{
+	u32 tgt = target;
+	u32 value = (VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(cmd) |
+		     VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(ix) |
+		     VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT);
+
+	if ((sel & TCAM_SEL_ENTRY) && ix >= entry_count)
+		return CMD_RET_FAILURE;
+
+	if (!(sel & TCAM_SEL_ENTRY))
+		value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS;
+
+	if (!(sel & TCAM_SEL_ACTION))
+		value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS;
+
+	if (!(sel & TCAM_SEL_COUNTER))
+		value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS;
+
+	out_le32((unsigned int *)(VSC9953_OFFSET +
+				VSC9953_VCAP_CFG_UPDATE_CTRL(tgt)), value);
+
+	do {
+		value = in_le32((unsigned int *)(VSC9953_OFFSET +
+				VSC9953_VCAP_CFG_UPDATE_CTRL(tgt)));
+
+	} while (value & VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT);
+
+	return CMD_RET_SUCCESS;
+}
+
+static void vsc9953_vcap_init(void)
+{
+	u32 tgt = VSC9953_ES0;
+	int cmd_ret;
+
+	/* write entries */
+	vcap_entry2cache_init(tgt, ENTRY_WORDS_ES0);
+	cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY,
+			   ENTRY_WORDS_ES0);
+	if (cmd_ret != CMD_RET_SUCCESS)
+		debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n",
+		      __LINE__);
+
+	/* write actions and counters */
+	vcap_action2cache_init(tgt, BITS_TO_DWORD(ES0_ACT_WIDTH),
+			       BITS_TO_DWORD(ES0_CNT_WIDTH));
+	out_le32((unsigned int *)(VSC9953_OFFSET +
+				  VSC9953_VCAP_CFG_MV_CFG(tgt)),
+		 VSC9953_VCAP_CFG_MV_CFG_SIZE(ES0_ACT_COUNT));
+	cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE,
+			   TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_ES0);
+	if (cmd_ret != CMD_RET_SUCCESS)
+		debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n",
+		      __LINE__);
+
+	tgt = VSC9953_IS1;
+
+	/* write entries */
+	vcap_entry2cache_init(tgt, ENTRY_WORDS_IS1);
+	cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY,
+			   ENTRY_WORDS_IS1);
+	if (cmd_ret != CMD_RET_SUCCESS)
+		debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n",
+		      __LINE__);
+
+	/* write actions and counters */
+	vcap_action2cache_init(tgt, BITS_TO_DWORD(IS1_ACT_WIDTH),
+			       BITS_TO_DWORD(IS1_CNT_WIDTH));
+	out_le32((unsigned int *)(VSC9953_OFFSET +
+				  VSC9953_VCAP_CFG_MV_CFG(tgt)),
+		 VSC9953_VCAP_CFG_MV_CFG_SIZE(IS1_ACT_COUNT));
+	cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE,
+			   TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS1);
+	if (cmd_ret != CMD_RET_SUCCESS)
+		debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n",
+		      __LINE__);
+
+	tgt = VSC9953_IS2;
+
+	/* write entries */
+	vcap_entry2cache_init(tgt, ENTRY_WORDS_IS2);
+	cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY,
+			   ENTRY_WORDS_IS2);
+	if (cmd_ret != CMD_RET_SUCCESS)
+		debug("VSC9953:%d invalid selection: TCAM_SEL_ENTRY\n",
+		      __LINE__);
+
+	/* write actions and counters */
+	vcap_action2cache_init(tgt, BITS_TO_DWORD(IS2_ACT_WIDTH),
+			       BITS_TO_DWORD(IS2_CNT_WIDTH));
+	out_le32((unsigned int *)(VSC9953_OFFSET +
+				  VSC9953_VCAP_CFG_MV_CFG(tgt)),
+		 VSC9953_VCAP_CFG_MV_CFG_SIZE(IS2_ACT_COUNT));
+	cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE,
+			   TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS2);
+	if (cmd_ret != CMD_RET_SUCCESS)
+		debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n",
+		      __LINE__);
+}
+
 void vsc9953_init(bd_t *bis)
 {
 	u32 i;
@@ -2604,6 +2737,7 @@ void vsc9953_init(bd_t *bis)
 		}
 	}
 
+	vsc9953_vcap_init();
 	vsc9953_default_configuration();
 
 #ifdef CONFIG_CMD_ETHSW

drivers/net/zynq_gem.c

@@ -185,7 +185,7 @@ struct zynq_gem_priv {
 	bool int_pcs;
 };
 
-static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
+static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
 			u32 op, u16 *data)
 {
 	u32 mgtcr;
@@ -216,10 +216,10 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
 	return 0;
 }
 
-static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
+static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
 		   u32 regnum, u16 *val)
 {
-	u32 ret;
+	int ret;
 
 	ret = phy_setup_op(priv, phy_addr, regnum,
 			   ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
@@ -231,7 +231,7 @@ static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
 	return ret;
 }
 
-static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
+static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
 		    u32 regnum, u16 data)
 {
 	debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
@@ -244,7 +244,7 @@ static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
 static int phy_detection(struct udevice *dev)
 {
 	int i;
-	u16 phyreg;
+	u16 phyreg = 0;
 	struct zynq_gem_priv *priv = dev->priv;
 
 	if (priv->phyaddr != -1) {
@@ -633,10 +633,16 @@ static int zynq_gem_probe(struct udevice *dev)
 
 	/* Align rxbuffers to ARCH_DMA_MINALIGN */
 	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
+	if (!priv->rxbuffers)
+		return -ENOMEM;
+
 	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 
 	/* Align bd_space to MMU_SECTION_SHIFT */
 	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
+	if (!bd_space)
+		return -ENOMEM;
+
 	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
 					BD_SPACE, DCACHE_OFF);
 

include/cortina.h

@@ -64,6 +64,10 @@
 #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427
 #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428
 
+/* Cortina CS4223 */
+#define CS4223_EEPROM_STATUS  0x5001
+#define CS4223_EEPROM_FIRMWARE_LOADDONE  0x1
+
 #define mseq_edc_bist_done (0x1<<0)
 #define mseq_edc_bist_fail (0x1<<8)
 

include/phy.h

@@ -65,6 +65,7 @@ typedef enum {
 	PHY_INTERFACE_MODE_XAUI,
 	PHY_INTERFACE_MODE_RXAUI,
 	PHY_INTERFACE_MODE_SFI,
+	PHY_INTERFACE_MODE_INTERNAL,
 	PHY_INTERFACE_MODE_NONE,	/* Must be last */
 
 	PHY_INTERFACE_MODE_COUNT,
@@ -87,6 +88,7 @@ static const char *phy_interface_strings[] = {
 	[PHY_INTERFACE_MODE_XAUI]		= "xaui",
 	[PHY_INTERFACE_MODE_RXAUI]		= "rxaui",
 	[PHY_INTERFACE_MODE_SFI]		= "sfi",
+	[PHY_INTERFACE_MODE_INTERNAL]		= "internal",
 	[PHY_INTERFACE_MODE_NONE]		= "",
 };
 
@@ -314,6 +316,7 @@ static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
 
 /* PHY UIDs for various PHYs that are referenced in external code */
 #define PHY_UID_CS4340  0x13e51002
+#define PHY_UID_CS4223  0x03e57003
 #define PHY_UID_TN2020	0x00a19410
 
 #endif

include/vsc9953.h

@@ -186,6 +186,76 @@
 
 #define MIIMIND_OPR_PEND		0x00000004
 
+#define VSC9953_BITMASK(offset)		((BIT(offset)) - 1)
+#define VSC9953_ENC_BITFIELD(target, offset, width) \
+	(((target) & VSC9953_BITMASK(width)) << (offset))
+
+#define VSC9953_IO_ADDR(target, offset)		((target) + (offset << 2))
+
+#define VSC9953_IO_REG(target, offset)	(VSC9953_IO_ADDR(target, offset))
+#define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri)  \
+	VSC9953_IO_REG(target, (0x2 + (ri)))
+
+#define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \
+	VSC9953_IO_REG(target, (0x42 + (ri)))
+
+#define VSC9953_VCAP_CACHE_TG_DAT(target)	VSC9953_IO_REG(target, 0xe2)
+#define VSC9953_VCAP_CFG_MV_CFG(target)	VSC9953_IO_REG(target, 0x1)
+#define VSC9953_VCAP_CFG_MV_CFG_SIZE(target) \
+	VSC9953_ENC_BITFIELD(target, 0, 16)
+
+#define VSC9953_VCAP_CFG_UPDATE_CTRL(target)	VSC9953_IO_REG(target, 0x0)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(target) \
+	VSC9953_ENC_BITFIELD(target, 22, 3)
+
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(target) \
+	VSC9953_ENC_BITFIELD(target, 3, 16)
+
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT	BIT(2)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS	BIT(21)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS	BIT(20)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS		BIT(19)
+#define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \
+	VSC9953_IO_REG(target, (0x82 + (ri)))
+
+#define VSC9953_VCAP_CACHE_CNT_DAT(target, ri)	\
+	VSC9953_IO_REG(target, (0xc2 + (ri)))
+
+#define VSC9953_PORT_OFFSET		1
+#define VSC9953_IS1_CNT			256
+#define VSC9953_IS2_CNT			1024
+#define VSC9953_ES0_CNT			1024
+
+#define BITS_TO_DWORD(in)		(1 + (((in) - 1) / 32))
+#define ENTRY_WORDS_ES0		BITS_TO_DWORD(29)
+#define ENTRY_WORDS_IS1		BITS_TO_DWORD(376)
+#define ENTRY_WORDS_IS2		BITS_TO_DWORD(376)
+#define ES0_ACT_WIDTH		BITS_TO_DWORD(91)
+#define ES0_CNT_WIDTH		BITS_TO_DWORD(1)
+#define IS1_ACT_WIDTH		BITS_TO_DWORD(320)
+#define IS1_CNT_WIDTH		BITS_TO_DWORD(4)
+#define IS2_ACT_WIDTH		BITS_TO_DWORD(103 - 2 * VSC9953_PORT_OFFSET)
+#define IS2_CNT_WIDTH		BITS_TO_DWORD(4 * 32)
+#define ES0_ACT_COUNT		(VSC9953_ES0_CNT + VSC9953_MAX_PORTS)
+#define IS1_ACT_COUNT		(VSC9953_IS1_CNT + 1)
+#define IS2_ACT_COUNT		(VSC9953_IS2_CNT + VSC9953_MAX_PORTS + 2)
+
+/* TCAM entries */
+enum tcam_sel {
+	TCAM_SEL_ENTRY   = BIT(0),
+	TCAM_SEL_ACTION  = BIT(1),
+	TCAM_SEL_COUNTER = BIT(2),
+	TCAM_SEL_ALL     = VSC9953_BITMASK(3),
+};
+
+enum tcam_cmd {
+	TCAM_CMD_WRITE      = 0,
+	TCAM_CMD_READ       = 1,
+	TCAM_CMD_MOVE_UP    = 2,
+	TCAM_CMD_MOVE_DOWN  = 3,
+	TCAM_CMD_INITIALIZE = 4,
+};
+
 struct vsc9953_mdio_info {
 	struct vsc9953_mii_mng	*regs;
 	char	*name;

net/arp.c

@@ -182,7 +182,8 @@ void arp_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len)
 		    (net_read_ip(&arp->ar_spa).s_addr & net_netmask.s_addr))
 			udelay(5000);
 #endif
-		net_send_packet((uchar *)et, eth_hdr_size + ARP_HDR_SIZE);
+		memcpy(net_tx_packet, et, eth_hdr_size + ARP_HDR_SIZE);
+		net_send_packet(net_tx_packet, eth_hdr_size + ARP_HDR_SIZE);
 		return;
 
 	case ARPOP_REPLY:		/* arp reply */

net/eth-uclass.c

@@ -395,7 +395,7 @@ int eth_initialize(void)
 	 * This is accomplished by attempting to probe each device and calling
 	 * their write_hwaddr() operation.
 	 */
-	uclass_first_device(UCLASS_ETH, &dev);
+	uclass_first_device_check(UCLASS_ETH, &dev);
 	if (!dev) {
 		printf("No ethernet found.\n");
 		bootstage_error(BOOTSTAGE_ID_NET_ETH_START);
@@ -424,7 +424,7 @@ int eth_initialize(void)
 
 			eth_write_hwaddr(dev);
 
-			uclass_next_device(&dev);
+			uclass_next_device_check(&dev);
 			num_devices++;
 		} while (dev);
 

net/net.c

@@ -393,6 +393,7 @@ void net_init(void)
 int net_loop(enum proto_t protocol)
 {
 	int ret = -EINVAL;
+	enum net_loop_state prev_net_state = net_state;
 
 	net_restarted = 0;
 	net_dev_exists = 0;
@@ -430,6 +431,7 @@ restart:
 	case 1:
 		/* network not configured */
 		eth_halt();
+		net_set_state(prev_net_state);
 		return -ENODEV;
 
 	case 2:
@@ -655,6 +657,7 @@ done:
 	net_set_udp_handler(NULL);
 	net_set_icmp_handler(NULL);
 #endif
+	net_set_state(prev_net_state);
 	return ret;
 }
 

net/nfs.c

@@ -822,6 +822,8 @@ static void nfs_handler(uchar *pkt, unsigned dest, struct in_addr sip,
 
 	case STATE_READ_REQ:
 		rlen = nfs_read_reply(pkt, len);
+		if (rlen == -NFS_RPC_DROP)
+			break;
 		net_set_timeout_handler(nfs_timeout, nfs_timeout_handler);
 		if (rlen > 0) {
 			nfs_offset += rlen;

net/ping.c

@@ -107,7 +107,8 @@ void ping_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len)
 		icmph->type = ICMP_ECHO_REPLY;
 		icmph->checksum = 0;
 		icmph->checksum = compute_ip_checksum(icmph, len - IP_HDR_SIZE);
-		net_send_packet((uchar *)et, eth_hdr_size + len);
+		memcpy(net_tx_packet, et, eth_hdr_size + len);
+		net_send_packet(net_tx_packet, eth_hdr_size + len);
 		return;
 /*	default:
 		return;*/