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体验新版 GitCode,发现更多精彩内容 >>
提交
5aaeb2a3
编写于
8月 23, 2009
作者:
G
Graeme Russ
提交者:
Tom Rix
10月 03, 2009
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure
Signed-off-by:
N
Graeme Russ
<
graeme.russ@gmail.com
>
上级
8866040f
变更
9
展开全部
隐藏空白更改
内联
并排
Showing
9 changed file
with
550 addition
and
545 deletion
+550
-545
board/eNET/eNET.c
board/eNET/eNET.c
+43
-43
board/sc520_cdp/flash.c
board/sc520_cdp/flash.c
+7
-7
board/sc520_cdp/sc520_cdp.c
board/sc520_cdp/sc520_cdp.c
+84
-87
board/sc520_spunk/sc520_spunk.c
board/sc520_spunk/sc520_spunk.c
+103
-108
cpu/i386/sc520/sc520.c
cpu/i386/sc520/sc520.c
+15
-56
cpu/i386/sc520/sc520_pci.c
cpu/i386/sc520/sc520_pci.c
+33
-33
cpu/i386/sc520/sc520_ssi.c
cpu/i386/sc520/sc520_ssi.c
+15
-13
cpu/i386/sc520/sc520_timer.c
cpu/i386/sc520/sc520_timer.c
+16
-15
include/asm-i386/ic/sc520.h
include/asm-i386/ic/sc520.h
+234
-183
未找到文件。
board/eNET/eNET.c
浏览文件 @
5aaeb2a3
...
...
@@ -46,7 +46,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
void
init_sc520_enet
(
void
)
{
/* Set CPU Speed to 100MHz */
write_mmcr_byte
(
SC520_CPUCTL
,
1
)
;
sc520_mmcr
->
cpuctl
=
0x01
;
gd
->
cpu_clk
=
100000000
;
/* wait at least one millisecond */
...
...
@@ -56,7 +56,7 @@ void init_sc520_enet (void)
"loop 0b
\n
"
:
:
:
"ecx"
);
/* turn on the SDRAM write buffer */
write_mmcr_byte
(
SC520_DBCTL
,
0x11
)
;
sc520_mmcr
->
dbctl
=
0x11
;
/* turn on the cache and disable write through */
asm
(
"movl %%cr0, %%eax
\n
"
...
...
@@ -71,51 +71,51 @@ int board_init(void)
{
init_sc520_enet
();
write_mmcr_byte
(
SC520_GPCSRT
,
0x01
)
;
/* GP Chip Select Recovery Time */
write_mmcr_byte
(
SC520_GPCSPW
,
0x07
)
;
/* GP Chip Select Pulse Width */
write_mmcr_byte
(
SC520_GPCSOFF
,
0x00
)
;
/* GP Chip Select Offset */
write_mmcr_byte
(
SC520_GPRDW
,
0x05
)
;
/* GP Read pulse width */
write_mmcr_byte
(
SC520_GPRDOFF
,
0x01
)
;
/* GP Read offset */
write_mmcr_byte
(
SC520_GPWRW
,
0x05
)
;
/* GP Write pulse width */
write_mmcr_byte
(
SC520_GPWROFF
,
0x01
)
;
/* GP Write offset */
write_mmcr_word
(
SC520_PIODATA15_0
,
0x0630
)
;
/* PIO15_PIO0 Data */
write_mmcr_word
(
SC520_PIODATA31_16
,
0x2000
)
;
/* PIO31_PIO16 Data */
write_mmcr_word
(
SC520_PIODIR31_16
,
0x2000
)
;
/* GPIO Direction */
write_mmcr_word
(
SC520_PIODIR15_0
,
0x87b5
)
;
/* GPIO Direction */
write_mmcr_word
(
SC520_PIOPFS31_16
,
0x0dfe
)
;
/* GPIO pin function 31-16 reg */
write_mmcr_word
(
SC520_PIOPFS15_0
,
0x200a
)
;
/* GPIO pin function 15-0 reg */
write_mmcr_byte
(
SC520_CSPFS
,
0x00f8
)
;
/* Chip Select Pin Function Select */
write_mmcr_long
(
SC520_PAR2
,
0x200713f8
)
;
/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
write_mmcr_long
(
SC520_PAR3
,
0x2c0712f8
)
;
/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
write_mmcr_long
(
SC520_PAR4
,
0x300711f8
)
;
/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
write_mmcr_long
(
SC520_PAR5
,
0x340710f8
)
;
/* Uart D (GPCS5, 0x010f8, 8 Bytes) */
write_mmcr_long
(
SC520_PAR6
,
0xe3ffc000
)
;
/* SDRAM (0x00000000, 128MB) */
write_mmcr_long
(
SC520_PAR7
,
0xaa3fd000
)
;
/* StrataFlash (ROMCS1, 0x10000000, 16MB) */
write_mmcr_long
(
SC520_PAR8
,
0xca3fd100
)
;
/* StrataFlash (ROMCS2, 0x11000000, 16MB) */
write_mmcr_long
(
SC520_PAR9
,
0x4203d900
)
;
/* SRAM (GPCS0, 0x19000000, 1MB) */
write_mmcr_long
(
SC520_PAR10
,
0x4e03d910
)
;
/* SRAM (GPCS3, 0x19100000, 1MB) */
write_mmcr_long
(
SC520_PAR11
,
0x50018100
)
;
/* DP-RAM (GPCS4, 0x18100000, 4kB) */
write_mmcr_long
(
SC520_PAR12
,
0x54020000
)
;
/* CFLASH1 (0x200000000, 4kB) */
write_mmcr_long
(
SC520_PAR13
,
0x5c020001
)
;
/* CFLASH2 (0x200010000, 4kB) */
/*
write_mmcr_long(SC520_PAR14, 0x8bfff800)
; */
/* BOOTCS at 0x18000000 */
/*
write_mmcr_long(SC520_PAR15, 0x38201000)
; */
/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
sc520_mmcr
->
gpcsrt
=
0x01
;
/* GP Chip Select Recovery Time */
sc520_mmcr
->
gpcspw
=
0x07
;
/* GP Chip Select Pulse Width */
sc520_mmcr
->
gpcsoff
=
0x00
;
/* GP Chip Select Offset */
sc520_mmcr
->
gprdw
=
0x05
;
/* GP Read pulse width */
sc520_mmcr
->
gprdoff
=
0x01
;
/* GP Read offset */
sc520_mmcr
->
gpwrw
=
0x05
;
/* GP Write pulse width */
sc520_mmcr
->
gpwroff
=
0x01
;
/* GP Write offset */
sc520_mmcr
->
piodata15_0
=
0x0630
;
/* PIO15_PIO0 Data */
sc520_mmcr
->
piodata31_16
=
0x2000
;
/* PIO31_PIO16 Data */
sc520_mmcr
->
piodir31_16
=
0x2000
;
/* GPIO Direction */
sc520_mmcr
->
piodir15_0
=
0x87b5
;
/* GPIO Direction */
sc520_mmcr
->
piopfs31_16
=
0x0dfe
;
/* GPIO pin function 31-16 reg */
sc520_mmcr
->
piopfs15_0
=
0x200a
;
/* GPIO pin function 15-0 reg */
sc520_mmcr
->
cspfs
=
0x00f8
;
/* Chip Select Pin Function Select */
sc520_mmcr
->
par
[
2
]
=
0x200713f8
;
/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
sc520_mmcr
->
par
[
3
]
=
0x2c0712f8
;
/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
sc520_mmcr
->
par
[
4
]
=
0x300711f8
;
/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
sc520_mmcr
->
par
[
5
]
=
0x340710f8
;
/* Uart D (GPCS5, 0x010f8, 8 Bytes) */
sc520_mmcr
->
par
[
6
]
=
0xe3ffc000
;
/* SDRAM (0x00000000, 128MB) */
sc520_mmcr
->
par
[
7
]
=
0xaa3fd000
;
/* StrataFlash (ROMCS1, 0x10000000, 16MB) */
sc520_mmcr
->
par
[
8
]
=
0xca3fd100
;
/* StrataFlash (ROMCS2, 0x11000000, 16MB) */
sc520_mmcr
->
par
[
9
]
=
0x4203d900
;
/* SRAM (GPCS0, 0x19000000, 1MB) */
sc520_mmcr
->
par
[
10
]
=
0x4e03d910
;
/* SRAM (GPCS3, 0x19100000, 1MB) */
sc520_mmcr
->
par
[
11
]
=
0x50018100
;
/* DP-RAM (GPCS4, 0x18100000, 4kB) */
sc520_mmcr
->
par
[
12
]
=
0x54020000
;
/* CFLASH1 (0x200000000, 4kB) */
sc520_mmcr
->
par
[
13
]
=
0x5c020001
;
/* CFLASH2 (0x200010000, 4kB) */
/*
sc520_mmcr->par14 = 0x8bfff800
; */
/* BOOTCS at 0x18000000 */
/*
sc520_mmcr->par15 = 0x38201000
; */
/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
/* Disable Watchdog */
write_mmcr_word
(
0x0cb0
,
0x3333
)
;
write_mmcr_word
(
0x0cb0
,
0xcccc
)
;
write_mmcr_word
(
0x0cb0
,
0x0000
)
;
sc520_mmcr
->
wdtmrctl
=
0x3333
;
sc520_mmcr
->
wdtmrctl
=
0xcccc
;
sc520_mmcr
->
wdtmrctl
=
0x0000
;
/* Chip Select Configuration */
write_mmcr_word
(
SC520_BOOTCSCTL
,
0x0033
)
;
write_mmcr_word
(
SC520_ROMCS1CTL
,
0x0615
)
;
write_mmcr_word
(
SC520_ROMCS2CTL
,
0x0615
)
;
write_mmcr_byte
(
SC520_ADDDECCTL
,
0x02
)
;
write_mmcr_byte
(
SC520_UART1CTL
,
0x07
)
;
write_mmcr_byte
(
SC520_SYSARBCTL
,
0x06
)
;
write_mmcr_word
(
SC520_SYSARBMENB
,
0x0003
)
;
sc520_mmcr
->
bootcsctl
=
0x0033
;
sc520_mmcr
->
romcs1ctl
=
0x0615
;
sc520_mmcr
->
romcs2ctl
=
0x0615
;
sc520_mmcr
->
adddecctl
=
0x02
;
sc520_mmcr
->
uart1ctl
=
0x07
;
sc520_mmcr
->
sysarbctl
=
0x06
;
sc520_mmcr
->
sysarbmenb
=
0x0003
;
/* Crystal is 33.000MHz */
gd
->
bus_clk
=
33000000
;
...
...
board/sc520_cdp/flash.c
浏览文件 @
5aaeb2a3
...
...
@@ -337,12 +337,12 @@ done: ;
unsigned micro; \
unsigned milli=0; \
\
micro =
*(volatile u16*)(0xfffef000+SC520_SWTMRMILLI)
; \
micro =
sc520_mmcr->swtmrmilli
; \
\
for (;;) { \
\
milli +=
*(volatile u16*)(0xfffef000+SC520_SWTMRMILLI)
; \
micro =
*(volatile u16*)(0xfffef000+SC520_SWTMRMICRO)
; \
milli +=
sc520_mmcr->swtmrmilli
; \
micro =
sc520_mmcr->swtmrmicro
; \
\
if ((delay) <= (micro + (milli * 1000))) { \
break; \
...
...
@@ -364,12 +364,12 @@ static u32 _amd_erase_flash(u32 addr, u32 sector)
/* Sector erase command comes last */
*
(
volatile
u32
*
)(
addr
+
sector
)
=
0x30303030
;
elapsed
=
*
(
volatile
u16
*
)(
0xfffef000
+
SC520_SWTMRMILLI
)
;
/* dummy read */
elapsed
=
sc520_mmcr
->
swtmrmilli
;
/* dummy read */
elapsed
=
0
;
__udelay
(
50
);
while
(((
*
(
volatile
u32
*
)(
addr
+
sector
))
&
0x80808080
)
!=
0x80808080
)
{
elapsed
+=
*
(
volatile
u16
*
)(
0xfffef000
+
SC520_SWTMRMILLI
)
;
elapsed
+=
sc520_mmcr
->
swtmrmilli
;
if
(
elapsed
>
((
CONFIG_SYS_FLASH_ERASE_TOUT
/
CONFIG_SYS_HZ
)
*
1000
))
{
*
(
volatile
u32
*
)(
addr
)
=
0xf0f0f0f0
;
return
1
;
...
...
@@ -487,12 +487,12 @@ static int _amd_write_word(unsigned start, unsigned dest, unsigned data)
dest2
[
0
]
=
data
;
elapsed
=
*
(
volatile
u16
*
)(
0xfffef000
+
SC520_SWTMRMILLI
)
;
/* dummy read */
elapsed
=
sc520_mmcr
->
swtmrmilli
;
/* dummy read */
elapsed
=
0
;
/* data polling for D7 */
while
((
dest2
[
0
]
&
0x80808080
)
!=
(
data2
[
0
]
&
0x80808080
))
{
elapsed
+=
*
(
volatile
u16
*
)(
0xfffef000
+
SC520_SWTMRMILLI
)
;
elapsed
+=
sc520_mmcr
->
swtmrmilli
;
if
(
elapsed
>
((
CONFIG_SYS_FLASH_WRITE_TOUT
/
CONFIG_SYS_HZ
)
*
1000
))
{
addr2
[
0
]
=
0xf0f0f0f0
;
return
1
;
...
...
board/sc520_cdp/sc520_cdp.c
浏览文件 @
5aaeb2a3
...
...
@@ -58,61 +58,60 @@ DECLARE_GLOBAL_DATA_PTR;
static
void
irq_init
(
void
)
{
/* disable global interrupt mode */
write_mmcr_byte
(
SC520_PICICR
,
0x40
)
;
sc520_mmcr
->
picicr
=
0x40
;
/* set all irqs to edge */
write_mmcr_byte
(
SC520_MPICMODE
,
0x00
)
;
write_mmcr_byte
(
SC520_SL1PICMODE
,
0x00
)
;
write_mmcr_byte
(
SC520_SL2PICMODE
,
0x00
)
;
sc520_mmcr
->
pic_mode
[
0
]
=
0x00
;
sc520_mmcr
->
pic_mode
[
1
]
=
0x00
;
sc520_mmcr
->
pic_mode
[
2
]
=
0x00
;
/* active low polarity on PIC interrupt pins,
* active high polarity on all other irq pins */
write_mmcr_word
(
SC520_INTPINPOL
,
0x0000
)
;
sc520_mmcr
->
intpinpol
=
0x0000
;
/* set irq number mapping */
write_mmcr_byte
(
SC520_GPTMR0MAP
,
SC520_IRQ_DISABLED
);
/* disable GP timer 0 INT */
write_mmcr_byte
(
SC520_GPTMR1MAP
,
SC520_IRQ_DISABLED
);
/* disable GP timer 1 INT */
write_mmcr_byte
(
SC520_GPTMR2MAP
,
SC520_IRQ_DISABLED
);
/* disable GP timer 2 INT */
write_mmcr_byte
(
SC520_PIT0MAP
,
SC520_IRQ0
);
/* Set PIT timer 0 INT to IRQ0 */
write_mmcr_byte
(
SC520_PIT1MAP
,
SC520_IRQ_DISABLED
);
/* disable PIT timer 1 INT */
write_mmcr_byte
(
SC520_PIT2MAP
,
SC520_IRQ_DISABLED
);
/* disable PIT timer 2 INT */
write_mmcr_byte
(
SC520_PCIINTAMAP
,
SC520_IRQ_DISABLED
);
/* disable PCI INT A */
write_mmcr_byte
(
SC520_PCIINTBMAP
,
SC520_IRQ_DISABLED
);
/* disable PCI INT B */
write_mmcr_byte
(
SC520_PCIINTCMAP
,
SC520_IRQ_DISABLED
);
/* disable PCI INT C */
write_mmcr_byte
(
SC520_PCIINTDMAP
,
SC520_IRQ_DISABLED
);
/* disable PCI INT D */
write_mmcr_byte
(
SC520_DMABCINTMAP
,
SC520_IRQ_DISABLED
);
/* disable DMA INT */
write_mmcr_byte
(
SC520_SSIMAP
,
SC520_IRQ_DISABLED
);
/* disable Synchronius serial INT */
write_mmcr_byte
(
SC520_WDTMAP
,
SC520_IRQ_DISABLED
);
/* disable Watchdog INT */
write_mmcr_byte
(
SC520_RTCMAP
,
SC520_IRQ8
);
/* Set RTC int to 8 */
write_mmcr_byte
(
SC520_WPVMAP
,
SC520_IRQ_DISABLED
);
/* disable write protect INT */
write_mmcr_byte
(
SC520_ICEMAP
,
SC520_IRQ1
);
/* Set ICE Debug Serielport INT to IRQ1 */
write_mmcr_byte
(
SC520_FERRMAP
,
SC520_IRQ13
);
/* Set FP error INT to IRQ13 */
sc520_mmcr
->
gp_tmr_int_map
[
0
]
=
SC520_IRQ_DISABLED
;
/* disable GP timer 0 INT */
sc520_mmcr
->
gp_tmr_int_map
[
1
]
=
SC520_IRQ_DISABLED
;
/* disable GP timer 1 INT */
sc520_mmcr
->
gp_tmr_int_map
[
2
]
=
SC520_IRQ_DISABLED
;
/* disable GP timer 2 INT */
sc520_mmcr
->
pit_int_map
[
0
]
=
SC520_IRQ0
;
/* Set PIT timer 0 INT to IRQ0 */
sc520_mmcr
->
pit_int_map
[
1
]
=
SC520_IRQ_DISABLED
;
/* disable PIT timer 1 INT */
sc520_mmcr
->
pit_int_map
[
2
]
=
SC520_IRQ_DISABLED
;
/* disable PIT timer 2 INT */
sc520_mmcr
->
pci_int_map
[
0
]
=
SC520_IRQ_DISABLED
;
/* disable PCI INT A */
sc520_mmcr
->
pci_int_map
[
1
]
=
SC520_IRQ_DISABLED
;
/* disable PCI INT B */
sc520_mmcr
->
pci_int_map
[
2
]
=
SC520_IRQ_DISABLED
;
/* disable PCI INT C */
sc520_mmcr
->
pci_int_map
[
3
]
=
SC520_IRQ_DISABLED
;
/* disable PCI INT D */
sc520_mmcr
->
dmabcintmap
=
SC520_IRQ_DISABLED
;
/* disable DMA INT */
sc520_mmcr
->
ssimap
=
SC520_IRQ_DISABLED
;
/* disable Synchronius serial INT */
sc520_mmcr
->
wdtmap
=
SC520_IRQ_DISABLED
;
/* disable Watchdog INT */
sc520_mmcr
->
rtcmap
=
SC520_IRQ8
;
/* Set RTC int to 8 */
sc520_mmcr
->
wpvmap
=
SC520_IRQ_DISABLED
;
/* disable write protect INT */
sc520_mmcr
->
icemap
=
SC520_IRQ1
;
/* Set ICE Debug Serielport INT to IRQ1 */
sc520_mmcr
->
ferrmap
=
SC520_IRQ13
;
/* Set FP error INT to IRQ13 */
if
(
CONFIG_SYS_USE_SIO_UART
)
{
write_mmcr_byte
(
SC520_UART1MAP
,
SC520_IRQ_DISABLED
);
/* disable internal UART1 INT */
write_mmcr_byte
(
SC520_UART2MAP
,
SC520_IRQ_DISABLED
);
/* disable internal UART2 INT */
write_mmcr_byte
(
SC520_GP3IMAP
,
SC520_IRQ3
);
/* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
write_mmcr_byte
(
SC520_GP4IMAP
,
SC520_IRQ4
);
/* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
sc520_mmcr
->
uart_int_map
[
0
]
=
SC520_IRQ_DISABLED
;
/* disable internal UART1 INT */
sc520_mmcr
->
uart_int_map
[
1
]
=
SC520_IRQ_DISABLED
;
/* disable internal UART2 INT */
sc520_mmcr
->
gp_int_map
[
3
]
=
SC520_IRQ3
;
/* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
sc520_mmcr
->
gp_int_map
[
4
]
=
SC520_IRQ4
;
/* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
}
else
{
write_mmcr_byte
(
SC520_UART1MAP
,
SC520_IRQ4
);
/* Set internal UART2 INT to IRQ4 */
write_mmcr_byte
(
SC520_UART2MAP
,
SC520_IRQ3
);
/* Set internal UART2 INT to IRQ3 */
write_mmcr_byte
(
SC520_GP3IMAP
,
SC520_IRQ_DISABLED
);
/* disable GPIRQ3 (ISA IRQ3) */
write_mmcr_byte
(
SC520_GP4IMAP
,
SC520_IRQ_DISABLED
);
/* disable GPIRQ4 (ISA IRQ4) */
sc520_mmcr
->
uart_int_map
[
0
]
=
SC520_IRQ4
;
/* Set internal UART2 INT to IRQ4 */
sc520_mmcr
->
uart_int_map
[
1
]
=
SC520_IRQ3
;
/* Set internal UART2 INT to IRQ3 */
sc520_mmcr
->
gp_int_map
[
3
]
=
SC520_IRQ_DISABLED
;
/* disable GPIRQ3 (ISA IRQ3) */
sc520_mmcr
->
gp_int_map
[
4
]
=
SC520_IRQ_DISABLED
;
/* disable GPIRQ4 (ISA IRQ4) */
}
write_mmcr_byte
(
SC520_GP1IMAP
,
SC520_IRQ1
);
/* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
write_mmcr_byte
(
SC520_GP5IMAP
,
SC520_IRQ5
);
/* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
write_mmcr_byte
(
SC520_GP6IMAP
,
SC520_IRQ6
);
/* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
write_mmcr_byte
(
SC520_GP7IMAP
,
SC520_IRQ7
);
/* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
write_mmcr_byte
(
SC520_GP8IMAP
,
SC520_IRQ8
);
/* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
write_mmcr_byte
(
SC520_GP9IMAP
,
SC520_IRQ9
);
/* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
write_mmcr_byte
(
SC520_GP0IMAP
,
SC520_IRQ11
);
/* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
write_mmcr_byte
(
SC520_GP2IMAP
,
SC520_IRQ12
);
/* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
write_mmcr_byte
(
SC520_GP10IMAP
,
SC520_IRQ14
);
/* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
write_mmcr_word
(
SC520_PCIHOSTMAP
,
0x11f
);
/* Map PCI hostbridge INT to NMI */
write_mmcr_word
(
SC520_ECCMAP
,
0x100
);
/* Map SDRAM ECC failure INT to NMI */
sc520_mmcr
->
gp_int_map
[
1
]
=
SC520_IRQ1
;
/* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
sc520_mmcr
->
gp_int_map
[
5
]
=
SC520_IRQ5
;
/* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
sc520_mmcr
->
gp_int_map
[
6
]
=
SC520_IRQ6
;
/* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
sc520_mmcr
->
gp_int_map
[
7
]
=
SC520_IRQ7
;
/* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
sc520_mmcr
->
gp_int_map
[
8
]
=
SC520_IRQ8
;
/* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
sc520_mmcr
->
gp_int_map
[
9
]
=
SC520_IRQ9
;
/* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
sc520_mmcr
->
gp_int_map
[
0
]
=
SC520_IRQ11
;
/* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
sc520_mmcr
->
gp_int_map
[
2
]
=
SC520_IRQ12
;
/* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
sc520_mmcr
->
gp_int_map
[
10
]
=
SC520_IRQ14
;
/* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
sc520_mmcr
->
pcihostmap
=
0x11f
;
/* Map PCI hostbridge INT to NMI */
sc520_mmcr
->
eccmap
=
0x100
;
/* Map SDRAM ECC failure INT to NMI */
}
#ifdef CONFIG_PCI
...
...
@@ -235,23 +234,22 @@ static void bus_init(void)
{
/* set up the GP IO pins */
write_mmcr_word
(
SC520_PIOPFS31_16
,
0xf7ff
);
/* set the GPIO pin function 31-16 reg */
write_mmcr_word
(
SC520_PIOPFS15_0
,
0xffff
);
/* set the GPIO pin function 15-0 reg */
write_mmcr_byte
(
SC520_CSPFS
,
0xf8
);
/* set the CS pin function reg */
write_mmcr_byte
(
SC520_CLKSEL
,
0x70
);
write_mmcr_byte
(
SC520_GPCSRT
,
1
);
/* set the GP CS offset */
write_mmcr_byte
(
SC520_GPCSPW
,
3
);
/* set the GP CS pulse width */
write_mmcr_byte
(
SC520_GPCSOFF
,
1
);
/* set the GP CS offset */
write_mmcr_byte
(
SC520_GPRDW
,
3
);
/* set the RD pulse width */
write_mmcr_byte
(
SC520_GPRDOFF
,
1
);
/* set the GP RD offset */
write_mmcr_byte
(
SC520_GPWRW
,
3
);
/* set the GP WR pulse width */
write_mmcr_byte
(
SC520_GPWROFF
,
1
);
/* set the GP WR offset */
write_mmcr_word
(
SC520_BOOTCSCTL
,
0x1823
);
/* set up timing of BOOTCS */
write_mmcr_word
(
SC520_ROMCS1CTL
,
0x1823
);
/* set up timing of ROMCS1 */
write_mmcr_word
(
SC520_ROMCS2CTL
,
0x1823
);
/* set up timing of ROMCS2 */
sc520_mmcr
->
piopfs31_16
=
0xf7ff
;
/* set the GPIO pin function 31-16 reg */
sc520_mmcr
->
piopfs15_0
=
0xffff
;
/* set the GPIO pin function 15-0 reg */
sc520_mmcr
->
cspfs
=
0xf8
;
/* set the CS pin function reg */
sc520_mmcr
->
clksel
=
0x70
;
sc520_mmcr
->
gpcsrt
=
1
;
/* set the GP CS offset */
sc520_mmcr
->
gpcspw
=
3
;
/* set the GP CS pulse width */
sc520_mmcr
->
gpcsoff
=
1
;
/* set the GP CS offset */
sc520_mmcr
->
gprdw
=
3
;
/* set the RD pulse width */
sc520_mmcr
->
gprdoff
=
1
;
/* set the GP RD offset */
sc520_mmcr
->
gpwrw
=
3
;
/* set the GP WR pulse width */
sc520_mmcr
->
gpwroff
=
1
;
/* set the GP WR offset */
sc520_mmcr
->
bootcsctl
=
0x1823
;
/* set up timing of BOOTCS */
sc520_mmcr
->
romcs1ctl
=
0x1823
;
/* set up timing of ROMCS1 */
sc520_mmcr
->
romcs2ctl
=
0x1823
;
/* set up timing of ROMCS2 */
/* adjust the memory map:
* by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
...
...
@@ -260,31 +258,31 @@ static void bus_init(void)
/* SRAM = GPCS3 128k @ d0000-effff*/
write_mmcr_long
(
SC520_PAR2
,
0x4e00400d
)
;
sc520_mmcr
->
par
[
2
]
=
0x4e00400d
;
/* IDE0 = GPCS6 1f0-1f7 */
write_mmcr_long
(
SC520_PAR3
,
0x380801f0
)
;
sc520_mmcr
->
par
[
3
]
=
0x380801f0
;
/* IDE1 = GPCS7 3f6 */
write_mmcr_long
(
SC520_PAR4
,
0x3c0003f6
)
;
sc520_mmcr
->
par
[
4
]
=
0x3c0003f6
;
/* bootcs */
write_mmcr_long
(
SC520_PAR12
,
0x8bffe800
)
;
sc520_mmcr
->
par
[
12
]
=
0x8bffe800
;
/* romcs2 */
write_mmcr_long
(
SC520_PAR13
,
0xcbfff000
)
;
sc520_mmcr
->
par
[
13
]
=
0xcbfff000
;
/* romcs1 */
write_mmcr_long
(
SC520_PAR14
,
0xabfff800
)
;
sc520_mmcr
->
par
[
14
]
=
0xabfff800
;
/* 680 LEDS */
write_mmcr_long
(
SC520_PAR15
,
0x30000640
)
;
sc520_mmcr
->
par
[
15
]
=
0x30000640
;
write_mmcr_byte
(
SC520_ADDDECCTL
,
0
)
;
sc520_mmcr
->
adddecctl
=
0
;
asm
(
"wbinvd
\n
"
);
/* Flush cache, req. after setting the unchached attribute ona PAR */
if
(
CONFIG_SYS_USE_SIO_UART
)
{
write_mmcr_byte
(
SC520_ADDDECCTL
,
read_mmcr_byte
(
SC520_ADDDECCTL
)
|
UART2_DIS
|
UART1_DIS
)
;
sc520_mmcr
->
adddecctl
=
sc520_mmcr
->
adddecctl
|
UART2_DIS
|
UART1_DIS
;
setup_ali_sio
(
1
);
}
else
{
write_mmcr_byte
(
SC520_ADDDECCTL
,
read_mmcr_byte
(
SC520_ADDDECCTL
)
&
~
(
UART2_DIS
|
UART1_DIS
)
);
sc520_mmcr
->
adddecctl
=
sc520_mmcr
->
adddecctl
&
~
(
UART2_DIS
|
UART1_DIS
);
setup_ali_sio
(
0
);
silence_uart
(
0x3e8
);
silence_uart
(
0x2e8
);
...
...
@@ -352,7 +350,7 @@ u32 isa_map_rom(u32 bus_addr, int size)
PRINTF
(
"setting PAR11 to %x
\n
"
,
par
);
/* Map rom 0x10000 with PAR1 */
write_mmcr_long
(
SC520_PAR11
,
par
)
;
sc520_mmcr
->
par
[
11
]
=
par
;
return
bus_addr
;
}
...
...
@@ -364,8 +362,8 @@ u32 isa_map_rom(u32 bus_addr, int size)
void
isa_unmap_rom
(
u32
addr
)
{
PRINTF
(
"isa_unmap_rom asked to unmap %x"
,
addr
);
if
((
addr
>>
12
)
==
(
read_mmcr_long
(
SC520_PAR11
)
&
0x3ffff
))
{
write_mmcr_long
(
SC520_PAR11
,
0
)
;
if
((
addr
>>
12
)
==
(
sc520_mmcr
->
par
[
11
]
&
0x3ffff
))
{
sc520_mmcr
->
par
[
11
]
=
0
;
PRINTF
(
" done
\n
"
);
return
;
}
...
...
@@ -401,7 +399,7 @@ u32 pci_get_rom_window(struct pci_controller *hose, int size)
PRINTF
(
"setting PAR1 to %x
\n
"
,
par
);
/* Map rom 0x10000 with PAR1 */
write_mmcr_long
(
SC520_PAR1
,
par
)
;
sc520_mmcr
->
par
[
1
]
=
par
;
return
PCI_ROM_TEMP_SPACE
;
}
...
...
@@ -414,7 +412,7 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
{
PRINTF
(
"pci_remove_rom_window: %x"
,
addr
);
if
(
addr
==
PCI_ROM_TEMP_SPACE
)
{
write_mmcr_long
(
SC520_PAR1
,
0
)
;
sc520_mmcr
->
par
[
1
]
=
0
;
PRINTF
(
" done
\n
"
);
return
;
}
...
...
@@ -432,11 +430,10 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
int
pci_enable_legacy_video_ports
(
struct
pci_controller
*
hose
)
{
/* Map video memory to 0xa0000*/
write_mmcr_long
(
SC520_PAR0
,
0x7200400a
)
;
sc520_mmcr
->
par
[
0
]
=
0x7200400a
;
/* forward all I/O accesses to PCI */
write_mmcr_byte
(
SC520_ADDDECCTL
,
read_mmcr_byte
(
SC520_ADDDECCTL
)
|
IO_HOLE_DEST_PCI
);
sc520_mmcr
->
adddecctl
=
sc520_mmcr
->
adddecctl
|
IO_HOLE_DEST_PCI
;
/* so we map away all io ports to pci (only way to access pci io
...
...
@@ -446,32 +443,32 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose)
*/
/* bring 0x100 - 0x1ef back to ISA using PAR5 */
write_mmcr_long
(
SC520_PAR5
,
0x30ef0100
)
;
sc520_mmcr
->
par
[
5
]
=
0x30ef0100
;
/* IDE use 1f0-1f7 */
/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
write_mmcr_long
(
SC520_PAR6
,
0x30ff01f8
)
;
sc520_mmcr
->
par
[
6
]
=
0x30ff01f8
;
/* com2 use 2f8-2ff */
/* bring 0x300 - 0x3af back to ISA using PAR7 */
write_mmcr_long
(
SC520_PAR7
,
0x30af0300
)
;
sc520_mmcr
->
par
[
7
]
=
0x30af0300
;
/* vga use 3b0-3bb */
/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
write_mmcr_long
(
SC520_PAR8
,
0x300303bc
)
;
sc520_mmcr
->
par
[
8
]
=
0x300303bc
;
/* vga use 3c0-3df */
/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
write_mmcr_long
(
SC520_PAR9
,
0x301503e0
)
;
sc520_mmcr
->
par
[
9
]
=
0x301503e0
;
/* ide use 3f6 */
/* bring 0x3f7 back to ISA using PAR10 */
write_mmcr_long
(
SC520_PAR10
,
0x300003f7
)
;
sc520_mmcr
->
par
[
10
]
=
0x300003f7
;
/* com1 use 3f8-3ff */
...
...
@@ -490,12 +487,12 @@ int board_init(void)
irq_init
();
/* max drive current on SDRAM */
write_mmcr_word
(
SC520_DSCTL
,
0x0100
)
;
sc520_mmcr
->
dsctl
=
0x0100
;
/* enter debug mode after next reset (only if jumper is also set) */
write_mmcr_byte
(
SC520_RESCFG
,
0x08
)
;
sc520_mmcr
->
rescfg
=
0x08
;
/* configure the software timer to 33.333MHz */
write_mmcr_byte
(
SC520_SWTMRCFG
,
0
)
;
sc520_mmcr
->
swtmrcfg
=
0
;
gd
->
bus_clk
=
33333000
;
return
0
;
...
...
board/sc520_spunk/sc520_spunk.c
浏览文件 @
5aaeb2a3
...
...
@@ -47,53 +47,54 @@ DECLARE_GLOBAL_DATA_PTR;
static
void
irq_init
(
void
)
{
/* disable global interrupt mode */
write_mmcr_byte
(
SC520_PICICR
,
0x40
)
;
sc520_mmcr
->
picicr
=
0x40
;
/* set all irqs to edge */
write_mmcr_byte
(
SC520_MPICMODE
,
0x00
)
;
write_mmcr_byte
(
SC520_SL1PICMODE
,
0x00
)
;
write_mmcr_byte
(
SC520_SL2PICMODE
,
0x00
)
;
sc520_mmcr
->
pic_mode
[
0
]
=
0x00
;
sc520_mmcr
->
pic_mode
[
1
]
=
0x00
;
sc520_mmcr
->
pic_mode
[
2
]
=
0x00
;
/* active low polarity on PIC interrupt pins,
* active high polarity on all other irq pins */
write_mmcr_word
(
SC520_INTPINPOL
,
0x0000
)
;
sc520_mmcr
->
intpinpol
=
0x0000
;
/* set irq number mapping */
write_mmcr_byte
(
SC520_GPTMR0MAP
,
SC520_IRQ_DISABLED
);
/* disable GP timer 0 INT */
write_mmcr_byte
(
SC520_GPTMR1MAP
,
SC520_IRQ_DISABLED
);
/* disable GP timer 1 INT */
write_mmcr_byte
(
SC520_GPTMR2MAP
,
SC520_IRQ_DISABLED
);
/* disable GP timer 2 INT */
write_mmcr_byte
(
SC520_PIT0MAP
,
SC520_IRQ0
);
/* Set PIT timer 0 INT to IRQ0 */
write_mmcr_byte
(
SC520_PIT1MAP
,
SC520_IRQ_DISABLED
);
/* disable PIT timer 1 INT */
write_mmcr_byte
(
SC520_PIT2MAP
,
SC520_IRQ_DISABLED
);
/* disable PIT timer 2 INT */
write_mmcr_byte
(
SC520_PCIINTAMAP
,
SC520_IRQ_DISABLED
);
/* disable PCI INT A */
write_mmcr_byte
(
SC520_PCIINTBMAP
,
SC520_IRQ_DISABLED
);
/* disable PCI INT B */
write_mmcr_byte
(
SC520_PCIINTCMAP
,
SC520_IRQ_DISABLED
);
/* disable PCI INT C */
write_mmcr_byte
(
SC520_PCIINTDMAP
,
SC520_IRQ_DISABLED
);
/* disable PCI INT D */
write_mmcr_byte
(
SC520_DMABCINTMAP
,
SC520_IRQ_DISABLED
);
/* disable DMA INT */
write_mmcr_byte
(
SC520_SSIMAP
,
SC520_IRQ6
);
/* Set Synchronius serial INT to IRQ6*/
write_mmcr_byte
(
SC520_WDTMAP
,
SC520_IRQ_DISABLED
);
/* disable Watchdog INT */
write_mmcr_byte
(
SC520_RTCMAP
,
SC520_IRQ8
);
/* Set RTC int to 8 */
write_mmcr_byte
(
SC520_WPVMAP
,
SC520_IRQ_DISABLED
);
/* disable write protect INT */
write_mmcr_byte
(
SC520_ICEMAP
,
SC520_IRQ1
);
/* Set ICE Debug Serielport INT to IRQ1 */
write_mmcr_byte
(
SC520_FERRMAP
,
SC520_IRQ13
);
/* Set FP error INT to IRQ13 */
write_mmcr_byte
(
SC520_UART1MAP
,
SC520_IRQ4
);
/* Set internal UART2 INT to IRQ4 */
write_mmcr_byte
(
SC520_UART2MAP
,
SC520_IRQ3
);
/* Set internal UART2 INT to IRQ3 */
write_mmcr_byte
(
SC520_GP0IMAP
,
SC520_IRQ7
);
/* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
write_mmcr_byte
(
SC520_GP1IMAP
,
SC520_IRQ14
);
/* Set GPIRQ1 (CF IRQ) to IRQ14 */
write_mmcr_byte
(
SC520_GP3IMAP
,
SC520_IRQ5
);
/* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
write_mmcr_byte
(
SC520_GP4IMAP
,
SC520_IRQ_DISABLED
);
/* disbale GIRQ4 ( IRR IRQ ) */
write_mmcr_byte
(
SC520_GP5IMAP
,
SC520_IRQ_DISABLED
);
/* disable GPIRQ5 */
write_mmcr_byte
(
SC520_GP6IMAP
,
SC520_IRQ_DISABLED
);
/* disable GPIRQ6 */
write_mmcr_byte
(
SC520_GP7IMAP
,
SC520_IRQ_DISABLED
);
/* disable GPIRQ7 */
write_mmcr_byte
(
SC520_GP8IMAP
,
SC520_IRQ_DISABLED
);
/* disable GPIRQ8 */
write_mmcr_byte
(
SC520_GP9IMAP
,
SC520_IRQ_DISABLED
);
/* disable GPIRQ9 */
write_mmcr_byte
(
SC520_GP2IMAP
,
SC520_IRQ_DISABLED
);
/* disable GPIRQ2 */
write_mmcr_byte
(
SC520_GP10IMAP
,
SC520_IRQ_DISABLED
);
/* disable GPIRQ10 */
write_mmcr_word
(
SC520_PCIHOSTMAP
,
0x11f
);
/* Map PCI hostbridge INT to NMI */
write_mmcr_word
(
SC520_ECCMAP
,
0x100
);
/* Map SDRAM ECC failure INT to NMI */
sc520_mmcr
->
gp_tmr_int_map
[
0
]
=
SC520_IRQ_DISABLED
;
/* disable GP timer 0 INT */
sc520_mmcr
->
gp_tmr_int_map
[
1
]
=
SC520_IRQ_DISABLED
;
/* disable GP timer 1 INT */
sc520_mmcr
->
gp_tmr_int_map
[
2
]
=
SC520_IRQ_DISABLED
;
/* disable GP timer 2 INT */
sc520_mmcr
->
pit_int_map
[
0
]
=
SC520_IRQ0
;
/* Set PIT timer 0 INT to IRQ0 */
sc520_mmcr
->
pit_int_map
[
1
]
=
SC520_IRQ_DISABLED
;
/* disable PIT timer 1 INT */
sc520_mmcr
->
pit_int_map
[
2
]
=
SC520_IRQ_DISABLED
;
/* disable PIT timer 2 INT */
sc520_mmcr
->
pci_int_map
[
0
]
=
SC520_IRQ_DISABLED
;
/* disable PCI INT A */
sc520_mmcr
->
pci_int_map
[
1
]
=
SC520_IRQ_DISABLED
;
/* disable PCI INT B */
sc520_mmcr
->
pci_int_map
[
2
]
=
SC520_IRQ_DISABLED
;
/* disable PCI INT C */
sc520_mmcr
->
pci_int_map
[
3
]
=
SC520_IRQ_DISABLED
;
/* disable PCI INT D */
sc520_mmcr
->
dmabcintmap
=
SC520_IRQ_DISABLED
;
/* disable DMA INT */
sc520_mmcr
->
ssimap
=
SC520_IRQ6
;
/* Set Synchronius serial INT to IRQ6*/
sc520_mmcr
->
wdtmap
=
SC520_IRQ_DISABLED
;
/* disable Watchdog INT */
sc520_mmcr
->
rtcmap
=
SC520_IRQ8
;
/* Set RTC int to 8 */
sc520_mmcr
->
wpvmap
=
SC520_IRQ_DISABLED
;
/* disable write protect INT */
sc520_mmcr
->
icemap
=
SC520_IRQ1
;
/* Set ICE Debug Serielport INT to IRQ1 */
sc520_mmcr
->
ferrmap
=
SC520_IRQ13
;
/* Set FP error INT to IRQ13 */
sc520_mmcr
->
uart_int_map
[
0
]
=
SC520_IRQ4
;
/* Set internal UART1 INT to IRQ4 */
sc520_mmcr
->
uart_int_map
[
1
]
=
SC520_IRQ3
;
/* Set internal UART2 INT to IRQ3 */
sc520_mmcr
->
gp_int_map
[
0
]
=
SC520_IRQ7
;
/* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
sc520_mmcr
->
gp_int_map
[
1
]
=
SC520_IRQ14
;
/* Set GPIRQ1 (CF IRQ) to IRQ14 */
sc520_mmcr
->
gp_int_map
[
3
]
=
SC520_IRQ5
;
/* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
sc520_mmcr
->
gp_int_map
[
4
]
=
SC520_IRQ_DISABLED
;
/* disbale GIRQ4 ( IRR IRQ ) */
sc520_mmcr
->
gp_int_map
[
5
]
=
SC520_IRQ_DISABLED
;
/* disable GPIRQ5 */
sc520_mmcr
->
gp_int_map
[
6
]
=
SC520_IRQ_DISABLED
;
/* disable GPIRQ6 */
sc520_mmcr
->
gp_int_map
[
7
]
=
SC520_IRQ_DISABLED
;
/* disable GPIRQ7 */
sc520_mmcr
->
gp_int_map
[
8
]
=
SC520_IRQ_DISABLED
;
/* disable GPIRQ8 */
sc520_mmcr
->
gp_int_map
[
9
]
=
SC520_IRQ_DISABLED
;
/* disable GPIRQ9 */
sc520_mmcr
->
gp_int_map
[
2
]
=
SC520_IRQ_DISABLED
;
/* disable GPIRQ2 */
sc520_mmcr
->
gp_int_map
[
10
]
=
SC520_IRQ_DISABLED
;
/* disable GPIRQ10 */
sc520_mmcr
->
pcihostmap
=
0x11f
;
/* Map PCI hostbridge INT to NMI */
sc520_mmcr
->
eccmap
=
0x100
;
/* Map SDRAM ECC failure INT to NMI */
}
...
...
@@ -101,7 +102,7 @@ static void irq_init(void)
/* PCI stuff */
static
void
pci_sc520_spunk_fixup_irq
(
struct
pci_controller
*
hose
,
pci_dev_t
dev
)
{
int
version
=
read_mmcr_byte
(
SC520_SYSINFO
)
;
int
version
=
sc520_mmcr
->
sysinfo
;
/* a configurable lists of irqs to steal
* when we need one (a board with more pci interrupt pins
...
...
@@ -255,41 +256,41 @@ static void bus_init(void)
* ?? Hyglo version 0.97 (small board)
* 10 Spunk board
*/
int
version
=
read_mmcr_byte
(
SC520_SYSINFO
)
;
int
version
=
sc520_mmcr
->
sysinfo
;
if
(
version
)
{
/* set up the GP IO pins (for the Spunk board) */
write_mmcr_word
(
SC520_PIOPFS31_16
,
0xfff0
)
;
/* set the GPIO pin function 31-16 reg */
write_mmcr_word
(
SC520_PIOPFS15_0
,
0x000f
)
;
/* set the GPIO pin function 15-0 reg */
write_mmcr_word
(
SC520_PIODIR31_16
,
0x000f
)
;
/* set the GPIO direction 31-16 reg */
write_mmcr_word
(
SC520_PIODIR15_0
,
0x1ff0
)
;
/* set the GPIO direction 15-0 reg */
write_mmcr_byte
(
SC520_CSPFS
,
0xc0
)
;
/* set the CS pin function reg */
write_mmcr_byte
(
SC520_CLKSEL
,
0x70
)
;
sc520_mmcr
->
piopfs31_16
=
0xfff0
;
/* set the GPIO pin function 31-16 reg */
sc520_mmcr
->
piopfs15_0
=
0x000f
;
/* set the GPIO pin function 15-0 reg */
sc520_mmcr
->
piodir31_16
=
0x000f
;
/* set the GPIO direction 31-16 reg */
sc520_mmcr
->
piodir15_0
=
0x1ff0
;
/* set the GPIO direction 15-0 reg */
sc520_mmcr
->
cspfs
=
0xc0
;
/* set the CS pin function reg */
sc520_mmcr
->
clksel
=
0x70
;
write_mmcr_word
(
SC520_PIOCLR31_16
,
0x0003
);
/* reset SSI chip-selects */
write_mmcr_word
(
SC520_PIOSET31_16
,
0x000c
)
;
sc520_mmcr
->
pioclr31_16
=
0x0003
;
/* reset SSI chip-selects */
sc520_mmcr
->
pioset31_16
=
0x000c
;
}
else
{
/* set up the GP IO pins (for the Hyglo board) */
write_mmcr_word
(
SC520_PIOPFS31_16
,
0xffc0
)
;
/* set the GPIO pin function 31-16 reg */
write_mmcr_word
(
SC520_PIOPFS15_0
,
0x1e7f
)
;
/* set the GPIO pin function 15-0 reg */
write_mmcr_word
(
SC520_PIODIR31_16
,
0x003f
)
;
/* set the GPIO direction 31-16 reg */
write_mmcr_word
(
SC520_PIODIR15_0
,
0xe180
)
;
/* set the GPIO direction 15-0 reg */
write_mmcr_byte
(
SC520_CSPFS
,
0x00
)
;
/* set the CS pin function reg */
write_mmcr_byte
(
SC520_CLKSEL
,
0x70
)
;
write_mmcr_word
(
SC520_PIOCLR15_0
,
0x0180
);
/* reset SSI chip-selects */
sc520_mmcr
->
piopfs31_16
=
0xffc0
;
/* set the GPIO pin function 31-16 reg */
sc520_mmcr
->
piopfs15_0
=
0x1e7f
;
/* set the GPIO pin function 15-0 reg */
sc520_mmcr
->
piodir31_16
=
0x003f
;
/* set the GPIO direction 31-16 reg */
sc520_mmcr
->
piodir15_0
=
0xe180
;
/* set the GPIO direction 15-0 reg */
sc520_mmcr
->
cspfs
=
0x00
;
/* set the CS pin function reg */
sc520_mmcr
->
clksel
=
0x70
;
sc520_mmcr
->
pioclr15_0
=
0x0180
;
/* reset SSI chip-selects */
}
write_mmcr_byte
(
SC520_GPCSRT
,
1
);
/* set the GP CS offset */
write_mmcr_byte
(
SC520_GPCSPW
,
3
);
/* set the GP CS pulse width */
write_mmcr_byte
(
SC520_GPCSOFF
,
1
);
/* set the GP CS offset */
write_mmcr_byte
(
SC520_GPRDW
,
3
);
/* set the RD pulse width */
write_mmcr_byte
(
SC520_GPRDOFF
,
1
);
/* set the GP RD offset */
write_mmcr_byte
(
SC520_GPWRW
,
3
);
/* set the GP WR pulse width */
write_mmcr_byte
(
SC520_GPWROFF
,
1
);
/* set the GP WR offset */
sc520_mmcr
->
gpcsrt
=
1
;
/* set the GP CS offset */
sc520_mmcr
->
gpcspw
=
3
;
/* set the GP CS pulse width */
sc520_mmcr
->
gpcsoff
=
1
;
/* set the GP CS offset */
sc520_mmcr
->
gprdw
=
3
;
/* set the RD pulse width */
sc520_mmcr
->
gprdoff
=
1
;
/* set the GP RD offset */
sc520_mmcr
->
gpwrw
=
3
;
/* set the GP WR pulse width */
sc520_mmcr
->
gpwroff
=
1
;
/* set the GP WR offset */
write_mmcr_word
(
SC520_BOOTCSCTL
,
0x0407
);
/* set up timing of BOOTCS */
sc520_mmcr
->
bootcsctl
=
0x0407
;
/* set up timing of BOOTCS */
/* adjust the memory map:
* by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
...
...
@@ -298,17 +299,17 @@ static void bus_init(void)
/* bootcs */
write_mmcr_long
(
SC520_PAR12
,
0x8bffe800
)
;
sc520_mmcr
->
par
[
12
]
=
0x8bffe800
;
/* IDE0 = GPCS6 1f0-1f7 */
write_mmcr_long
(
SC520_PAR3
,
0x380801f0
)
;
sc520_mmcr
->
par
[
3
]
=
0x380801f0
;
/* IDE1 = GPCS7 3f6 */
write_mmcr_long
(
SC520_PAR4
,
0x3c0003f6
)
;
sc520_mmcr
->
par
[
4
]
=
0x3c0003f6
;
asm
(
"wbinvd
\n
"
);
/* Flush cache, req. after setting the unchached attribute ona PAR */
write_mmcr_byte
(
SC520_ADDDECCTL
,
read_mmcr_byte
(
SC520_ADDDECCTL
)
&
~
(
UART2_DIS
|
UART1_DIS
)
);
sc520_mmcr
->
adddecctl
=
sc520_mmcr
->
adddecctl
&
~
(
UART2_DIS
|
UART1_DIS
);
}
...
...
@@ -361,7 +362,7 @@ u32 isa_map_rom(u32 bus_addr, int size)
printf
(
"setting PAR11 to %x
\n
"
,
par
);
/* Map rom 0x10000 with PAR1 */
write_mmcr_long
(
SC520_PAR11
,
par
)
;
sc520_mmcr
->
par
[
11
]
=
par
;
return
bus_addr
;
}
...
...
@@ -373,8 +374,8 @@ u32 isa_map_rom(u32 bus_addr, int size)
void
isa_unmap_rom
(
u32
addr
)
{
printf
(
"isa_unmap_rom asked to unmap %x"
,
addr
);
if
((
addr
>>
12
)
==
(
read_mmcr_long
(
SC520_PAR11
)
&
0x3ffff
))
{
write_mmcr_long
(
SC520_PAR11
,
0
)
;
if
((
addr
>>
12
)
==
(
sc520_mmcr
->
par
[
11
]
&
0x3ffff
))
{
sc520_mmcr
->
par
[
11
]
=
0
;
printf
(
" done
\n
"
);
return
;
}
...
...
@@ -410,7 +411,7 @@ u32 pci_get_rom_window(struct pci_controller *hose, int size)
printf
(
"setting PAR1 to %x
\n
"
,
par
);
/* Map rom 0x10000 with PAR1 */
write_mmcr_long
(
SC520_PAR1
,
par
)
;
sc520_mmcr
->
par
[
1
]
=
par
;
return
PCI_ROM_TEMP_SPACE
;
}
...
...
@@ -423,7 +424,7 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
{
printf
(
"pci_remove_rom_window: %x"
,
addr
);
if
(
addr
==
PCI_ROM_TEMP_SPACE
)
{
write_mmcr_long
(
SC520_PAR1
,
0
)
;
sc520_mmcr
->
par
[
1
]
=
0
;
printf
(
" done
\n
"
);
return
;
}
...
...
@@ -441,11 +442,10 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
int
pci_enable_legacy_video_ports
(
struct
pci_controller
*
hose
)
{
/* Map video memory to 0xa0000*/
write_mmcr_long
(
SC520_PAR0
,
0x7200400a
)
;
sc520_mmcr
->
par
[
0
]
=
0x7200400a
;
/* forward all I/O accesses to PCI */
write_mmcr_byte
(
SC520_ADDDECCTL
,
read_mmcr_byte
(
SC520_ADDDECCTL
)
|
IO_HOLE_DEST_PCI
);
sc520_mmcr
->
adddecctl
=
sc520_mmcr
->
adddecctl
|
IO_HOLE_DEST_PCI
;
/* so we map away all io ports to pci (only way to access pci io
...
...
@@ -455,22 +455,22 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose)
*/
/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
write_mmcr_long
(
SC520_PAR5
,
0x31f70100
)
;
sc520_mmcr
->
par
[
5
]
=
0x31f70100
;
/* com2 use 2f8-2ff */
/* bring 0x300 - 0x3af back to ISA using PAR7 */
write_mmcr_long
(
SC520_PAR7
,
0x30af0300
)
;
sc520_mmcr
->
par
[
7
]
=
0x30af0300
;
/* vga use 3b0-3bb */
/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
write_mmcr_long
(
SC520_PAR8
,
0x300303bc
)
;
sc520_mmcr
->
par
[
8
]
=
0x300303bc
;
/* vga use 3c0-3df */
/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
write_mmcr_long
(
SC520_PAR9
,
0x301703e0
)
;
sc520_mmcr
->
par
[
9
]
=
0x301703e0
;
/* com1 use 3f8-3ff */
...
...
@@ -489,12 +489,12 @@ int board_init(void)
irq_init
();
/* max drive current on SDRAM */
write_mmcr_word
(
SC520_DSCTL
,
0x0100
)
;
sc520_mmcr
->
dsctl
=
0x0100
;
/* enter debug mode after next reset (only if jumper is also set) */
write_mmcr_byte
(
SC520_RESCFG
,
0x08
)
;
sc520_mmcr
->
rescfg
=
0x08
;
/* configure the software timer to 33.000MHz */
write_mmcr_byte
(
SC520_SWTMRCFG
,
1
)
;
sc520_mmcr
->
swtmrcfg
=
1
;
gd
->
bus_clk
=
33000000
;
return
0
;
...
...
@@ -508,17 +508,15 @@ int dram_init(void)
void
show_boot_progress
(
int
val
)
{
int
version
=
read_mmcr_byte
(
SC520_SYSINFO
)
;
int
version
=
sc520_mmcr
->
sysinfo
;
if
(
val
<
-
32
)
val
=
-
1
;
/* let things compatible */
if
(
version
==
0
)
{
/* PIO31-PIO16 Data */
write_mmcr_word
(
SC520_PIODATA31_16
,
(
read_mmcr_word
(
SC520_PIODATA31_16
)
&
0xffc0
)
|
((
val
&
0x7e
)
>>
1
));
/* 0x1f8 >> 3 */
sc520_mmcr
->
piodata31_16
=
(
sc520_mmcr
->
piodata31_16
&
0xffc0
)
|
((
val
&
0x7e
)
>>
1
);
/* 0x1f8 >> 3 */
/* PIO0-PIO15 Data */
write_mmcr_word
(
SC520_PIODATA15_0
,
(
read_mmcr_word
(
SC520_PIODATA15_0
)
&
0x1fff
)
|
((
val
&
0x7
)
<<
13
));
sc520_mmcr
->
piodata15_0
=
(
sc520_mmcr
->
piodata15_0
&
0x1fff
)
|
((
val
&
0x7
)
<<
13
);
}
else
{
/* newer boards use PIO4-PIO12 */
/* PIO0-PIO15 Data */
...
...
@@ -527,8 +525,7 @@ void show_boot_progress(int val)
#else
val
=
(
val
&
0x007
)
|
((
val
&
0x07e
)
<<
2
);
#endif
write_mmcr_word
(
SC520_PIODATA15_0
,
(
read_mmcr_word
(
SC520_PIODATA15_0
)
&
0xe00f
)
|
((
val
&
0x01ff
)
<<
4
));
sc520_mmcr
->
piodata15_0
=
(
sc520_mmcr
->
piodata15_0
&
0xe00f
)
|
((
val
&
0x01ff
)
<<
4
);
}
}
...
...
@@ -536,7 +533,7 @@ void show_boot_progress(int val)
int
last_stage_init
(
void
)
{
int
version
=
read_mmcr_byte
(
SC520_SYSINFO
)
;
int
version
=
sc520_mmcr
->
sysinfo
;
printf
(
"Omicron Ceti SC520 Spunk revision %x
\n
"
,
version
);
...
...
@@ -587,30 +584,30 @@ int last_stage_init(void)
void
ssi_chip_select
(
int
dev
)
{
int
version
=
read_mmcr_byte
(
SC520_SYSINFO
)
;
int
version
=
sc520_mmcr
->
sysinfo
;
if
(
version
)
{
/* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
switch
(
dev
)
{
case
1
:
/* EEPROM */
write_mmcr_word
(
SC520_PIOCLR31_16
,
0x0004
)
;
sc520_mmcr
->
pioclr31_16
=
0x0004
;
break
;
case
2
:
/* Temp Probe */
write_mmcr_word
(
SC520_PIOSET31_16
,
0x0002
)
;
sc520_mmcr
->
pioset31_16
=
0x0002
;
break
;
case
3
:
/* CAN */
write_mmcr_word
(
SC520_PIOCLR31_16
,
0x0008
)
;
sc520_mmcr
->
pioclr31_16
=
0x0008
;
break
;
case
4
:
/* AUX */
write_mmcr_word
(
SC520_PIOSET31_16
,
0x0001
)
;
sc520_mmcr
->
pioset31_16
=
0x0001
;
break
;
case
0
:
write_mmcr_word
(
SC520_PIOCLR31_16
,
0x0003
)
;
write_mmcr_word
(
SC520_PIOSET31_16
,
0x000c
)
;
sc520_mmcr
->
pioclr31_16
=
0x0003
;
sc520_mmcr
->
pioset31_16
=
0x000c
;
break
;
default:
...
...
@@ -622,15 +619,15 @@ void ssi_chip_select(int dev)
switch
(
dev
)
{
case
1
:
/* EEPROM */
write_mmcr_word
(
SC520_PIOSET15_0
,
0x0100
)
;
sc520_mmcr
->
pioset15_0
=
0x0100
;
break
;
case
2
:
/* Temp Probe */
write_mmcr_word
(
SC520_PIOSET15_0
,
0x0080
)
;
sc520_mmcr
->
pioset15_0
=
0x0080
;
break
;
case
0
:
write_mmcr_word
(
SC520_PIOCLR15_0
,
0x0180
)
;
sc520_mmcr
->
pioclr15_0
=
0x0180
;
break
;
default:
...
...
@@ -669,9 +666,7 @@ int mw_eeprom_write(int x, int offset, uchar *buffer, int len)
void
spi_init_f
(
void
)
{
read_mmcr_byte
(
SC520_SYSINFO
)
?
spi_eeprom_probe
(
1
)
:
mw_eeprom_probe
(
1
);
sc520_mmcr
->
sysinfo
?
spi_eeprom_probe
(
1
)
:
mw_eeprom_probe
(
1
);
}
...
...
@@ -686,7 +681,7 @@ ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
offset
|=
addr
[
i
];
}
return
read_mmcr_byte
(
SC520_SYSINFO
)
?
return
sc520_mmcr
->
sysinfo
?
spi_eeprom_read
(
1
,
offset
,
buffer
,
len
)
:
mw_eeprom_read
(
1
,
offset
,
buffer
,
len
);
}
...
...
@@ -702,7 +697,7 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
offset
|=
addr
[
i
];
}
return
read_mmcr_byte
(
SC520_SYSINFO
)
?
return
sc520_mmcr
->
sysinfo
?
spi_eeprom_write
(
1
,
offset
,
buffer
,
len
)
:
mw_eeprom_write
(
1
,
offset
,
buffer
,
len
);
}
...
...
cpu/i386/sc520/sc520.c
浏览文件 @
5aaeb2a3
...
...
@@ -33,75 +33,35 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* utility functions for boards based on the AMD sc520
*
* void write_mmcr_byte(u16 mmcr, u8 data)
* void write_mmcr_word(u16 mmcr, u16 data)
* void write_mmcr_long(u16 mmcr, u32 data)
*
* u8 read_mmcr_byte(u16 mmcr)
* u16 read_mmcr_word(u16 mmcr)
* u32 read_mmcr_long(u16 mmcr)
*
* void init_sc520(void)
* unsigned long init_sc520_dram(void)
*/
static
u32
mmcr_base
=
0xfffef000
;
void
write_mmcr_byte
(
u16
mmcr
,
u8
data
)
{
writeb
(
data
,
mmcr
+
mmcr_base
);
}
void
write_mmcr_word
(
u16
mmcr
,
u16
data
)
{
writew
(
data
,
mmcr
+
mmcr_base
);
}
void
write_mmcr_long
(
u16
mmcr
,
u32
data
)
{
writel
(
data
,
mmcr
+
mmcr_base
);
}
u8
read_mmcr_byte
(
u16
mmcr
)
{
return
readb
(
mmcr
+
mmcr_base
);
}
u16
read_mmcr_word
(
u16
mmcr
)
{
return
readw
(
mmcr
+
mmcr_base
);
}
u32
read_mmcr_long
(
u16
mmcr
)
{
return
readl
(
mmcr
+
mmcr_base
);
}
volatile
sc520_mmcr_t
*
sc520_mmcr
=
(
sc520_mmcr_t
*
)
0xfffef000
;
void
init_sc520
(
void
)
{
/* Set the UARTxCTL register at it's slower,
* baud clock giving us a 1.8432 MHz reference
*/
write_mmcr_byte
(
SC520_UART1CTL
,
7
)
;
write_mmcr_byte
(
SC520_UART2CTL
,
7
)
;
sc520_mmcr
->
uart1ctl
=
0x07
;
sc520_mmcr
->
uart2ctl
=
0x07
;
/* first set the timer pin mapping */
write_mmcr_byte
(
SC520_CLKSEL
,
0x72
)
;
/* no clock frequency selected, use 1.1892MHz */
sc520_mmcr
->
clksel
=
0x72
;
/* no clock frequency selected, use 1.1892MHz */
/* enable PCI bus arbitrer */
write_mmcr_byte
(
SC520_SYSARBCTL
,
0x02
);
/* enable concurrent mode */
write_mmcr_word
(
SC520_SYSARBMENB
,
0x1f
);
/* enable external grants */
write_mmcr_word
(
SC520_HBCTL
,
0x04
);
/* enable posted-writes */
sc520_mmcr
->
sysarbctl
=
0x02
;
/* enable concurrent mode */
sc520_mmcr
->
sysarbmenb
=
0x1f
;
/* enable external grants */
sc520_mmcr
->
hbctl
=
0x04
;
/* enable posted-writes */
if
(
CONFIG_SYS_SC520_HIGH_SPEED
)
{
write_mmcr_byte
(
SC520_CPUCTL
,
0x2
)
;
/* set it to 133 MHz and write back */
sc520_mmcr
->
cpuctl
=
0x02
;
/* set it to 133 MHz and write back */
gd
->
cpu_clk
=
133000000
;
printf
(
"## CPU Speed set to 133MHz
\n
"
);
}
else
{
write_mmcr_byte
(
SC520_CPUCTL
,
1
);
/* set CPU to 100 MHz and write back cache
*/
sc520_mmcr
->
cpuctl
=
0x01
;
/* set it to 100 MHz and write back
*/
printf
(
"## CPU Speed set to 100MHz
\n
"
);
gd
->
cpu_clk
=
100000000
;
}
...
...
@@ -114,7 +74,7 @@ void init_sc520(void)
"loop 0b
\n
"
:
:
:
"ecx"
);
/* turn on the SDRAM write buffer */
write_mmcr_byte
(
SC520_DBCTL
,
0x11
)
;
sc520_mmcr
->
dbctl
=
0x11
;
/* turn on the cache and disable write through */
asm
(
"movl %%cr0, %%eax
\n
"
...
...
@@ -156,10 +116,9 @@ unsigned long init_sc520_dram(void)
val
=
3
;
/* 62.4us */
}
write_mmcr_byte
(
SC520_DRCCTL
,
(
read_mmcr_byte
(
SC520_DRCCTL
)
&
0xcf
)
|
(
val
<<
4
)
);
sc520_mmcr
->
drcctl
=
(
sc520_mmcr
->
drcctl
&
0xcf
)
|
(
val
<<
4
);
val
=
read_mmcr_byte
(
SC520_DRCTMCTL
);
val
&=
0xf0
;
val
=
sc520_mmcr
->
drctmctl
&
0xf0
;
if
(
cas_precharge_delay
==
3
)
{
val
|=
0x04
;
/* 3T */
...
...
@@ -174,12 +133,12 @@ unsigned long init_sc520_dram(void)
}
else
{
val
|=
1
;
}
write_mmcr_byte
(
SC520_DRCTMCTL
,
val
)
;
sc520_mmcr
->
drctmctl
=
val
;
#endif
/* We read-back the configuration of the dram
* controller that the assembly code wrote */
dram_ctrl
=
read_mmcr_long
(
SC520_DRCBENDADR
)
;
dram_ctrl
=
sc520_mmcr
->
drcbendadr
;
bd
->
bi_dram
[
0
].
start
=
0
;
if
(
dram_ctrl
&
0x80
)
{
...
...
@@ -232,7 +191,7 @@ void reset_cpu(ulong addr)
{
printf
(
"Resetting using SC520 MMCR
\n
"
);
/* Write a '1' to the SYS_RST of the RESCFG MMCR */
write_mmcr_word
(
SC520_RESCFG
,
0x0001
)
;
sc520_mmcr
->
rescfg
=
0x01
;
/* NOTREACHED */
}
...
...
cpu/i386/sc520/sc520_pci.c
浏览文件 @
5aaeb2a3
...
...
@@ -33,23 +33,23 @@ static struct {
u16
level_reg
;
u8
level_bit
;
}
sc520_irq
[]
=
{
{
SC520_IRQ0
,
SC520_MPICMODE
,
0x01
},
{
SC520_IRQ1
,
SC520_MPICMODE
,
0x02
},
{
SC520_IRQ2
,
SC520_SL1PICMODE
,
0x02
},
{
SC520_IRQ3
,
SC520_MPICMODE
,
0x08
},
{
SC520_IRQ4
,
SC520_MPICMODE
,
0x10
},
{
SC520_IRQ5
,
SC520_MPICMODE
,
0x20
},
{
SC520_IRQ6
,
SC520_MPICMODE
,
0x40
},
{
SC520_IRQ7
,
SC520_MPICMODE
,
0x80
},
{
SC520_IRQ8
,
SC520_SL1PICMODE
,
0x01
},
{
SC520_IRQ9
,
SC520_SL1PICMODE
,
0x02
},
{
SC520_IRQ10
,
SC520_SL1PICMODE
,
0x04
},
{
SC520_IRQ11
,
SC520_SL1PICMODE
,
0x08
},
{
SC520_IRQ12
,
SC520_SL1PICMODE
,
0x10
},
{
SC520_IRQ13
,
SC520_SL1PICMODE
,
0x20
},
{
SC520_IRQ14
,
SC520_SL1PICMODE
,
0x40
},
{
SC520_IRQ15
,
SC520_SL1PICMODE
,
0x80
}
{
SC520_IRQ0
,
0
,
0x01
},
{
SC520_IRQ1
,
0
,
0x02
},
{
SC520_IRQ2
,
1
,
0x02
},
{
SC520_IRQ3
,
0
,
0x08
},
{
SC520_IRQ4
,
0
,
0x10
},
{
SC520_IRQ5
,
0
,
0x20
},
{
SC520_IRQ6
,
0
,
0x40
},
{
SC520_IRQ7
,
0
,
0x80
},
{
SC520_IRQ8
,
1
,
0x01
},
{
SC520_IRQ9
,
1
,
0x02
},
{
SC520_IRQ10
,
1
,
0x04
},
{
SC520_IRQ11
,
1
,
0x08
},
{
SC520_IRQ12
,
1
,
0x10
},
{
SC520_IRQ13
,
1
,
0x20
},
{
SC520_IRQ14
,
1
,
0x40
},
{
SC520_IRQ15
,
1
,
0x80
}
};
...
...
@@ -77,34 +77,34 @@ int pci_sc520_set_irq(int pci_pin, int irq)
/* first disable any non-pci interrupt source that use
* this level */
for
(
i
=
SC520_GPTMR0MAP
;
i
<=
SC520_GP10IMAP
;
i
++
)
{
if
(
i
>=
SC520_PCIINTAMAP
&&
i
<=
SC520_PCIINTDMAP
)
{
continue
;
}
if
(
read_mmcr_byte
(
i
)
==
sc520_irq
[
irq
].
priority
)
{
write_mmcr_byte
(
i
,
SC520_IRQ_DISABLED
);
}
/* PCI interrupt mapping (A through D)*/
for
(
i
=
0
;
i
<=
3
;
i
++
)
{
if
(
sc520_mmcr
->
pci_int_map
[
i
]
==
sc520_irq
[
irq
].
priority
)
sc520_mmcr
->
pci_int_map
[
i
]
=
SC520_IRQ_DISABLED
;
}
/* GP IRQ interrupt mapping */
for
(
i
=
0
;
i
<=
10
;
i
++
)
{
if
(
sc520_mmcr
->
gp_int_map
[
i
]
==
sc520_irq
[
irq
].
priority
)
sc520_mmcr
->
gp_int_map
[
i
]
=
SC520_IRQ_DISABLED
;
}
/* Set the trigger to level */
write_mmcr_byte
(
sc520_irq
[
irq
].
level_reg
,
read_mmcr_byte
(
sc520_irq
[
irq
].
level_reg
)
|
sc520_irq
[
irq
].
level_bit
)
;
sc520_mmcr
->
pic_mode
[
sc520_irq
[
irq
].
level_reg
]
=
sc520_mmcr
->
pic_mode
[
sc520_irq
[
irq
].
level_reg
]
|
sc520_irq
[
irq
].
level_bit
;
if
(
pci_pin
<
4
)
{
/* PCI INTA-INTD */
/* route the interrupt */
write_mmcr_byte
(
SC520_PCIINTAMAP
+
pci_pin
,
sc520_irq
[
irq
].
priority
);
sc520_mmcr
->
pci_int_map
[
pci_pin
]
=
sc520_irq
[
irq
].
priority
;
}
else
{
/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
write_mmcr_byte
(
SC520_GP0IMAP
+
pci_pin
-
4
,
sc520_irq
[
irq
].
priority
)
;
sc520_mmcr
->
gp_int_map
[
pci_pin
-
4
]
=
sc520_irq
[
irq
].
priority
;
/* also set the polarity in this case */
write_mmcr_word
(
SC520_INTPINPOL
,
read_mmcr_word
(
SC520_INTPINPOL
)
|
(
1
<<
(
pci_pin
-
4
)));
sc520_mmcr
->
intpinpol
=
sc520_mmcr
->
intpinpol
|
(
1
<<
(
pci_pin
-
4
));
}
/* register the pin */
...
...
cpu/i386/sc520/sc520_ssi.c
浏览文件 @
5aaeb2a3
...
...
@@ -61,32 +61,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
temp
|=
PHS_INV_ENB
;
}
write_mmcr_byte
(
SC520_SSICTL
,
temp
)
;
sc520_mmcr
->
ssictl
=
temp
;
return
0
;
}
u8
ssi_txrx_byte
(
u8
data
)
{
write_mmcr_byte
(
SC520_SSIXMIT
,
data
);
while
((
read_mmcr_byte
(
SC520_SSISTA
))
&
SSISTA_BSY
);
write_mmcr_byte
(
SC520_SSICMD
,
SSICMD_CMD_SEL_XMITRCV
);
while
((
read_mmcr_byte
(
SC520_SSISTA
))
&
SSISTA_BSY
);
return
read_mmcr_byte
(
SC520_SSIRCV
);
sc520_mmcr
->
ssixmit
=
data
;
while
(
sc520_mmcr
->
ssista
&
SSISTA_BSY
);
sc520_mmcr
->
ssicmd
=
SSICMD_CMD_SEL_XMITRCV
;
while
(
sc520_mmcr
->
ssista
&
SSISTA_BSY
);
return
sc520_mmcr
->
ssircv
;
}
void
ssi_tx_byte
(
u8
data
)
{
write_mmcr_byte
(
SC520_SSIXMIT
,
data
)
;
while
(
(
read_mmcr_byte
(
SC520_SSISTA
))
&
SSISTA_BSY
);
write_mmcr_byte
(
SC520_SSICMD
,
SSICMD_CMD_SEL_XMIT
)
;
sc520_mmcr
->
ssixmit
=
data
;
while
(
sc520_mmcr
->
ssista
&
SSISTA_BSY
);
sc520_mmcr
->
ssicmd
=
SSICMD_CMD_SEL_XMIT
;
}
u8
ssi_rx_byte
(
void
)
{
while
((
read_mmcr_byte
(
SC520_SSISTA
))
&
SSISTA_BSY
);
write_mmcr_byte
(
SC520_SSICMD
,
SSICMD_CMD_SEL_RCV
);
while
((
read_mmcr_byte
(
SC520_SSISTA
))
&
SSISTA_BSY
);
return
read_mmcr_byte
(
SC520_SSIRCV
);
while
(
sc520_mmcr
->
ssista
&
SSISTA_BSY
);
sc520_mmcr
->
ssicmd
=
SSICMD_CMD_SEL_RCV
;
while
(
sc520_mmcr
->
ssista
&
SSISTA_BSY
);
return
sc520_mmcr
->
ssircv
;
}
cpu/i386/sc520/sc520_timer.c
浏览文件 @
5aaeb2a3
...
...
@@ -30,29 +30,29 @@
void
sc520_timer_isr
(
void
)
{
/* Ack the GP Timer Interrupt */
write_mmcr_byte
(
SC520_GPTMRSTA
,
0x02
)
;
sc520_mmcr
->
gptmrsta
=
0x02
;
}
int
timer_init
(
void
)
{
/* Map GP Timer 1 to Master PIC IR0 */
write_mmcr_byte
(
SC520_GPTMR1MAP
,
0x01
)
;
sc520_mmcr
->
gp_tmr_int_map
[
1
]
=
0x01
;
/* Disable GP Timers 1 & 2 - Allow configuration writes */
write_mmcr_word
(
SC520_GPTMR1CTL
,
0x4000
)
;
write_mmcr_word
(
SC520_GPTMR2CTL
,
0x4000
)
;
sc520_mmcr
->
gptmr1ctl
=
0x4000
;
sc520_mmcr
->
gptmr2ctl
=
0x4000
;
/* Reset GP Timers 1 & 2 */
write_mmcr_word
(
SC520_GPTMR1CNT
,
0x0000
)
;
write_mmcr_word
(
SC520_GPTMR2CNT
,
0x0000
)
;
sc520_mmcr
->
gptmr1cnt
=
0x0000
;
sc520_mmcr
->
gptmr2cnt
=
0x0000
;
/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
write_mmcr_word
(
SC520_GPTMR2MAXCMPA
,
83
)
;
write_mmcr_word
(
SC520_GPTMR2CTL
,
0xc001
)
;
sc520_mmcr
->
gptmr2maxcmpa
=
83
;
sc520_mmcr
->
gptmr2ctl
=
0xc001
;
/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
write_mmcr_word
(
SC520_GPTMR1MAXCMPA
,
100
)
;
write_mmcr_word
(
SC520_GPTMR1CTL
,
0xe009
)
;
sc520_mmcr
->
gptmr1maxcmpa
=
100
;
sc520_mmcr
->
gptmr1ctl
=
0xe009
;
/* Register the SC520 specific timer interrupt handler */
register_timer_isr
(
sc520_timer_isr
);
...
...
@@ -62,7 +62,7 @@ int timer_init(void)
unmask_irq
(
0
);
/* Clear the GP Timer 1 status register to get the show rolling*/
write_mmcr_byte
(
SC520_GPTMRSTA
,
0x02
)
;
sc520_mmcr
->
gptmrsta
=
0x02
;
return
0
;
}
...
...
@@ -71,12 +71,13 @@ void udelay(unsigned long usec)
{
int
m
=
0
;
long
u
;
long
temp
;
read_mmcr_word
(
SC520_SWTMRMILLI
)
;
read_mmcr_word
(
SC520_SWTMRMICRO
)
;
temp
=
sc520_mmcr
->
swtmrmilli
;
temp
=
sc520_mmcr
->
swtmrmicro
;
do
{
m
+=
read_mmcr_word
(
SC520_SWTMRMILLI
)
;
u
=
read_mmcr_word
(
SC520_SWTMRMICRO
)
+
(
m
*
1000
);
m
+=
sc520_mmcr
->
swtmrmilli
;
u
=
sc520_mmcr
->
swtmrmicro
+
(
m
*
1000
);
}
while
(
u
<
usec
);
}
include/asm-i386/ic/sc520.h
浏览文件 @
5aaeb2a3
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