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体验新版 GitCode,发现更多精彩内容 >>
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5a451f11
编写于
4月 09, 2019
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge tag 'u-boot-atmel-2019.07-a' of
git://git.denx.de/u-boot-atmel
First set of u-boot-atmel features and fixes for 2019.07 cycle
上级
1d63ec3f
7bf9bca7
变更
39
隐藏空白更改
内联
并排
Showing
39 changed file
with
899 addition
and
137 deletion
+899
-137
Kconfig
Kconfig
+11
-0
Makefile
Makefile
+3
-1
README
README
+0
-3
arch/arm/dts/Makefile
arch/arm/dts/Makefile
+5
-0
arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi
arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi
+5
-0
arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts
arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts
+120
-0
arch/arm/dts/at91sam9x5.dtsi
arch/arm/dts/at91sam9x5.dtsi
+1
-1
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Kconfig
+8
-0
arch/arm/mach-at91/arm926ejs/Makefile
arch/arm/mach-at91/arm926ejs/Makefile
+2
-0
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+2
-0
arch/arm/mach-at91/armv7/sama5d2_devices.c
arch/arm/mach-at91/armv7/sama5d2_devices.c
+1
-1
arch/arm/mach-at91/clock.c
arch/arm/mach-at91/clock.c
+48
-0
arch/arm/mach-at91/include/mach/at91_wdt.h
arch/arm/mach-at91/include/mach/at91_wdt.h
+10
-0
arch/arm/mach-at91/include/mach/sama5d2.h
arch/arm/mach-at91/include/mach/sama5d2.h
+4
-1
arch/arm/mach-at91/spl_at91.c
arch/arm/mach-at91/spl_at91.c
+10
-0
board/gardena/smart-gateway-at91sam/Kconfig
board/gardena/smart-gateway-at91sam/Kconfig
+12
-0
board/gardena/smart-gateway-at91sam/MAINTAINERS
board/gardena/smart-gateway-at91sam/MAINTAINERS
+7
-0
board/gardena/smart-gateway-at91sam/Makefile
board/gardena/smart-gateway-at91sam/Makefile
+7
-0
board/gardena/smart-gateway-at91sam/board.c
board/gardena/smart-gateway-at91sam/board.c
+59
-0
board/gardena/smart-gateway-at91sam/spl.c
board/gardena/smart-gateway-at91sam/spl.c
+135
-0
board/ronetix/pm9g45/pm9g45.c
board/ronetix/pm9g45/pm9g45.c
+5
-5
configs/gardena-smart-gateway-at91sam_defconfig
configs/gardena-smart-gateway-at91sam_defconfig
+83
-0
configs/pm9g45_defconfig
configs/pm9g45_defconfig
+37
-7
configs/smartweb_defconfig
configs/smartweb_defconfig
+0
-1
configs/taurus_defconfig
configs/taurus_defconfig
+0
-1
drivers/net/macb.c
drivers/net/macb.c
+7
-1
drivers/pinctrl/pinctrl-at91.c
drivers/pinctrl/pinctrl-at91.c
+79
-5
drivers/serial/Kconfig
drivers/serial/Kconfig
+9
-0
drivers/serial/atmel_usart.c
drivers/serial/atmel_usart.c
+12
-0
drivers/watchdog/Kconfig
drivers/watchdog/Kconfig
+0
-4
drivers/watchdog/at91sam9_wdt.c
drivers/watchdog/at91sam9_wdt.c
+13
-19
include/configs/corvus.h
include/configs/corvus.h
+3
-0
include/configs/gardena-smart-gateway-at91sam.h
include/configs/gardena-smart-gateway-at91sam.h
+88
-0
include/configs/pm9g45.h
include/configs/pm9g45.h
+91
-82
include/configs/smartweb.h
include/configs/smartweb.h
+4
-0
include/configs/taurus.h
include/configs/taurus.h
+3
-0
include/dt-bindings/pinctrl/at91.h
include/dt-bindings/pinctrl/at91.h
+4
-0
include/watchdog.h
include/watchdog.h
+8
-2
scripts/Makefile.spl
scripts/Makefile.spl
+3
-3
未找到文件。
Kconfig
浏览文件 @
5a451f11
...
...
@@ -224,6 +224,16 @@ config BUILD_ROM
which are not shipped in the U-Boot source tree.
Please, see doc/README.x86 for details.
config SPL_IMAGE
string "SPL image used in the combined SPL+U-Boot image"
default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "spl/u-boot-spl.bin"
help
Select the SPL build target that shall be generated by the SPL
build process (default spl/u-boot-spl.bin). This image will be
used to generate a combined image with SPL and main U-Boot
proper as one single image.
config BUILD_TARGET
string "Build target special images"
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
...
...
@@ -232,6 +242,7 @@ config BUILD_TARGET
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
default "u-boot.kwb" if KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
help
Some SoCs need special image types (e.g. U-Boot binary
with a special header) as build targets. By defining
...
...
Makefile
浏览文件 @
5a451f11
...
...
@@ -1232,9 +1232,11 @@ else
SPL_PAYLOAD
:=
u-boot.bin
endif
SPL_IMAGE
:=
$
(
CONFIG_SPL_IMAGE:
"%"
=
%
)
OBJCOPYFLAGS_u-boot-with-spl.bin
=
-I
binary
-O
binary
\
--pad-to
=
$(CONFIG_SPL_PAD_TO)
u-boot-with-spl.bin
:
spl/u-boot-spl.bin
$(SPL_PAYLOAD) FORCE
u-boot-with-spl.bin
:
$(SPL_IMAGE)
$(SPL_PAYLOAD) FORCE
$(
call
if_changed,pad_cat
)
ifeq
($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
...
...
README
浏览文件 @
5a451f11
...
...
@@ -767,9 +767,6 @@ The following options need to be configured:
SoC, then define this variable and provide board
specific code for the "hw_watchdog_reset" function.
CONFIG_AT91_HW_WDT_TIMEOUT
specify the timeout in seconds. default 2 seconds.
- Real-Time Clock:
When CONFIG_CMD_DATE is selected, the type of the RTC
...
...
arch/arm/dts/Makefile
浏览文件 @
5a451f11
...
...
@@ -598,6 +598,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK)
+=
at91sam9m10g45ek.dtb
dtb-$(CONFIG_TARGET_PM9G45)
+=
at91sam9m10g45ek.dtb
dtb-$(CONFIG_TARGET_AT91SAM9X5EK)
+=
\
at91sam9g15ek.dtb
\
at91sam9g25ek.dtb
\
...
...
@@ -607,6 +609,9 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
dtb-$(CONFIG_TARGET_AT91SAM9N12EK)
+=
at91sam9n12ek.dtb
dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM)
+=
\
at91sam9g25-gardena-smart-gateway.dtb
dtb-$(CONFIG_TARGET_ETHERNUT5)
+=
ethernut5.dtb
dtb-$(CONFIG_TARGET_USB_A9263)
+=
usb_a9263.dtb
...
...
arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi
0 → 100644
浏览文件 @
5a451f11
// SPDX-License-Identifier: GPL-2.0+
&dbgu {
u-boot,dm-pre-reloc;
};
arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts
0 → 100644
浏览文件 @
5a451f11
//
SPDX
-
License
-
Identifier
:
GPL
-
2.0
+
/*
*
Device
Tree
file
for
the
GARDENA
smart
Gateway
(
AT91SAM
)
*
*
Copyright
(
C
)
2012
Atmel
,
*
2012
Nicolas
Ferre
<
nicolas
.
ferre
@
atmel
.
com
>
*/
/
dts
-
v1
/;
#
include
"at91sam9g25.dtsi"
/
{
model
=
"GARDENA smart Gateway (AT91SAM)"
;
compatible
=
"gardena,smart-gateway-at91sam"
,
"atmel,at91sam9"
;
aliases
{
serial0
=
&
dbgu
;
};
chosen
{
stdout
-
path
=
"serial0:115200n8"
;
};
memory
{
reg
=
<
0x20000000
0x8000000
>;
};
clocks
{
slow_xtal
{
clock
-
frequency
=
<
32768
>;
};
main_xtal
{
clock
-
frequency
=
<
12000000
>;
};
};
leds
{
compatible
=
"gpio-leds"
;
power_blue
{
label
=
"smartgw:power:blue"
;
gpios
=
<&
pioC
21
GPIO_ACTIVE_HIGH
>;
default
-
state
=
"off"
;
};
power_green
{
label
=
"smartgw:power:green"
;
gpios
=
<&
pioC
20
GPIO_ACTIVE_HIGH
>;
default
-
state
=
"on"
;
};
power_red
{
label
=
"smartgw:power:red"
;
gpios
=
<&
pioC
19
GPIO_ACTIVE_HIGH
>;
default
-
state
=
"off"
;
};
radio_blue
{
label
=
"smartgw:radio:blue"
;
gpios
=
<&
pioC
18
GPIO_ACTIVE_HIGH
>;
default
-
state
=
"off"
;
};
radio_green
{
label
=
"smartgw:radio:green"
;
gpios
=
<&
pioC
17
GPIO_ACTIVE_HIGH
>;
default
-
state
=
"off"
;
};
radio_red
{
label
=
"smartgw:radio:red"
;
gpios
=
<&
pioC
16
GPIO_ACTIVE_HIGH
>;
default
-
state
=
"off"
;
};
internet_blue
{
label
=
"smartgw:internet:blue"
;
gpios
=
<&
pioC
15
GPIO_ACTIVE_HIGH
>;
default
-
state
=
"off"
;
};
internet_green
{
label
=
"smartgw:internet:green"
;
gpios
=
<&
pioC
14
GPIO_ACTIVE_HIGH
>;
default
-
state
=
"off"
;
};
internet_red
{
label
=
"smartgw:internet:red"
;
gpios
=
<&
pioC
13
GPIO_ACTIVE_HIGH
>;
default
-
state
=
"off"
;
};
};
};
&
dbgu
{
status
=
"okay"
;
};
&
macb0
{
phy
-
mode
=
"rmii"
;
status
=
"okay"
;
};
&
nand0
{
nand
-
bus
-
width
=
<
8
>;
nand
-
ecc
-
mode
=
"hw"
;
atmel
,
has
-
pmecc
;
/*
Enable
PMECC
*/
atmel
,
pmecc
-
cap
=
<
2
>;
atmel
,
pmecc
-
sector
-
size
=
<
512
>;
nand
-
on
-
flash
-
bbt
;
status
=
"okay"
;
};
&
watchdog
{
status
=
"okay"
;
timeout
-
sec
=
<
16
>;
};
arch/arm/dts/at91sam9x5.dtsi
浏览文件 @
5a451f11
...
...
@@ -1180,7 +1180,7 @@
};
};
watchdog
@
fffffe40
{
watchdog
:
watchdog
@
fffffe40
{
compatible
=
"atmel,at91sam9260-wdt"
;
reg
=
<
0xfffffe40
0x10
>;
interrupts
=
<
1
IRQ_TYPE_LEVEL_HIGH
7
>;
...
...
arch/arm/mach-at91/Kconfig
浏览文件 @
5a451f11
...
...
@@ -147,6 +147,13 @@ config TARGET_AT91SAM9X5EK
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_GARDENA_SMART_GATEWAY_AT91SAM
bool "GARDENA smart Gateway (AT91SAM)"
select AT91SAM9X5
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
select BOARD_EARLY_INIT_F
...
...
@@ -283,6 +290,7 @@ source "board/bluewater/snapper9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/gardena/smart-gateway-at91sam/Kconfig"
source "board/l+g/vinco/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
...
...
arch/arm/mach-at91/arm926ejs/Makefile
浏览文件 @
5a451f11
...
...
@@ -24,8 +24,10 @@ obj-y += timer.o
endif
ifndef
CONFIG_SKIP_LOWLEVEL_INIT
ifndef
CONFIG_SKIP_LOWLEVEL_INIT_ONLY
obj-y
+=
lowlevel_init.o
endif
endif
ifdef
CONFIG_$(SPL_)SYS_THUMB_BUILD
ifndef
CONFIG_HAS_THUMB2
...
...
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
浏览文件 @
5a451f11
...
...
@@ -39,6 +39,8 @@ SECTIONS
*(.__end)
} >.sram
_image_binary_end = .;
.bss :
{
. = ALIGN(4);
...
...
arch/arm/mach-at91/armv7/sama5d2_devices.c
浏览文件 @
5a451f11
...
...
@@ -9,7 +9,7 @@
#include <asm/arch/clk.h>
#include <asm/arch/sama5d2.h>
int
cpu_is_sama5d2
(
void
)
int
_
cpu_is_sama5d2
(
void
)
{
unsigned
int
chip_id
=
get_chip_id
();
...
...
arch/arm/mach-at91/clock.c
浏览文件 @
5a451f11
...
...
@@ -5,12 +5,17 @@
*/
#include <common.h>
#include <dm.h>
#include <wdt.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_wdt.h>
#define EN_UPLL_TIMEOUT 500
static
struct
udevice
*
watchdog_dev
__attribute__
((
section
(
".data"
)))
=
NULL
;
void
at91_periph_clk_enable
(
int
id
)
{
struct
at91_pmc
*
pmc
=
(
struct
at91_pmc
*
)
ATMEL_BASE_PMC
;
...
...
@@ -118,3 +123,46 @@ void at91_pllicpr_init(u32 icpr)
writel
(
icpr
,
&
pmc
->
pllicpr
);
}
/* Called by macro WATCHDOG_RESET */
void
watchdog_reset
(
void
)
{
static
ulong
next_reset
;
ulong
now
;
if
(
!
watchdog_dev
)
return
;
now
=
get_timer
(
0
);
/* Do not reset the watchdog too often */
if
(
now
>
next_reset
)
{
next_reset
=
now
+
1000
;
/* reset every 1000ms */
wdt_reset
(
watchdog_dev
);
}
}
int
arch_early_init_r
(
void
)
{
struct
at91_wdt_priv
*
priv
;
/* Init watchdog */
if
(
uclass_get_device_by_seq
(
UCLASS_WDT
,
0
,
&
watchdog_dev
))
{
debug
(
"Watchdog: Not found by seq!
\n
"
);
if
(
uclass_get_device
(
UCLASS_WDT
,
0
,
&
watchdog_dev
))
{
puts
(
"Watchdog: Not found!
\n
"
);
return
0
;
}
}
priv
=
dev_get_priv
(
watchdog_dev
);
if
(
!
priv
)
{
printf
(
"Watchdog: priv not available!
\n
"
);
return
0
;
}
wdt_start
(
watchdog_dev
,
priv
->
timeout
*
1000
,
0
);
printf
(
"Watchdog: Started
\n
"
);
return
0
;
}
arch/arm/mach-at91/include/mach/at91_wdt.h
浏览文件 @
5a451f11
...
...
@@ -25,6 +25,12 @@ typedef struct at91_wdt {
u32
sr
;
}
at91_wdt_t
;
struct
at91_wdt_priv
{
void
__iomem
*
regs
;
u32
regval
;
u32
timeout
;
};
#endif
/* Watchdog Control Register */
...
...
@@ -43,4 +49,8 @@ typedef struct at91_wdt {
#define AT91_WDT_MR_WDDBGHLT 0x10000000
#define AT91_WDT_MR_WDIDLEHLT 0x20000000
/* Hardware timeout in seconds */
#define WDT_MAX_TIMEOUT 16
#define WDT_DEFAULT_TIMEOUT 2
#endif
arch/arm/mach-at91/include/mach/sama5d2.h
浏览文件 @
5a451f11
...
...
@@ -222,6 +222,9 @@
#define ARCH_EXID_SAMA5D27C_D1G 0x00000033
#define ARCH_EXID_SAMA5D28C_D1G 0x00000013
/* Checked if defined in ethernet driver macb */
#define cpu_is_sama5d2 _cpu_is_sama5d2
/* PIT Timer(PIT_PIIR) */
#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
...
...
@@ -231,7 +234,7 @@
#ifndef __ASSEMBLY__
unsigned
int
get_chip_id
(
void
);
unsigned
int
get_extension_chip_id
(
void
);
int
cpu_is_sama5d2
(
void
);
int
_
cpu_is_sama5d2
(
void
);
unsigned
int
has_lcdc
(
void
);
char
*
get_cpu_name
(
void
);
#endif
...
...
arch/arm/mach-at91/spl_at91.c
浏览文件 @
5a451f11
...
...
@@ -75,6 +75,16 @@ void __weak spl_board_init(void)
void
board_init_f
(
ulong
dummy
)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
int
ret
;
ret
=
spl_early_init
();
if
(
ret
)
{
debug
(
"spl_early_init() failed: %d
\n
"
,
ret
);
hang
();
}
#endif
lowlevel_clock_init
();
#if !defined(CONFIG_WDT_AT91)
at91_disable_wdt
();
...
...
board/gardena/smart-gateway-at91sam/Kconfig
0 → 100644
浏览文件 @
5a451f11
if TARGET_GARDENA_SMART_GATEWAY_AT91SAM
config SYS_BOARD
default "smart-gateway-at91sam"
config SYS_VENDOR
default "gardena"
config SYS_CONFIG_NAME
default "gardena-smart-gateway-at91sam"
endif
board/gardena/smart-gateway-at91sam/MAINTAINERS
0 → 100644
浏览文件 @
5a451f11
GARDENA_SMART_GATEWAY_AT91SAM BOARD
M: Stefan Roese <sr@denx.de>
S: Maintained
F: board/gardena/smart-gateway-at91sam/
F: include/configs/gardena-smart-gateway-at91sam.h
F: configs/gardena-smart-gateway-at91sam_defconfig
F: arch/arm/dts/gardena-smart-gateway-at91sam.dts
board/gardena/smart-gateway-at91sam/Makefile
0 → 100644
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# SPDX-License-Identifier: GPL-2.0+
obj-y
+=
board.o
ifdef
CONFIG_SPL_BUILD
obj-y
+=
spl.o
endif
board/gardena/smart-gateway-at91sam/board.c
0 → 100644
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Atmel Corporation
* Copyright (C) 2019 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <debug_uart.h>
#include <led.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/clk.h>
DECLARE_GLOBAL_DATA_PTR
;
static
void
at91_prepare_cpu_var
(
void
)
{
env_set
(
"cpu"
,
get_cpu_name
());
}
int
board_late_init
(
void
)
{
at91_prepare_cpu_var
();
if
(
IS_ENABLED
(
CONFIG_LED
))
led_default_state
();
return
0
;
}
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void
board_debug_uart_init
(
void
)
{
at91_seriald_hw_init
();
}
#endif
int
board_early_init_f
(
void
)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init
();
#endif
return
0
;
}
int
board_init
(
void
)
{
/* Address of boot parameters */
gd
->
bd
->
bi_boot_params
=
CONFIG_SYS_SDRAM_BASE
+
0x100
;
return
0
;
}
int
dram_init
(
void
)
{
gd
->
ram_size
=
get_ram_size
((
void
*
)
CONFIG_SYS_SDRAM_BASE
,
CONFIG_SYS_SDRAM_SIZE
);
return
0
;
}
board/gardena/smart-gateway-at91sam/spl.c
0 → 100644
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Atmel Corporation
* Copyright (C) 2019 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <nand.h>
#include <spl.h>
#include <asm/arch/at91sam9x5_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
static
void
at91sam9x5ek_nand_hw_init
(
void
)
{
struct
at91_smc
*
smc
=
(
struct
at91_smc
*
)
ATMEL_BASE_SMC
;
struct
at91_matrix
*
matrix
=
(
struct
at91_matrix
*
)
ATMEL_BASE_MATRIX
;
unsigned
long
csa
;
/* Enable CS3 */
csa
=
readl
(
&
matrix
->
ebicsa
);
csa
|=
AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA
;
/* NAND flash on D16 */
csa
|=
AT91_MATRIX_NFD0_ON_D16
;
/* Configure IO drive */
csa
&=
~
AT91_MATRIX_EBI_EBI_IOSR_NORMAL
;
writel
(
csa
,
&
matrix
->
ebicsa
);
/* Configure SMC CS3 for NAND/SmartMedia */
writel
(
AT91_SMC_SETUP_NWE
(
1
)
|
AT91_SMC_SETUP_NCS_WR
(
0
)
|
AT91_SMC_SETUP_NRD
(
1
)
|
AT91_SMC_SETUP_NCS_RD
(
0
),
&
smc
->
cs
[
3
].
setup
);
writel
(
AT91_SMC_PULSE_NWE
(
3
)
|
AT91_SMC_PULSE_NCS_WR
(
5
)
|
AT91_SMC_PULSE_NRD
(
4
)
|
AT91_SMC_PULSE_NCS_RD
(
6
),
&
smc
->
cs
[
3
].
pulse
);
writel
(
AT91_SMC_CYCLE_NWE
(
5
)
|
AT91_SMC_CYCLE_NRD
(
6
),
&
smc
->
cs
[
3
].
cycle
);
writel
(
AT91_SMC_MODE_RM_NRD
|
AT91_SMC_MODE_WM_NWE
|
AT91_SMC_MODE_EXNW_DISABLE
|
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_MODE_DBW_16
|
#else
/* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_MODE_DBW_8
|
#endif
AT91_SMC_MODE_TDF_CYCLE
(
1
),
&
smc
->
cs
[
3
].
mode
);
at91_periph_clk_enable
(
ATMEL_ID_PIOCD
);
/* Configure RDY/BSY */
at91_set_gpio_input
(
CONFIG_SYS_NAND_READY_PIN
,
1
);
/* Enable NandFlash */
at91_set_gpio_output
(
CONFIG_SYS_NAND_ENABLE_PIN
,
1
);
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
0
,
1
);
/* NAND OE */
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
1
,
1
);
/* NAND WE */
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
2
,
1
);
/* NAND ALE */
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
3
,
1
);
/* NAND CLE */
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
6
,
1
);
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
7
,
1
);
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
8
,
1
);
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
9
,
1
);
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
10
,
1
);
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
11
,
1
);
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
12
,
1
);
at91_pio3_set_a_periph
(
AT91_PIO_PORTD
,
13
,
1
);
}
void
at91_spl_board_init
(
void
)
{
at91sam9x5ek_nand_hw_init
();
}
static
void
ddr2_conf
(
struct
atmel_mpddrc_config
*
ddr2
)
{
ddr2
->
md
=
(
ATMEL_MPDDRC_MD_DBW_16_BITS
|
ATMEL_MPDDRC_MD_DDR2_SDRAM
);
ddr2
->
cr
=
(
ATMEL_MPDDRC_CR_NC_COL_10
|
ATMEL_MPDDRC_CR_NR_ROW_13
|
ATMEL_MPDDRC_CR_CAS_DDR_CAS3
|
ATMEL_MPDDRC_CR_NB_8BANKS
|
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
);
ddr2
->
rtr
=
0x411
;
ddr2
->
tpr0
=
(
6
<<
ATMEL_MPDDRC_TPR0_TRAS_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TRCD_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TWR_OFFSET
|
8
<<
ATMEL_MPDDRC_TPR0_TRC_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TRP_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TRRD_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TWTR_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TMRD_OFFSET
);
ddr2
->
tpr1
=
(
2
<<
ATMEL_MPDDRC_TPR1_TXP_OFFSET
|
200
<<
ATMEL_MPDDRC_TPR1_TXSRD_OFFSET
|
19
<<
ATMEL_MPDDRC_TPR1_TXSNR_OFFSET
|
18
<<
ATMEL_MPDDRC_TPR1_TRFC_OFFSET
);
ddr2
->
tpr2
=
(
7
<<
ATMEL_MPDDRC_TPR2_TFAW_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR2_TRTP_OFFSET
|
3
<<
ATMEL_MPDDRC_TPR2_TRPA_OFFSET
|
7
<<
ATMEL_MPDDRC_TPR2_TXARDS_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR2_TXARD_OFFSET
);
}
void
mem_init
(
void
)
{
struct
at91_matrix
*
matrix
=
(
struct
at91_matrix
*
)
ATMEL_BASE_MATRIX
;
struct
at91_pmc
*
pmc
=
(
struct
at91_pmc
*
)
ATMEL_BASE_PMC
;
struct
atmel_mpddrc_config
ddr2
;
unsigned
long
csa
;
ddr2_conf
(
&
ddr2
);
/* Enable DDR2 clock */
writel
(
AT91_PMC_DDR
,
&
pmc
->
scer
);
/* Chip select 1 is for DDR2/SDRAM */
csa
=
readl
(
&
matrix
->
ebicsa
);
csa
|=
AT91_MATRIX_EBI_CS1A_SDRAMC
;
csa
&=
~
AT91_MATRIX_EBI_DBPU_OFF
;
csa
|=
AT91_MATRIX_EBI_DBPD_OFF
;
csa
|=
AT91_MATRIX_EBI_EBI_IOSR_NORMAL
;
writel
(
csa
,
&
matrix
->
ebicsa
);
/* DDRAM2 Controller initialize */
ddr2_init
(
ATMEL_BASE_DDRSDRC
,
ATMEL_BASE_CS1
,
&
ddr2
);
}
board/ronetix/pm9g45/pm9g45.c
浏览文件 @
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...
...
@@ -124,7 +124,7 @@ int board_init(void)
/* arch number of AT91SAM9M10G45EK-Board */
gd
->
bd
->
bi_arch_number
=
MACH_TYPE_PM9G45
;
/* adress of boot parameters */
gd
->
bd
->
bi_boot_params
=
PHYS_SDRAM
+
0x100
;
gd
->
bd
->
bi_boot_params
=
CONFIG_SYS_SDRAM_BASE
+
0x100
;
#ifdef CONFIG_CMD_NAND
pm9g45_nand_hw_init
();
...
...
@@ -139,15 +139,15 @@ int board_init(void)
int
dram_init
(
void
)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd
->
ram_size
=
get_ram_size
((
void
*
)
PHYS_SDRAM
,
PH
YS_SDRAM_SIZE
);
gd
->
ram_size
=
get_ram_size
((
void
*
)
CONFIG_SYS_SDRAM_BASE
,
CONFIG_S
YS_SDRAM_SIZE
);
return
0
;
}
int
dram_init_banksize
(
void
)
{
gd
->
bd
->
bi_dram
[
0
].
start
=
PHYS_SDRAM
;
gd
->
bd
->
bi_dram
[
0
].
size
=
PH
YS_SDRAM_SIZE
;
gd
->
bd
->
bi_dram
[
0
].
start
=
CONFIG_SYS_SDRAM_BASE
;
gd
->
bd
->
bi_dram
[
0
].
size
=
CONFIG_S
YS_SDRAM_SIZE
;
return
0
;
}
...
...
configs/gardena-smart-gateway-at91sam_defconfig
0 → 100644
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CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x22900000
CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SMBIOS_PRODUCT_NAME="at91sam9x5ek"
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand0"
CONFIG_MTDPARTS_DEFAULT="nand0:1536k(uboot),1024k(unused),512k(dtb_old),4608k(kernel_old),86528k(ubi),-(rootfs_old)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupts interrupt-parent interrupts-extended dmas dma-names"
CONFIG_ENV_IS_IN_UBI=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
# CONFIG_CONFIG_UBI_SILENCE_MSG is not set
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
# CONFIG_SYS_WHITE_ON_BLACK is not set
CONFIG_WATCHDOG=y
CONFIG_WDT=y
CONFIG_WDT_AT91=y
# CONFIG_UBIFS_SILENCE_MSG is not set
CONFIG_USE_TINY_PRINTF=y
configs/pm9g45_defconfig
浏览文件 @
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...
...
@@ -2,27 +2,57 @@ CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
CONFIG_TARGET_PM9G45=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_
SYS_EXTRA_OPTIONS="AT91SAM9G45"
CONFIG_
NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="fbcon=rotate:3 console=tty0 console=ttyS0,115200 root=/dev/mtdblock4 mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,1664k(env),2M(linux)ro,-(root) rw rootfstype=jffs2"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
configs/smartweb_defconfig
浏览文件 @
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...
...
@@ -59,6 +59,5 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_WDT=y
CONFIG_WDT_AT91=y
CONFIG_AT91_HW_WDT_TIMEOUT=y
CONFIG_SPL_TINY_MEMSET=y
# CONFIG_EFI_LOADER is not set
configs/taurus_defconfig
浏览文件 @
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...
...
@@ -62,5 +62,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_WDT=y
CONFIG_WDT_AT91=y
CONFIG_AT91_HW_WDT_TIMEOUT=y
CONFIG_USE_TINY_PRINTF=y
drivers/net/macb.c
浏览文件 @
5a451f11
...
...
@@ -550,8 +550,14 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
for
(
i
=
0
;
i
<
MACB_AUTONEG_TIMEOUT
/
100
;
i
++
)
{
status
=
macb_mdio_read
(
macb
,
MII_BMSR
);
if
(
status
&
BMSR_LSTATUS
)
if
(
status
&
BMSR_LSTATUS
)
{
/*
* Delay a bit after the link is established,
* so that the next xfer does not fail
*/
mdelay
(
10
);
break
;
}
udelay
(
100
);
}
}
...
...
drivers/pinctrl/pinctrl-at91.c
浏览文件 @
5a451f11
...
...
@@ -37,6 +37,9 @@ struct at91_pinctrl_priv {
#define OUTPUT BIT(7)
#define OUTPUT_VAL_SHIFT 8
#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
#define SLEWRATE_SHIFT 9
#define SLEWRATE_MASK 0x1
#define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
#define DEBOUNCE BIT(16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
...
...
@@ -50,10 +53,22 @@ struct at91_pinctrl_priv {
* DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
* strength when there is no dt config for it.
*/
#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
enum
drive_strength_bit
{
DRIVE_STRENGTH_BIT_DEF
,
DRIVE_STRENGTH_BIT_LOW
,
DRIVE_STRENGTH_BIT_MED
,
DRIVE_STRENGTH_BIT_HI
,
};
#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
DRIVE_STRENGTH_SHIFT)
enum
slewrate_bit
{
SLEWRATE_BIT_DIS
,
SLEWRATE_BIT_ENA
,
};
#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
enum
at91_mux
{
AT91_MUX_GPIO
=
0
,
...
...
@@ -90,6 +105,7 @@ struct at91_pinctrl_mux_ops {
void
(
*
disable_schmitt_trig
)(
struct
at91_port
*
pio
,
u32
mask
);
void
(
*
set_drivestrength
)(
struct
at91_port
*
pio
,
u32
pin
,
u32
strength
);
void
(
*
set_slewrate
)(
struct
at91_port
*
pio
,
u32
pin
,
u32
slewrate
);
};
static
u32
two_bit_pin_value_shift_amount
(
u32
pin
)
...
...
@@ -238,11 +254,52 @@ static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
/* strength is inverse on SAM9x5s with our defines
* 0 = hi, 1 = med, 2 = low, 3 = rsvd */
setting
=
DRIVE_STRENGTH_
HI
-
setting
;
setting
=
DRIVE_STRENGTH_
BIT_MSK
(
HI
)
-
setting
;
set_drive_strength
(
reg
,
pin
,
setting
);
}
static
void
at91_mux_sam9x60_set_drivestrength
(
struct
at91_port
*
pio
,
u32
pin
,
u32
setting
)
{
void
*
reg
=
&
pio
->
driver12
;
u32
tmp
;
if
(
setting
<=
DRIVE_STRENGTH_BIT_DEF
||
setting
==
DRIVE_STRENGTH_BIT_MED
||
setting
>
DRIVE_STRENGTH_BIT_HI
)
return
;
tmp
=
readl
(
reg
);
/* Strength is 0: low, 1: hi */
if
(
setting
==
DRIVE_STRENGTH_BIT_LOW
)
tmp
&=
~
BIT
(
pin
);
else
tmp
|=
BIT
(
pin
);
writel
(
tmp
,
reg
);
}
static
void
at91_mux_sam9x60_set_slewrate
(
struct
at91_port
*
pio
,
u32
pin
,
u32
setting
)
{
void
*
reg
=
&
pio
->
reserved12
[
3
];
u32
tmp
;
if
(
setting
<
SLEWRATE_BIT_DIS
||
setting
>
SLEWRATE_BIT_ENA
)
return
;
tmp
=
readl
(
reg
);
if
(
setting
==
SLEWRATE_BIT_DIS
)
tmp
&=
~
BIT
(
pin
);
else
tmp
|=
BIT
(
pin
);
writel
(
tmp
,
reg
);
}
static
struct
at91_pinctrl_mux_ops
at91rm9200_ops
=
{
.
mux_A_periph
=
at91_mux_set_A_periph
,
.
mux_B_periph
=
at91_mux_set_B_periph
,
...
...
@@ -273,6 +330,19 @@ static struct at91_pinctrl_mux_ops sama5d3_ops = {
.
set_drivestrength
=
at91_mux_sama5d3_set_drivestrength
,
};
static
struct
at91_pinctrl_mux_ops
sam9x60_ops
=
{
.
mux_A_periph
=
at91_mux_pio3_set_A_periph
,
.
mux_B_periph
=
at91_mux_pio3_set_B_periph
,
.
mux_C_periph
=
at91_mux_pio3_set_C_periph
,
.
mux_D_periph
=
at91_mux_pio3_set_D_periph
,
.
set_deglitch
=
at91_mux_pio3_set_deglitch
,
.
set_debounce
=
at91_mux_pio3_set_debounce
,
.
set_pulldown
=
at91_mux_pio3_set_pulldown
,
.
disable_schmitt_trig
=
at91_mux_pio3_disable_schmitt_trig
,
.
set_drivestrength
=
at91_mux_sam9x60_set_drivestrength
,
.
set_slewrate
=
at91_mux_sam9x60_set_slewrate
,
};
static
void
at91_mux_gpio_disable
(
struct
at91_port
*
pio
,
u32
mask
)
{
writel
(
mask
,
&
pio
->
pdr
);
...
...
@@ -339,6 +409,9 @@ static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
if
(
ops
->
set_drivestrength
)
ops
->
set_drivestrength
(
pio
,
pin
,
(
config
&
DRIVE_STRENGTH
)
>>
DRIVE_STRENGTH_SHIFT
);
if
(
ops
->
set_slewrate
)
ops
->
set_slewrate
(
pio
,
pin
,
(
config
&
SLEWRATE
)
>>
SLEWRATE_SHIFT
);
return
0
;
}
...
...
@@ -440,6 +513,7 @@ static const struct udevice_id at91_pinctrl_match[] = {
{
.
compatible
=
"atmel,sama5d3-pinctrl"
,
.
data
=
(
ulong
)
&
sama5d3_ops
},
{
.
compatible
=
"atmel,at91sam9x5-pinctrl"
,
.
data
=
(
ulong
)
&
at91sam9x5_ops
},
{
.
compatible
=
"atmel,at91rm9200-pinctrl"
,
.
data
=
(
ulong
)
&
at91rm9200_ops
},
{
.
compatible
=
"microchip,sam9x60-pinctrl"
,
.
data
=
(
ulong
)
&
sam9x60_ops
},
{}
};
...
...
drivers/serial/Kconfig
浏览文件 @
5a451f11
...
...
@@ -508,6 +508,15 @@ config ATMEL_USART
configured in the device tree, and input clock frequency can
be got from the clk node.
config SPL_UART_CLOCK
int "SPL fixed UART input clock"
depends on ATMEL_USART && SPL && !SPL_CLK
default 132096000 if ARCH_AT91
help
Provide a fixed clock value as input to the UART controller. This
might be needed on platforms which can't enable CONFIG_SPL_CLK
because of SPL image size restrictions.
config BCM283X_MU_SERIAL
bool "Support for BCM283x Mini-UART"
depends on DM_SERIAL && ARCH_BCM283X
...
...
drivers/serial/atmel_usart.c
浏览文件 @
5a451f11
...
...
@@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = {
.
setbrg
=
atmel_serial_setbrg
,
};
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
static
int
atmel_serial_enable_clk
(
struct
udevice
*
dev
)
{
struct
atmel_serial_priv
*
priv
=
dev_get_priv
(
dev
);
/* Use fixed clock value in SPL */
priv
->
usart_clk_rate
=
CONFIG_SPL_UART_CLOCK
;
return
0
;
}
#else
static
int
atmel_serial_enable_clk
(
struct
udevice
*
dev
)
{
struct
atmel_serial_priv
*
priv
=
dev_get_priv
(
dev
);
...
...
@@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
return
0
;
}
#endif
static
int
atmel_serial_probe
(
struct
udevice
*
dev
)
{
...
...
drivers/watchdog/Kconfig
浏览文件 @
5a451f11
...
...
@@ -139,10 +139,6 @@ config WDT_AT91
Select this to enable Microchip watchdog timer, which can be found on
some AT91 devices.
config AT91_HW_WDT_TIMEOUT
bool "AT91 watchdog timeout specified"
depends on WDT_AT91
config WDT_MT7621
bool "MediaTek MT7621 watchdog timer support"
depends on WDT && ARCH_MT7620
...
...
drivers/watchdog/at91sam9_wdt.c
浏览文件 @
5a451f11
...
...
@@ -17,6 +17,7 @@
#include <asm/io.h>
#include <asm/arch/at91_wdt.h>
#include <common.h>
#include <div64.h>
#include <dm.h>
#include <errno.h>
#include <wdt.h>
...
...
@@ -30,28 +31,21 @@ DECLARE_GLOBAL_DATA_PTR;
*/
#define WDT_SEC2TICKS(s) (((s) << 8) - 1)
/* Hardware timeout in seconds */
#define WDT_MAX_TIMEOUT 16
#define WDT_MIN_TIMEOUT 0
#define WDT_DEFAULT_TIMEOUT 2
struct
at91_wdt_priv
{
void
__iomem
*
regs
;
u32
regval
;
u32
timeout
;
};
/*
* Set the watchdog time interval in 1/256Hz (write-once)
* Counter is 12 bit.
*/
static
int
at91_wdt_start
(
struct
udevice
*
dev
,
u64
timeout_s
,
ulong
flags
)
static
int
at91_wdt_start
(
struct
udevice
*
dev
,
u64
timeout_
m
s
,
ulong
flags
)
{
struct
at91_wdt_priv
*
priv
=
dev_get_priv
(
dev
);
u32
timeout
=
WDT_SEC2TICKS
(
timeout_s
);
u64
timeout
;
u32
ticks
;
if
(
timeout_s
>
WDT_MAX_TIMEOUT
||
timeout_s
<
WDT_MIN_TIMEOUT
)
timeout
=
priv
->
timeout
;
/* Calculate timeout in seconds and the resulting ticks */
timeout
=
timeout_ms
;
do_div
(
timeout
,
1000
);
timeout
=
min_t
(
u64
,
timeout
,
WDT_MAX_TIMEOUT
);
ticks
=
WDT_SEC2TICKS
(
timeout
);
/* Check if disabled */
if
(
readl
(
priv
->
regs
+
AT91_WDT_MR
)
&
AT91_WDT_MR_WDDIS
)
{
...
...
@@ -65,12 +59,10 @@ static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags)
* Since WDV is a 12-bit counter, the maximum period is
* 4096 / 256 = 16 seconds.
*/
priv
->
regval
=
AT91_WDT_MR_WDRSTEN
/* causes watchdog reset */
|
AT91_WDT_MR_WDDBGHLT
/* disabled in debug mode */
|
AT91_WDT_MR_WDD
(
0xfff
)
/* restart at any time */
|
AT91_WDT_MR_WDV
(
timeout
);
/* timer value */
|
AT91_WDT_MR_WDV
(
ticks
);
/* timer value */
writel
(
priv
->
regval
,
priv
->
regs
+
AT91_WDT_MR
);
return
0
;
...
...
@@ -115,10 +107,12 @@ static int at91_wdt_probe(struct udevice *dev)
if
(
!
priv
->
regs
)
return
-
EINVAL
;
#if
def CONFIG_AT91_HW_WDT_TIMEOUT
#if
CONFIG_IS_ENABLED(OF_CONTROL)
priv
->
timeout
=
dev_read_u32_default
(
dev
,
"timeout-sec"
,
WDT_DEFAULT_TIMEOUT
);
debug
(
"%s: timeout %d"
,
__func__
,
priv
->
timeout
);
#else
priv
->
timeout
=
WDT_DEFAULT_TIMEOUT
;
#endif
debug
(
"%s: Probing wdt%u
\n
"
,
__func__
,
dev
->
seq
);
...
...
include/configs/corvus.h
浏览文件 @
5a451f11
...
...
@@ -139,4 +139,7 @@
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
#endif
include/configs/gardena-smart-gateway-at91sam.h
0 → 100644
浏览文件 @
5a451f11
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 Atmel Corporation
* Copyright (C) 2019 Stefan Roese <sr@denx.de>
*
* Configuation settings for the GARDENA smart Gateway (AT91SAM9G25)
*/
#ifndef __CONFIG_H__
#define __CONFIG_H__
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000
/* 12 MHz crystal */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY
/* required until (g)pio is fixed */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
/* 128 megs */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
/* NAND flash */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#define CONFIG_SYS_LOAD_ADDR 0x22000000
/* load address */
/* environment organization */
#define CONFIG_ENV_UBI_PART "ubi"
#define CONFIG_ENV_UBI_VOLUME "env"
#define CONFIG_ENV_UBI_VOLUME_REDUND "env_r"
#define CONFIG_ENV_SIZE (64 << 10)
/* SPL */
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x7000
#define CONFIG_SPL_STACK 0x308000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define CONFIG_SYS_AT91_PLLA 0x20c73f03
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_RAW_ONLY
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
#endif
include/configs/pm9g45.h
浏览文件 @
5a451f11
...
...
@@ -15,110 +15,119 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* SoC must be defined first, before hardware.h is included.
* In this case SoC is defined in boards.cfg.
*/
#include <asm/hardware.h>
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
#define CONFIG_MACH_TYPE MACH_TYPE_PM9G45
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000
/* from 12 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
/* slow clock xtal */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CMDLINE_TAG 1
/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000
/* from 12 MHz crystal */
#define CONFIG_CMDLINE_TAG
/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
#define CONFIG_SYS_USE_NANDFLASH 1
/* LED */
#define CONFIG_AT91_LED
#define CONFIG_RED_LED GPIO_PIN_PD(31)
/* this is the user1 led */
#define CONFIG_GREEN_LED GPIO_PIN_PD(0)
/* this is the user2 led */
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY
/* required until (g)pio is fixed */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE 1
#define CONFIG_JFFS2_CMDLINE 1
#define CONFIG_JFFS2_NAND 1
#define CONFIG_JFFS2_DEV "nand0"
/* NAND dev jffs2 lives on */
#define CONFIG_JFFS2_PART_OFFSET 0
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024)
/* partition */
#define CONFIG_BOOTP_BOOTFILESIZE
/* SDRAM */
#define PHYS_SDRAM 0x70000000
#define PHYS_SDRAM_SIZE 0x08000000
/* 128 megs */
#define CONFIG_SYS_SDRAM_BASE 0x70000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE
0x40000000
#define CONFIG_SYS_NAND_DBW_8
1
#define CONFIG_SYS_MAX_NAND_DEVICE
1
#define CONFIG_SYS_NAND_BASE
ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE
(1 <<
21)
#define CONFIG_SYS_NAND_MASK_ALE
BIT(
21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE
(1 <<
22)
#define CONFIG_SYS_NAND_ENABLE_PIN
GPIO_PIN_PC(14)
#define CONFIG_SYS_NAND_READY_PIN
GPIO_PIN_PD(3)
#define CONFIG_SYS_NAND_MASK_CLE
BIT(
22)
#define CONFIG_SYS_NAND_ENABLE_PIN
AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN
AT91_PIN_PD3
#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif
/* Ethernet */
#define CONFIG_MACB 1
#define CONFIG_RMII 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R 1
/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000
/* _UHP_OHCI_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
/* board specific(not enough SRAM) */
#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000
/* load addr */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_SYS_LOAD_ADDR 0x22000000
/* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */
#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_BOOTCOMMAND \
"nand read 0x70000000 0x200000 0x300000;" \
"bootm 0x70000000"
#elif CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \
"fatload mmc 0:1 0x72000000 zImage; " \
"bootz 0x72000000 - 0x71000000"
#endif
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
0x1000)
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
128 * 1024, 0x1000)
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE 0x010000
#define CONFIG_SPL_STACK 0x310000
#define CONFIG_SYS_MONITOR_LEN 0x80000
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_BSS_START_ADDR 0x70000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SPL_ATMEL_SIZE
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define CONFIG_SYS_AT91_PLLA 0x20c73f03
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#endif
include/configs/smartweb.h
浏览文件 @
5a451f11
...
...
@@ -221,4 +221,8 @@
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#endif
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
#endif
/* __CONFIG_H */
include/configs/taurus.h
浏览文件 @
5a451f11
...
...
@@ -173,4 +173,7 @@
#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
#define CONFIG_SYS_AT91_PLLB 0x10193F05
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
#endif
include/dt-bindings/pinctrl/at91.h
浏览文件 @
5a451f11
...
...
@@ -17,6 +17,7 @@
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
#define AT91_PINCTRL_OUTPUT (1 << 7)
#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
#define AT91_PINCTRL_SLEWRATE (1 << 9)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
...
...
@@ -27,6 +28,9 @@
#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9)
#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9)
#define AT91_PIOA 0
#define AT91_PIOB 1
#define AT91_PIOC 2
...
...
include/watchdog.h
浏览文件 @
5a451f11
...
...
@@ -51,9 +51,15 @@ int init_func_watchdog_reset(void);
#if defined(__ASSEMBLY__)
#define WATCHDOG_RESET bl watchdog_reset
#else
extern
void
watchdog_reset
(
void
);
/* Don't require the watchdog to be enabled in SPL */
#if defined(CONFIG_SPL_BUILD) && \
!defined(CONFIG_SPL_WATCHDOG_SUPPORT)
#define WATCHDOG_RESET() {}
#else
extern
void
watchdog_reset
(
void
);
#define WATCHDOG_RESET watchdog_reset
#define WATCHDOG_RESET watchdog_reset
#endif
#endif
#else
/*
...
...
scripts/Makefile.spl
浏览文件 @
5a451f11
...
...
@@ -179,10 +179,10 @@ MKIMAGEFLAGS_boot.bin = -T atmelimage
ifeq
($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y)
MKIMAGEFLAGS_boot.bin
+=
-n
$(
shell
$(obj)
/../tools/atmel_pmecc_params
)
boot.bin
:
$(obj)/../tools/atmel_pmecc_params
$(obj)/
boot.bin
:
$(obj)/../tools/atmel_pmecc_params
endif
boot.bin
:
$(obj)/u-boot-spl.bin FORCE
$(obj)/
boot.bin
:
$(obj)/u-boot-spl.bin FORCE
$(
call
if_changed,mkimage
)
else
ifdef
CONFIG_ARCH_ZYNQ
...
...
@@ -225,7 +225,7 @@ endif
endif
ifeq
($(CONFIG_SYS_SOC),"at91")
ALL-y
+=
boot.bin
ALL-y
+=
$(obj)
/
boot.bin
endif
ALL-$(CONFIG_SPL_X86_16BIT_INIT)
+=
$(obj)
/u-boot-x86-16bit-spl.bin
...
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