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体验新版 GitCode,发现更多精彩内容 >>
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59abd15b
编写于
6月 06, 2008
作者:
S
Sergei Poselenov
提交者:
Andrew Fleming-AFLEMING
6月 11, 2008
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
Socrates: Added FPGA mapping. LAWs and TLBs cleanup.
Signed-off-by:
N
Sergei Poselenov
<
sposelenov@emcraft.com
>
上级
740280e6
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
27 addition
and
30 deletion
+27
-30
board/socrates/law.c
board/socrates/law.c
+8
-7
board/socrates/socrates.c
board/socrates/socrates.c
+7
-1
board/socrates/tlb.c
board/socrates/tlb.c
+8
-17
include/configs/socrates.h
include/configs/socrates.h
+4
-5
未找到文件。
board/socrates/law.c
浏览文件 @
59abd15b
...
...
@@ -33,13 +33,12 @@
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x
7fff_ffff DDR 2G
* 0x0000_0000 0x
2fff_ffff DDR 512M
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0x
dfff_ffff RapidIO 512
M
* 0xe000_0000 0xe00
0_ffff CCSR 1M
* 0xc000_0000 0x
c00f_ffff FPGA 1
M
* 0xe000_0000 0xe00
f_ffff CCSR 1M (mapped by CCSRBAR)
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf800_0000 0xf80f_ffff BCSR 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
* 0xfc00_0000 0xffff_ffff FLASH 64M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
...
...
@@ -49,9 +48,11 @@
struct
law_entry
law_table
[]
=
{
SET_LAW_ENTRY
(
1
,
CFG_DDR_SDRAM_BASE
,
LAW_SIZE_512M
,
LAW_TRGT_IF_DDR
),
SET_LAW_ENTRY
(
2
,
CFG_PCI1_MEM_PHYS
,
LAW_SIZE_512M
,
LAW_TRGT_IF_PCI
),
SET_LAW_ENTRY
(
3
,
CFG_LBC_FLASH_BASE
,
LAW_SIZE_
128
M
,
LAW_TRGT_IF_LBC
),
SET_LAW_ENTRY
(
3
,
CFG_LBC_FLASH_BASE
,
LAW_SIZE_
64
M
,
LAW_TRGT_IF_LBC
),
SET_LAW_ENTRY
(
4
,
CFG_PCI1_IO_PHYS
,
LAW_SIZE_16M
,
LAW_TRGT_IF_PCI
),
SET_LAW_ENTRY
(
5
,
CFG_RIO_MEM_BASE
,
LAWAR_SIZE_512M
,
LAW_TRGT_IF_RIO
),
#if defined(CFG_FPGA_BASE)
SET_LAW_ENTRY
(
5
,
CFG_FPGA_BASE
,
LAWAR_SIZE_1M
,
LAW_TRGT_IF_LBC
),
#endif
};
int
num_law_entries
=
ARRAY_SIZE
(
law_table
);
board/socrates/socrates.c
浏览文件 @
59abd15b
...
...
@@ -37,6 +37,9 @@
#include <fdt_support.h>
#include <asm/io.h>
#if defined(CFG_FPGA_BASE)
#include "upm_table.h"
#endif
DECLARE_GLOBAL_DATA_PTR
;
extern
flash_info_t
flash_info
[];
/* FLASH chips info */
...
...
@@ -76,7 +79,10 @@ int checkboard (void)
* Initialize local bus.
*/
local_bus_init
();
#if defined(CFG_FPGA_BASE)
/* Init UPMA for FPGA access */
upmconfig
(
UPMA
,
(
uint
*
)
UPMTableA
,
sizeof
(
UPMTableA
)
/
sizeof
(
int
));
#endif
return
0
;
}
...
...
board/socrates/tlb.c
浏览文件 @
59abd15b
...
...
@@ -46,16 +46,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 0
, 1: 128
M Non-cacheable, guarded
* 0xf
8000000 128
M FLASH
* TLB 0
: 64
M Non-cacheable, guarded
* 0xf
c000000 64
M FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY
(
1
,
CFG_FLASH_BASE
,
CFG_FLASH_BASE
,
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
1
,
BOOKE_PAGESZ_64M
,
1
),
SET_TLB_ENTRY
(
1
,
CFG_FLASH_BASE
+
0x4000000
,
CFG_FLASH_BASE
+
0x4000000
,
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
0
,
BOOKE_PAGESZ_64M
,
1
),
/*
* TLB 2: 256M Non-cacheable, guarded
...
...
@@ -73,21 +70,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
3
,
BOOKE_PAGESZ_256M
,
1
),
#if defined(CFG_FPGA_BASE)
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
SET_TLB_ENTRY
(
1
,
CFG_RIO_MEM_BASE
,
CFG_RIO_MEM_BASE
,
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
4
,
BOOKE_PAGESZ_256M
,
1
),
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
* TLB 4: 1M Non-cacheable, guarded
* 0xc0000000 1M FPGA and NAND
*/
SET_TLB_ENTRY
(
1
,
CFG_
RIO_MEM_BASE
+
0x10000000
,
CFG_RIO_MEM_BASE
+
0x10000000
,
SET_TLB_ENTRY
(
1
,
CFG_
FPGA_BASE
,
CFG_FPGA_BASE
,
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
5
,
BOOKE_PAGESZ_256M
,
1
),
0
,
4
,
BOOKE_PAGESZ_1M
,
1
),
#endif
/*
* TLB 6: 64M Non-cacheable, guarded
...
...
include/configs/socrates.h
浏览文件 @
59abd15b
...
...
@@ -216,11 +216,6 @@
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/* necessary for the LM75 chip */
#define CFG_EEPROM_PAGE_WRITE_BITS 4
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000
/* base address */
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x20000000
/* 128M */
/*
* General PCI
* Memory space is mapped 1-1.
...
...
@@ -414,4 +409,8 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_USB_STORAGE 1
/* FPGA and NAND */
#define CFG_FPGA_BASE 0xc0000000
#define CFG_BR3_PRELIM 0xc0001881
/* UPMA, 32-bit */
#define CFG_OR3_PRELIM 0xfff00000
/* 1 MB */
#endif
/* __CONFIG_H */
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