提交 58932ec6 编写于 作者: Y York Sun

armv8: ls2088ardb: Add 3DS RDIMM support

Tested with MTA72ASS8G72PSZ-2S6G1. This is 3DS RDIMM module with x4
DDR chips. LS2088ARDB needs to be modified to connect all DQS signals.
Some of them are grounded by default for x8 chips. Tested with RDIMM
MTA18ASF2G72PDZ on main memory controllers. DP-DDR doesn't support
RDIMM. Dropped related timing table.
Signed-off-by: NYork Sun <york.sun@nxp.com>
上级 f513de6c
......@@ -85,6 +85,8 @@ found:
pbsp->wrlvl_ctl_3);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
if (popts->registered_dimm_en)
printf("WARN: RDIMM not supported.\n");
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
popts->otf_burst_chop_en = 0;
......
......@@ -55,24 +55,9 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
/* DP-DDR DIMM */
static const struct board_specific_parameters rdimm2[] = {
/*
* memory controller 2
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{2, 1666, 0, 8, 0x0F, 0x0D0C0A09, 0x0B0C0E08,},
{2, 1900, 0, 8, 0x10, 0x0F0D0B0A, 0x0B0E0F09,},
{2, 2200, 0, 8, 0x13, 0x120F0E0B, 0x0D10110B,},
{}
};
......@@ -85,7 +70,7 @@ static const struct board_specific_parameters *udimms[] = {
static const struct board_specific_parameters *rdimms[] = {
rdimm0,
rdimm0,
rdimm2,
udimm2, /* DP-DDR doesn't support RDIMM */
};
......
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