提交 5568fb44 编写于 作者: D Dirk Eibach 提交者: Tom Rini

board: gdsys: Configure bridge on DP501 to support DDC only

The I2C bridge on DP501 supports EDID, MCCS and HDCP by default.
Allow EDID only to avoid I2C address conflicts.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
上级 cccd4f40
...@@ -54,6 +54,7 @@ static void dp501_link_training(u8 addr) ...@@ -54,6 +54,7 @@ static void dp501_link_training(u8 addr)
void dp501_powerup(u8 addr) void dp501_powerup(u8 addr)
{ {
dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */ dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */ i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */ dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */ dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
......
...@@ -199,9 +199,10 @@ ...@@ -199,9 +199,10 @@
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* Probing DP501 I2C-Bridge will hang */
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x30}, {0, 0x37}, {0, 0x3a}, \ #ifndef CONFIG_TRAILBLAZER
{0, 0x3b}, {0, 0x50} } #define CONFIG_CMD_I2C
#endif
#define CONFIG_PCA9698 /* NXP PCA9698 */ #define CONFIG_PCA9698 /* NXP PCA9698 */
......
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