提交 5564ed5d 编写于 作者: S Simon Glass

rockchip: rk3288: Move rockchip_get_cru() out of the driver

This function is called from outside the driver. It should be placed into
common SoC code. Move it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
上级 c8a6bc96
......@@ -25,6 +25,13 @@
#define PERI_HCLK_HZ 148500000
#define PERI_PCLK_HZ 74250000
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3288_clk_priv {
struct rk3288_grf *grf;
struct rk3288_cru *cru;
ulong rate;
};
struct rk3288_cru {
struct rk3288_pll {
u32 con0;
......
......@@ -9,9 +9,25 @@
#include <dm.h>
#include <syscon.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3288.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3288_cru), devp);
}
void *rockchip_get_cru(void)
{
struct rk3288_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}
......@@ -30,12 +30,6 @@ struct rk3288_clk_plat {
#endif
};
struct rk3288_clk_priv {
struct rk3288_grf *grf;
struct rk3288_cru *cru;
ulong rate;
};
struct pll_div {
u32 nr;
u32 nf;
......@@ -140,21 +134,6 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
void *rockchip_get_cru(void)
{
struct rk3288_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}
static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
{
......
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