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体验新版 GitCode,发现更多精彩内容 >>
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53885e76
编写于
7月 26, 2018
作者:
T
Tom Rini
浏览文件
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浏览文件
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差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-tegra
上级
a57d45db
2eea1269
变更
9
隐藏空白更改
内联
并排
Showing
9 changed file
with
57 addition
and
33 deletion
+57
-33
arch/arm/dts/tegra30-apalis.dts
arch/arm/dts/tegra30-apalis.dts
+0
-3
arch/arm/dts/tegra30-beaver.dts
arch/arm/dts/tegra30-beaver.dts
+0
-3
arch/arm/include/asm/arch-tegra124/flow.h
arch/arm/include/asm/arch-tegra124/flow.h
+4
-6
arch/arm/include/asm/proc-armv/ptrace.h
arch/arm/include/asm/proc-armv/ptrace.h
+1
-0
arch/arm/lib/psci-dt.c
arch/arm/lib/psci-dt.c
+6
-0
arch/arm/mach-tegra/board2.c
arch/arm/mach-tegra/board2.c
+4
-0
arch/arm/mach-tegra/powergate.c
arch/arm/mach-tegra/powergate.c
+1
-19
arch/arm/mach-tegra/tegra124/cpu.c
arch/arm/mach-tegra/tegra124/cpu.c
+40
-2
scripts/config_whitelist.txt
scripts/config_whitelist.txt
+1
-0
未找到文件。
arch/arm/dts/tegra30-apalis.dts
浏览文件 @
53885e76
...
@@ -119,9 +119,6 @@
...
@@ -119,9 +119,6 @@
vccio
-
supply
=
<&
sys_3v3_reg
>;
vccio
-
supply
=
<&
sys_3v3_reg
>;
regulators
{
regulators
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
0
>;
/*
SW1
:
+
V1
.35
_VDDIO_DDR
*/
/*
SW1
:
+
V1
.35
_VDDIO_DDR
*/
vdd1_reg
:
vdd1
{
vdd1_reg
:
vdd1
{
regulator
-
name
=
"vddio_ddr_1v35"
;
regulator
-
name
=
"vddio_ddr_1v35"
;
...
...
arch/arm/dts/tegra30-beaver.dts
浏览文件 @
53885e76
...
@@ -102,9 +102,6 @@
...
@@ -102,9 +102,6 @@
vccio
-
supply
=
<&
vdd_5v_in_reg
>;
vccio
-
supply
=
<&
vdd_5v_in_reg
>;
regulators
{
regulators
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
0
>;
vdd1_reg
:
vdd1
{
vdd1_reg
:
vdd1
{
regulator
-
name
=
"vddio_ddr_1v2"
;
regulator
-
name
=
"vddio_ddr_1v2"
;
regulator
-
min
-
microvolt
=
<
1200000
>;
regulator
-
min
-
microvolt
=
<
1200000
>;
...
...
arch/arm/include/asm/arch-tegra124/flow.h
浏览文件 @
53885e76
...
@@ -29,7 +29,7 @@ struct flow_ctlr {
...
@@ -29,7 +29,7 @@ struct flow_ctlr {
u32
flow_dbg_cnt0
;
/* offset 0x48 */
u32
flow_dbg_cnt0
;
/* offset 0x48 */
u32
flow_dbg_cnt1
;
/* offset 0x4c */
u32
flow_dbg_cnt1
;
/* offset 0x4c */
u32
flow_dbg_qual
;
/* offset 0x50 */
u32
flow_dbg_qual
;
/* offset 0x50 */
u32
flow_ct
lr
_spare
;
/* offset 0x54 */
u32
flow_ct
rl
_spare
;
/* offset 0x54 */
u32
ram_repair_cluster1
;
/* offset 0x58 */
u32
ram_repair_cluster1
;
/* offset 0x58 */
};
};
...
@@ -48,10 +48,8 @@ struct flow_ctlr {
...
@@ -48,10 +48,8 @@ struct flow_ctlr {
#define CSR_WAIT_WFI_SHIFT 8
#define CSR_WAIT_WFI_SHIFT 8
#define CSR_PWR_OFF_STS (1 << 16)
#define CSR_PWR_OFF_STS (1 << 16)
/* RAM_REPAIR, 0x40, 0x58 */
#define RAM_REPAIR_REQ BIT(0)
enum
{
#define RAM_REPAIR_STS BIT(1)
RAM_REPAIR_REQ
=
0x1
<<
0
,
#define RAM_REPAIR_BYPASS_EN BIT(2)
RAM_REPAIR_STS
=
0x1
<<
1
,
};
#endif
/* _TEGRA124_FLOW_H_ */
#endif
/* _TEGRA124_FLOW_H_ */
arch/arm/include/asm/proc-armv/ptrace.h
浏览文件 @
53885e76
...
@@ -37,6 +37,7 @@ struct pt_regs {
...
@@ -37,6 +37,7 @@ struct pt_regs {
#define FIQ_MODE 0x11
#define FIQ_MODE 0x11
#define IRQ_MODE 0x12
#define IRQ_MODE 0x12
#define SVC_MODE 0x13
#define SVC_MODE 0x13
#define MON_MODE 0x16
#define ABT_MODE 0x17
#define ABT_MODE 0x17
#define HYP_MODE 0x1a
#define HYP_MODE 0x1a
#define UND_MODE 0x1b
#define UND_MODE 0x1b
...
...
arch/arm/lib/psci-dt.c
浏览文件 @
53885e76
...
@@ -67,6 +67,8 @@ init_psci_node:
...
@@ -67,6 +67,8 @@ init_psci_node:
psci_ver
=
sec_firmware_support_psci_version
();
psci_ver
=
sec_firmware_support_psci_version
();
#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver
=
ARM_PSCI_VER_1_0
;
psci_ver
=
ARM_PSCI_VER_1_0
;
#elif defined(CONFIG_ARMV7_PSCI_0_2)
psci_ver
=
ARM_PSCI_VER_0_2
;
#endif
#endif
if
(
psci_ver
>=
ARM_PSCI_VER_1_0
)
{
if
(
psci_ver
>=
ARM_PSCI_VER_1_0
)
{
tmp
=
fdt_setprop_string
(
fdt
,
nodeoff
,
tmp
=
fdt_setprop_string
(
fdt
,
nodeoff
,
...
@@ -114,6 +116,10 @@ init_psci_node:
...
@@ -114,6 +116,10 @@ init_psci_node:
if
(
tmp
)
if
(
tmp
)
return
tmp
;
return
tmp
;
tmp
=
fdt_setprop_string
(
fdt
,
nodeoff
,
"status"
,
"okay"
);
if
(
tmp
)
return
tmp
;
#endif
#endif
return
0
;
return
0
;
}
}
arch/arm/mach-tegra/board2.c
浏览文件 @
53885e76
...
@@ -249,6 +249,10 @@ static ulong carveout_size(void)
...
@@ -249,6 +249,10 @@ static ulong carveout_size(void)
{
{
#ifdef CONFIG_ARM64
#ifdef CONFIG_ARM64
return
SZ_512M
;
return
SZ_512M
;
#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
// BASE+SIZE might not == 4GB. If so, we want the carveout to cover
// from BASE to 4GB, not BASE to BASE+SIZE.
return
(
0
-
CONFIG_ARMV7_SECURE_BASE
);
#else
#else
return
0
;
return
0
;
#endif
#endif
...
...
arch/arm/mach-tegra/powergate.c
浏览文件 @
53885e76
...
@@ -8,7 +8,7 @@
...
@@ -8,7 +8,7 @@
#include <asm/io.h>
#include <asm/io.h>
#include <asm/types.h>
#include <asm/types.h>
#include <asm/arch/flow.h>
#include <asm/arch/powergate.h>
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
#include <asm/arch/tegra.h>
...
@@ -74,29 +74,11 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id)
...
@@ -74,29 +74,11 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id)
return
0
;
return
0
;
}
}
static
void
tegra_powergate_ram_repair
(
void
)
{
#ifdef CONFIG_TEGRA124
struct
flow_ctlr
*
flow
=
(
struct
flow_ctlr
*
)
NV_PA_FLOW_BASE
;
/* Request RAM repair for cluster 0 and wait until complete */
setbits_le32
(
&
flow
->
ram_repair
,
RAM_REPAIR_REQ
);
while
(
!
(
readl
(
&
flow
->
ram_repair
)
&
RAM_REPAIR_STS
))
;
/* Same for cluster 1 */
setbits_le32
(
&
flow
->
ram_repair_cluster1
,
RAM_REPAIR_REQ
);
while
(
!
(
readl
(
&
flow
->
ram_repair_cluster1
)
&
RAM_REPAIR_STS
))
;
#endif
}
int
tegra_powergate_sequence_power_up
(
enum
tegra_powergate
id
,
int
tegra_powergate_sequence_power_up
(
enum
tegra_powergate
id
,
enum
periph_id
periph
)
enum
periph_id
periph
)
{
{
int
err
;
int
err
;
tegra_powergate_ram_repair
();
reset_set_enable
(
periph
,
1
);
reset_set_enable
(
periph
,
1
);
err
=
tegra_powergate_power_on
(
id
);
err
=
tegra_powergate_power_on
(
id
);
...
...
arch/arm/mach-tegra/tegra124/cpu.c
浏览文件 @
53885e76
...
@@ -104,6 +104,43 @@ static void remove_cpu_resets(void)
...
@@ -104,6 +104,43 @@ static void remove_cpu_resets(void)
writel
(
reg
,
&
clkrst
->
crc_rst_cpug_cmplx_clr
);
writel
(
reg
,
&
clkrst
->
crc_rst_cpug_cmplx_clr
);
}
}
static
void
tegra124_ram_repair
(
void
)
{
struct
flow_ctlr
*
flow
=
(
struct
flow_ctlr
*
)
NV_PA_FLOW_BASE
;
u32
ram_repair_timeout
;
/*usec*/
u32
val
;
/*
* Request the Flow Controller perform RAM repair whenever it turns on
* a power rail that requires RAM repair.
*/
clrbits_le32
(
&
flow
->
ram_repair
,
RAM_REPAIR_BYPASS_EN
);
/* Request SW trigerred RAM repair by setting req bit */
/* cluster 0 */
setbits_le32
(
&
flow
->
ram_repair
,
RAM_REPAIR_REQ
);
/* Wait for completion (status == 0) */
ram_repair_timeout
=
500
;
do
{
udelay
(
1
);
val
=
readl
(
&
flow
->
ram_repair
);
}
while
(
!
(
val
&
RAM_REPAIR_STS
)
&&
ram_repair_timeout
--
);
if
(
!
ram_repair_timeout
)
debug
(
"Ram Repair cluster0 failed
\n
"
);
/* cluster 1 */
setbits_le32
(
&
flow
->
ram_repair_cluster1
,
RAM_REPAIR_REQ
);
/* Wait for completion (status == 0) */
ram_repair_timeout
=
500
;
do
{
udelay
(
1
);
val
=
readl
(
&
flow
->
ram_repair_cluster1
);
}
while
(
!
(
val
&
RAM_REPAIR_STS
)
&&
ram_repair_timeout
--
);
if
(
!
ram_repair_timeout
)
debug
(
"Ram Repair cluster1 failed
\n
"
);
}
/**
/**
* Tegra124 requires some special clock initialization, including setting up
* Tegra124 requires some special clock initialization, including setting up
* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
...
@@ -254,10 +291,11 @@ void start_cpu(u32 reset_vector)
...
@@ -254,10 +291,11 @@ void start_cpu(u32 reset_vector)
&
pmc
->
pmc_pwrgate_timer_mult
);
&
pmc
->
pmc_pwrgate_timer_mult
);
enable_cpu_power_rail
();
enable_cpu_power_rail
();
powerup_cpus
();
tegra124_ram_repair
();
enable_cpu_clocks
();
enable_cpu_clocks
();
clock_enable_coresight
(
1
);
clock_enable_coresight
(
1
);
remove_cpu_resets
();
writel
(
reset_vector
,
EXCEP_VECTOR_CPU_RESET_VECTOR
);
writel
(
reset_vector
,
EXCEP_VECTOR_CPU_RESET_VECTOR
);
powerup_cpu
s
();
remove_cpu_reset
s
();
debug
(
"%s exit, should continue @ reset_vector
\n
"
,
__func__
);
debug
(
"%s exit, should continue @ reset_vector
\n
"
,
__func__
);
}
}
scripts/config_whitelist.txt
浏览文件 @
53885e76
...
@@ -51,6 +51,7 @@ CONFIG_ARMADA100
...
@@ -51,6 +51,7 @@ CONFIG_ARMADA100
CONFIG_ARMADA100_FEC
CONFIG_ARMADA100_FEC
CONFIG_ARMADA168
CONFIG_ARMADA168
CONFIG_ARMADA_39X
CONFIG_ARMADA_39X
CONFIG_ARMV7_PSCI_0_2
CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE
CONFIG_ARMV7_SECURE_MAX_SIZE
...
...
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