提交 5342a710 编写于 作者: S Sandeep Paulraj 提交者: Albert Aribaud

DaVinci DM6467: Fix Build Error

This commit fixes build errors on the DM6467 port.
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
上级 b157dd51
...@@ -60,6 +60,12 @@ ...@@ -60,6 +60,12 @@
#define DDR_PLLDIV PLLC_PLLDIV1 #define DDR_PLLDIV PLLC_PLLDIV1
#endif #endif
#ifdef CONFIG_SOC_DM646X
#define DSP_PLLDIV PLLC_PLLDIV1
#define ARM_PLLDIV PLLC_PLLDIV2
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
#ifdef CONFIG_SOC_DA8XX #ifdef CONFIG_SOC_DA8XX
const dv_reg * const sysdiv[7] = { const dv_reg * const sysdiv[7] = {
&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2, &davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
...@@ -145,7 +151,11 @@ static inline unsigned pll_postdiv(volatile void *pllbase) ...@@ -145,7 +151,11 @@ static inline unsigned pll_postdiv(volatile void *pllbase)
static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
{ {
volatile void *pllbase = (volatile void *) pll_addr; volatile void *pllbase = (volatile void *) pll_addr;
#ifdef CONFIG_SOC_DM646X
unsigned base = CFG_REFCLK_FREQ / 1000;
#else
unsigned base = CONFIG_SYS_HZ_CLOCK / 1000; unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
#endif
/* the PLL might be bypassed */ /* the PLL might be bypassed */
if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) { if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
...@@ -176,6 +186,12 @@ int print_cpuinfo(void) ...@@ -176,6 +186,12 @@ int print_cpuinfo(void)
return 0; return 0;
} }
#ifdef DAVINCI_DM6467EVM
unsigned int davinci_arm_clk_get()
{
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
}
#endif
#endif #endif
/* /*
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册