ARM: socfpga: fix data and tag latency values for pl310 cache controller

The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>

arch/arm/mach-socfpga/misc.c

@@ -62,8 +62,8 @@ void v7_outer_cache_enable(void)
 	/* Disable the L2 cache */
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
-	writel(0x111, &pl310->pl310_tag_latency_ctrl);
-	writel(0x121, &pl310->pl310_data_latency_ctrl);
+	writel(0x0, &pl310->pl310_tag_latency_ctrl);
+	writel(0x10, &pl310->pl310_data_latency_ctrl);
 
 	/* enable BRESP, instruction and data prefetch, full line of zeroes */
 	setbits_le32(&pl310->pl310_aux_ctrl,