Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x

Kconfig

@@ -251,6 +251,16 @@ config FIT
 
 if FIT
 
+config FIT_EXTERNAL_OFFSET
+	hex "Text Base"
+	default 0x0
+	help
+	  This specifies a data offset in fit image.
+	  The offset is from data payload offset to the beginning of
+	  fit image header. When specifies a offset, specific data
+	  could be put in the hole between data payload and fit image
+	  header, such as CSF data on i.MX platform.
+
 config FIT_ENABLE_SHA256_SUPPORT
 	bool "Support SHA256 checksum of FIT image contents"
 	default y

Makefile

@@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
 	>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
 
 quiet_cmd_mkfitimage = MKIMAGE $@
-cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \
+cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\
 	>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
 
 quiet_cmd_cat = CAT     $@
@@ -1207,6 +1207,11 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
 SPL: spl/u-boot-spl.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
+ifeq ($(CONFIG_ARCH_IMX8M), y)
+flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
+	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+endif
+
 u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 

arch/arm/Kconfig

@@ -694,7 +694,7 @@ config ARCH_IMX8
 	select DM
 	select OF_CONTROL
 
-config ARCH_MX8M
+config ARCH_IMX8M
 	bool "NXP i.MX8M platform"
 	select ARM64
 	select DM
@@ -1451,7 +1451,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig"
 
 source "arch/arm/mach-imx/imx8/Kconfig"
 
-source "arch/arm/mach-imx/mx8m/Kconfig"
+source "arch/arm/mach-imx/imx8m/Kconfig"
 
 source "arch/arm/mach-imx/mxs/Kconfig"
 

arch/arm/Makefile

@@ -103,11 +103,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
 libs-y += arch/arm/mach-imx/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
 libs-y += arch/arm/mach-imx/
 endif
 endif

arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2

@@ -8,3 +8,14 @@ Freescale LayerScape with Chassis Generation 2
 
 This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
 for example LS1043A.
+
+Watchdog support Overview
+-------------------
+Support watchdog driver for LSCH2. The driver is disabled in default.
+You can enable it by setting CONFIG_IMX_WATCHDOG.
+Use following config to set watchdog timeout, if this config is not defined,
+the default timeout value is 128s which is the maximum. Set 10 seconds for
+example:
+    #define CONFIG_WATCHDOG_TIMEOUT_MSECS 10000
+Set CONFIG_WATCHDOG_RESET_DISABLE to disable reset watchdog, so that the
+watchdog will not be fed in u-boot.

arch/arm/dts/Makefile

@@ -466,6 +466,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 
 dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
 
+dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
+
 dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a7795-h3ulcb-u-boot.dtb \
 	r8a7795-salvator-x-u-boot.dtb \

arch/arm/dts/fsl-imx8mq-evk.dts

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x40000000 0x00020000;
+
+#include "fsl-imx8mq.dtsi"
+
+/ {
+	model = "Freescale i.MX8MQ EVK";
+	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+	chosen {
+		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		ledpwm2 {
+			label = "PWM2";
+			pwms = <&pwm2 0 50000>;
+			max-brightness = <255>;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx8mq-evk {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
+				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+				MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL	0x4000007f
+				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA	0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL	0x4000007f
+				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA	0x4000007f
+			>;
+		};
+
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
+				MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
+				MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
+				MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
+				MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
+				MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
+
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x83
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc3
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc3
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc3
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc3
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc3
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc3
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc3
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc3
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc3
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x83
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x85
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc5
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc5
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc5
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc5
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc5
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc5
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc5
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc5
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc5
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x85
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x87
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc7
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc7
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc7
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc7
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc7
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc7
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc7
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc7
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc7
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x87
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc5
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc5
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc5
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc5
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x87
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc7
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc7
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc7
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc7
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
+				MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
+				MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+			>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-disabled;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pfuze100@08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3ab {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "disabled";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+	disp-dev = "mipi_dsi_northwest";
+	display = <&display0>;
+
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+			clock-frequency = <9200000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <8>;
+			hback-porch = <4>;
+			hsync-len = <41>;
+			vback-porch = <2>;
+			vfront-porch = <4>;
+			vsync-len = <10>;
+
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+
+	flash0: n25q256a@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};

arch/arm/dts/vf.dtsi

@@ -89,6 +89,12 @@
 				status = "disabled";
 			};
 
+			iomuxc: iomuxc@40048000 {
+				compatible = "fsl,vf610-iomuxc";
+				reg = <0x40048000 0x1000>;
+				fsl,mux_mask = <0x700000>;
+			};
+
 			gpio0: gpio@40049000 {
 				compatible = "fsl,vf610-gpio";
 				reg = <0x400ff000 0x40>;

arch/arm/include/asm/arch-imx/cpu.h

@@ -24,7 +24,7 @@
 #define MXC_CPU_MX6QP		0x69
 #define MXC_CPU_MX7S		0x71 /* dummy ID */
 #define MXC_CPU_MX7D		0x72
-#define MXC_CPU_MX8MQ		0x82
+#define MXC_CPU_IMX8MQ		0x82
 #define MXC_CPU_IMX8QXP_A0	0x90 /* dummy ID */
 #define MXC_CPU_IMX8QXP		0x92 /* dummy ID */
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
@@ -32,7 +32,7 @@
 
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
-#define MXC_SOC_MX8M		0x80
+#define MXC_SOC_IMX8M		0x80
 #define MXC_SOC_IMX8		0x90 /* dummy */
 #define MXC_SOC_MX7ULP		0xE0 /* dummy */
 
@@ -41,6 +41,7 @@
 #define CHIP_REV_1_2            0x12
 #define CHIP_REV_1_5            0x15
 #define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_1            0x21
 #define CHIP_REV_2_5            0x25
 #define CHIP_REV_3_0            0x30
 

arch/arm/include/asm/arch-mx8m/clock.h → arch/arm/include/asm/arch-imx8m/clock.h

@@ -10,6 +10,8 @@
 
 #include <linux/bitops.h>
 
+#define MHZ(X)	((X) * 1000000UL)
+
 enum pll_clocks {
 	ANATOP_ARM_PLL,
 	ANATOP_GPU_PLL,
@@ -631,6 +633,26 @@ enum frac_pll_out_val {
 	FRAC_PLL_OUT_1600M,
 };
 
+#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k)			\
+	{								\
+		.clk		=	(_rate),			\
+		.alt_root_sel	=	(_m),				\
+		.alt_pre_div	=	(_p),				\
+		.apb_root_sel	=	(_s),				\
+		.apb_pre_div	=	(_k),				\
+	}
+
+struct dram_bypass_clk_setting {
+	ulong clk;
+	int alt_root_sel;
+	enum root_pre_div alt_pre_div;
+	int apb_root_sel;
+	enum root_pre_div apb_pre_div;
+};
+
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
+void dram_disable_bypass(void);
 u32 imx_get_fecclk(void);
 u32 imx_get_uartclk(void);
 int clock_init(void);

arch/arm/include/asm/arch-mx8m/crm_regs.h → arch/arm/include/asm/arch-imx8m/crm_regs.h

@@ -3,7 +3,7 @@
  * Copyright 2017 NXP
  */
 
-#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
-#define _ASM_ARCH_MX8M_CRM_REGS_H
+#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H
+#define _ASM_ARCH_IMX8M_CRM_REGS_H
 /* Dummy header, some imx-common code needs this file */
 #endif

arch/arm/include/asm/arch-mx8m/gpio.h → arch/arm/include/asm/arch-imx8m/gpio.h

@@ -3,8 +3,8 @@
  * Copyright 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8M_GPIO_H
-#define __ASM_ARCH_MX8M_GPIO_H
+#ifndef __ASM_ARCH_IMX8M_GPIO_H
+#define __ASM_ARCH_IMX8M_GPIO_H
 
 #include <asm/mach-imx/gpio.h>
 

arch/arm/include/asm/arch-mx8m/imx-regs.h → arch/arm/include/asm/arch-imx8m/imx-regs.h

@@ -3,8 +3,8 @@
  * Copyright 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8M_REGS_H__
-#define __ASM_ARCH_MX8M_REGS_H__
+#ifndef __ASM_ARCH_IMX8M_REGS_H__
+#define __ASM_ARCH_IMX8M_REGS_H__
 
 #include <asm/mach-imx/regs-lcdif.h>
 

arch/arm/include/asm/arch-mx8m/mx8mq_pins.h → arch/arm/include/asm/arch-imx8m/imx8mq_pins.h

@@ -3,8 +3,8 @@
  * Copyright (C) 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8MQ_PINS_H__
-#define __ASM_ARCH_MX8MQ_PINS_H__
+#ifndef __ASM_ARCH_IMX8MQ_PINS_H__
+#define __ASM_ARCH_IMX8MQ_PINS_H__
 
 #include <asm/mach-imx/iomux-v3.h>
 

arch/arm/include/asm/arch-imx8m/lpddr4_define.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LPDDR4_DEFINE_H_
+#define __LPDDR4_DEFINE_H_
+
+#define LPDDR4_DVFS_DBI
+#define DDR_ONE_RANK
+/* #define LPDDR4_DBI_ON */
+#define DFI_BUG_WR
+#define M845S_4GBx2
+#define PRETRAIN
+
+/* DRAM MR setting */
+#ifdef LPDDR4_DBI_ON
+#define LPDDR4_MR3			0xf1
+#define LPDDR4_PHY_DMIPinPresent	0x1
+#else
+#define LPDDR4_MR3			0x31
+#define LPDDR4_PHY_DMIPinPresent	0x0
+#endif
+
+#ifdef DDR_ONE_RANK
+#define LPDDR4_CS			0x1
+#else
+#define LPDDR4_CS			0x3
+#endif
+
+/* PHY training feature */
+#define LPDDR4_HDT_CTL_2D		0xC8
+#define LPDDR4_HDT_CTL_3200_1D		0xC8
+#define LPDDR4_HDT_CTL_400_1D		0xC8
+#define LPDDR4_HDT_CTL_100_1D		0xC8
+
+/* 400/100 training seq */
+#define LPDDR4_TRAIN_SEQ_P2		0x121f
+#define LPDDR4_TRAIN_SEQ_P1		0x121f
+#define LPDDR4_TRAIN_SEQ_P0		0x121f
+#define LPDDR4_TRAIN_SEQ_100		0x121f
+#define LPDDR4_TRAIN_SEQ_400		0x121f
+
+/* 2D share & weight */
+#define LPDDR4_2D_WEIGHT		0x1f7f
+#define LPDDR4_2D_SHARE			1
+#define LPDDR4_CATRAIN_3200_1d		0
+#define LPDDR4_CATRAIN_400		0
+#define LPDDR4_CATRAIN_100		0
+#define LPDDR4_CATRAIN_3200_2d		0
+
+/* MRS parameter */
+/* for LPDDR4 Rtt */
+#define LPDDR4_RTT40			6
+#define LPDDR4_RTT48			5
+#define LPDDR4_RTT60			4
+#define LPDDR4_RTT80			3
+#define LPDDR4_RTT120			2
+#define LPDDR4_RTT240			1
+#define LPDDR4_RTT_DIS			0
+
+/* for LPDDR4 Ron */
+#define LPDDR4_RON34			7
+#define LPDDR4_RON40			6
+#define LPDDR4_RON48			5
+#define LPDDR4_RON60			4
+#define LPDDR4_RON80			3
+
+#define LPDDR4_PHY_ADDR_RON60		0x1
+#define LPDDR4_PHY_ADDR_RON40		0x3
+#define LPDDR4_PHY_ADDR_RON30		0x7
+#define LPDDR4_PHY_ADDR_RON24		0xf
+#define LPDDR4_PHY_ADDR_RON20		0x1f
+
+/* for read channel */
+#define LPDDR4_RON			LPDDR4_RON40
+#define LPDDR4_PHY_RTT			30
+#define LPDDR4_PHY_VREF_VALUE		17
+
+/* for write channel */
+#define LPDDR4_PHY_RON			30
+#define LPDDR4_PHY_ADDR_RON		LPDDR4_PHY_ADDR_RON40
+#define LPDDR4_RTT_DQ			LPDDR4_RTT40
+#define LPDDR4_RTT_CA			LPDDR4_RTT40
+#define LPDDR4_RTT_CA_BANK0		LPDDR4_RTT40
+#define LPDDR4_RTT_CA_BANK1		LPDDR4_RTT40
+#define LPDDR4_VREF_VALUE_CA		((1 << 6) | (0xd))
+#define LPDDR4_VREF_VALUE_DQ_RANK0	((1 << 6) | (0xd))
+#define LPDDR4_VREF_VALUE_DQ_RANK1	((1 << 6) | (0xd))
+#define LPDDR4_MR22_RANK0		((0 << 5) | (1 << 4) | (0 << 3) | \
+					(LPDDR4_RTT40))
+#define LPDDR4_MR22_RANK1		((1 << 5) | (1 << 4) | (1 << 3) | \
+					(LPDDR4_RTT40))
+
+#define LPDDR4_MR3_PU_CAL		1
+
+#endif /* __LPDDR4_DEFINE_H__ */

arch/arm/include/asm/arch-mx8m/sys_proto.h → arch/arm/include/asm/arch-imx8m/sys_proto.h

@@ -3,8 +3,8 @@
  * Copyright (C) 2017 NXP
  */
 
-#ifndef __ARCH_MX8M_SYS_PROTO_H
-#define __ARCH_MX8M_SYS_PROTO_H
+#ifndef __ARCH_IMX8M_SYS_PROTO_H
+#define __ARCH_NMX8M_SYS_PROTO_H
 
 #include <asm/mach-imx/sys_proto.h>
 

arch/arm/include/asm/arch-mx8m/ddr.h

-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 NXP
- */
-
-#ifndef __ASM_ARCH_MX8M_DDR_H
-#define __ASM_ARCH_MX8M_DDR_H
-
-#define DDRC_DDR_SS_GPR0		0x3d000000
-#define DDRC_IPS_BASE_ADDR_0		0x3f400000
-#define IP2APB_DDRPHY_IPS_BASE_ADDR(X)	(0x3c000000 + (X * 0x2000000))
-#define DDRPHY_MEM(X)			(0x3c000000 + (X * 0x2000000) + 0x50000)
-
-struct ddrc_freq {
-	u32 res0[8];
-	u32 derateen;
-	u32 derateint;
-	u32 res1[10];
-	u32 rfshctl0;
-	u32 res2[4];
-	u32 rfshtmg;
-	u32 rfshtmg1;
-	u32 res3[28];
-	u32 init3;
-	u32 init4;
-	u32 res;
-	u32 init6;
-	u32 init7;
-	u32 res4[4];
-	u32 dramtmg0;
-	u32 dramtmg1;
-	u32 dramtmg2;
-	u32 dramtmg3;
-	u32 dramtmg4;
-	u32 dramtmg5;
-	u32 dramtmg6;
-	u32 dramtmg7;
-	u32 dramtmg8;
-	u32 dramtmg9;
-	u32 dramtmg10;
-	u32 dramtmg11;
-	u32 dramtmg12;
-	u32 dramtmg13;
-	u32 dramtmg14;
-	u32 dramtmg15;
-	u32 dramtmg16;
-	u32 dramtmg17;
-	u32 res5[10];
-	u32 mramtmg0;
-	u32 mramtmg1;
-	u32 mramtmg4;
-	u32 mramtmg9;
-	u32 zqctl0;
-	u32 res6[3];
-	u32 dfitmg0;
-	u32 dfitmg1;
-	u32 res7[7];
-	u32 dfitmg2;
-	u32 dfitmg3;
-	u32 res8[33];
-	u32 odtcfg;
-};
-
-struct imx8m_ddrc_regs {
-	u32 mstr;
-	u32 stat;
-	u32 mstr1;
-	u32 res1;
-	u32 mrctrl0;
-	u32 mrctrl1;
-	u32 mrstat;
-	u32 mrctrl2;
-	u32 derateen;
-	u32 derateint;
-	u32 mstr2;
-	u32 res2;
-	u32 pwrctl;
-	u32 pwrtmg;
-	u32 hwlpctl;
-	u32 hwffcctl;
-	u32 hwffcstat;
-	u32 res3[3];
-	u32 rfshctl0;
-	u32 rfshctl1;
-	u32 rfshctl2;
-	u32 rfshctl4;
-	u32 rfshctl3;
-	u32 rfshtmg;
-	u32 rfshtmg1;
-	u32 res4;
-	u32 ecccfg0;
-	u32 ecccfg1;
-	u32 eccstat;
-	u32 eccclr;
-	u32 eccerrcnt;
-	u32 ecccaddr0;
-	u32 ecccaddr1;
-	u32 ecccsyn0;
-	u32 ecccsyn1;
-	u32 ecccsyn2;
-	u32 eccbitmask0;
-	u32 eccbitmask1;
-	u32 eccbitmask2;
-	u32 eccuaddr0;
-	u32 eccuaddr1;
-	u32 eccusyn0;
-	u32 eccusyn1;
-	u32 eccusyn2;
-	u32 eccpoisonaddr0;
-	u32 eccpoisonaddr1;
-	u32 crcparctl0;
-	u32 crcparctl1;
-	u32 crcparctl2;
-	u32 crcparstat;
-	u32 init0;
-	u32 init1;
-	u32 init2;
-	u32 init3;
-	u32 init4;
-	u32 init5;
-	u32 init6;
-	u32 init7;
-	u32 dimmctl;
-	u32 rankctl;
-	u32 res5;
-	u32 chctl;
-	u32 dramtmg0;
-	u32 dramtmg1;
-	u32 dramtmg2;
-	u32 dramtmg3;
-	u32 dramtmg4;
-	u32 dramtmg5;
-	u32 dramtmg6;
-	u32 dramtmg7;
-	u32 dramtmg8;
-	u32 dramtmg9;
-	u32 dramtmg10;
-	u32 dramtmg11;
-	u32 dramtmg12;
-	u32 dramtmg13;
-	u32 dramtmg14;
-	u32 dramtmg15;
-	u32 dramtmg16;
-	u32 dramtmg17;
-	u32 res6[10];
-	u32 mramtmg0;
-	u32 mramtmg1;
-	u32 mramtmg4;
-	u32 mramtmg9;
-	u32 zqctl0;
-	u32 zqctl1;
-	u32 zqctl2;
-	u32 zqstat;
-	u32 dfitmg0;
-	u32 dfitmg1;
-	u32 dfilpcfg0;
-	u32 dfilpcfg1;
-	u32 dfiupd0;
-	u32 dfiupd1;
-	u32 dfiupd2;
-	u32 res7;
-	u32 dfimisc;
-	u32 dfitmg2;
-	u32 dfitmg3;
-	u32 dfistat;
-	u32 dbictl;
-	u32 dfiphymstr;
-	u32 res8[14];
-	u32 addrmap0;
-	u32 addrmap1;
-	u32 addrmap2;
-	u32 addrmap3;
-	u32 addrmap4;
-	u32 addrmap5;
-	u32 addrmap6;
-	u32 addrmap7;
-	u32 addrmap8;
-	u32 addrmap9;
-	u32 addrmap10;
-	u32 addrmap11;
-	u32 res9[4];
-	u32 odtcfg;
-	u32 odtmap;
-	u32 res10[2];
-	u32 sched;
-	u32 sched1;
-	u32 sched2;
-	u32 perfhpr1;
-	u32 res11;
-	u32 perflpr1;
-	u32 res12;
-	u32 perfwr1;
-	u32 res13[4];
-	u32 dqmap0;
-	u32 dqmap1;
-	u32 dqmap2;
-	u32 dqmap3;
-	u32 dqmap4;
-	u32 dqmap5;
-	u32 res14[26];
-	u32 dbg0;
-	u32 dbg1;
-	u32 dbgcam;
-	u32 dbgcmd;
-	u32 dbgstat;
-	u32 res15[3];
-	u32 swctl;
-	u32 swstat;
-	u32 res16[2];
-	u32 ocparcfg0;
-	u32 ocparcfg1;
-	u32 ocparcfg2;
-	u32 ocparcfg3;
-	u32 ocparstat0;
-	u32 ocparstat1;
-	u32 ocparwlog0;
-	u32 ocparwlog1;
-	u32 ocparwlog2;
-	u32 ocparawlog0;
-	u32 ocparawlog1;
-	u32 ocparrlog0;
-	u32 ocparrlog1;
-	u32 ocpararlog0;
-	u32 ocpararlog1;
-	u32 poisoncfg;
-	u32 poisonstat;
-	u32 adveccindex;
-	union  {
-		u32 adveccstat;
-		u32 eccapstat;
-	};
-	u32 eccpoisonpat0;
-	u32 eccpoisonpat1;
-	u32 eccpoisonpat2;
-	u32 res17[6];
-	u32 caparpoisonctl;
-	u32 caparpoisonstat;
-	u32 res18[2];
-	u32 dynbsmstat;
-	u32 res19[18];
-	u32 pstat;
-	u32 pccfg;
-	struct {
-		u32 pcfgr;
-		u32 pcfgw;
-		u32 pcfgc;
-		struct {
-			u32 pcfgidmaskch0;
-			u32 pcfidvaluech0;
-		} pcfgid[16];
-		u32 pctrl;
-		u32 pcfgqos0;
-		u32 pcfgqos1;
-		u32 pcfgwqos0;
-		u32 pcfgwqos1;
-		u32 res[4];
-	} pcfg[16];
-	struct {
-		u32 sarbase;
-		u32 sarsize;
-	} sar[4];
-	u32 sbrctl;
-	u32 sbrstat;
-	u32 sbrwdata0;
-	u32 sbrwdata1;
-	u32 pdch;
-	u32 res20[755];
-	/* umctl2_regs_dch1 */
-	u32 ch1_stat;
-	u32 res21[2];
-	u32 ch1_mrctrl0;
-	u32 ch1_mrctrl1;
-	u32 ch1_mrstat;
-	u32 ch1_mrctrl2;
-	u32 res22[4];
-	u32 ch1_pwrctl;
-	u32 ch1_pwrtmg;
-	u32 ch1_hwlpctl;
-	u32 res23[15];
-	u32 ch1_eccstat;
-	u32 ch1_eccclr;
-	u32 ch1_eccerrcnt;
-	u32 ch1_ecccaddr0;
-	u32 ch1_ecccaddr1;
-	u32 ch1_ecccsyn0;
-	u32 ch1_ecccsyn1;
-	u32 ch1_ecccsyn2;
-	u32 ch1_eccbitmask0;
-	u32 ch1_eccbitmask1;
-	u32 ch1_eccbitmask2;
-	u32 ch1_eccuaddr0;
-	u32 ch1_eccuaddr1;
-	u32 ch1_eccusyn0;
-	u32 ch1_eccusyn1;
-	u32 ch1_eccusyn2;
-	u32 res24[2];
-	u32 ch1_crcparctl0;
-	u32 res25[2];
-	u32 ch1_crcparstat;
-	u32 res26[46];
-	u32 ch1_zqctl2;
-	u32 ch1_zqstat;
-	u32 res27[11];
-	u32 ch1_dfistat;
-	u32 res28[33];
-	u32 ch1_odtmap;
-	u32 res29[47];
-	u32 ch1_dbg1;
-	u32 ch1_dbgcam;
-	u32 ch1_dbgcmd;
-	u32 ch1_dbgstat;
-	u32 res30[123];
-	/* umctl2_regs_freq1 */
-	struct ddrc_freq freq1;
-	u32 res31[109];
-	/* umctl2_regs_addrmap_alt */
-	u32 addrmap0_alt;
-	u32 addrmap1_alt;
-	u32 addrmap2_alt;
-	u32 addrmap3_alt;
-	u32 addrmap4_alt;
-	u32 addrmap5_alt;
-	u32 addrmap6_alt;
-	u32 addrmap7_alt;
-	u32 addrmap8_alt;
-	u32 addrmap9_alt;
-	u32 addrmap10_alt;
-	u32 addrmap11_alt;
-	u32 res32[758];
-	/* umctl2_regs_freq2 */
-	struct ddrc_freq freq2;
-	u32 res33[879];
-	/* umctl2_regs_freq3 */
-	struct ddrc_freq freq3;
-};
-
-struct imx8m_ddrphy_regs {
-	u32 reg[0xf0000];
-};
-
-/* PHY State */
-enum pstate {
-	PS0,
-	PS1,
-	PS2,
-	PS3,
-};
-
-enum msg_response {
-	TRAIN_SUCCESS = 0x7,
-	TRAIN_STREAM_START = 0x8,
-	TRAIN_FAIL = 0xff,
-};
-
-#endif

arch/arm/include/asm/mach-imx/iomux-v3.h

@@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t;
 #define IOMUX_CONFIG_LPSR       0x20
 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
 				MUX_MODE_SHIFT)
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 #define PAD_CTL_DSE0		(0x0 << 0)
 #define PAD_CTL_DSE1		(0x1 << 0)
 #define PAD_CTL_DSE2		(0x2 << 0)

arch/arm/include/asm/mach-imx/regs-lcdif.h

@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8M)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
 #endif
 	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8M)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
 #endif
 	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
@@ -73,7 +73,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8M)
 	mxs_reg_32(hw_lcdif_thres)
 	mxs_reg_32(hw_lcdif_as_ctrl)
 	mxs_reg_32(hw_lcdif_as_buf)

arch/arm/include/asm/mach-imx/sys_proto.h

@@ -26,7 +26,7 @@
 
 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
-#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
+#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
@@ -42,6 +42,7 @@
 
 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
 
+#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
 
 #ifdef CONFIG_MX6

arch/arm/mach-imx/Makefile

@@ -5,12 +5,14 @@
 #
 # (C) Copyright 2011 Freescale Semiconductor, Inc.
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610))
 obj-y	= iomux-v3.o
 endif
 
-ifeq ($(SOC),$(filter $(SOC),mx8m))
+ifeq ($(SOC),$(filter $(SOC),imx8m))
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
 obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
 obj-$(CONFIG_FEC_MXC) += mac.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
@@ -22,7 +24,7 @@ obj-y	+= cpu.o speed.o
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m))
 obj-y	+= misc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
@@ -104,7 +106,11 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
 ifeq ($(CONFIG_ARCH_IMX8), y)
 CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
 IMAGE_TYPE := imx8image
-DEPFILE_EXISTS := $(shell if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
+DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
+else ifeq ($(CONFIG_ARCH_IMX8M), y)
+IMAGE_TYPE := imx8mimage
+IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh
+DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi)
 else
 IMAGE_TYPE := imximage
 DEPFILE_EXISTS := 0
@@ -129,6 +135,26 @@ ifeq ($(DEPFILE_EXISTS),0)
 endif
 endif
 
+ifdef CONFIG_ARM64
+ifeq ($(CONFIG_ARCH_IMX8M), y)
+SPL:
+
+MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \
+		   -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
+flash.bin: MKIMAGEOUTPUT = flash.log
+
+spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
+ifeq ($(DEPFILE_EXISTS),0)
+	$(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1
+endif
+
+flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE
+ifeq ($(DEPFILE_EXISTS),0)
+	$(call if_changed,mkimage)
+endif
+endif
+
+else
 MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
 		   -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
 SPL: MKIMAGEOUTPUT = SPL.log
@@ -160,6 +186,7 @@ cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \
 
 spl/u-boot-nand-spl.imx: SPL FORCE
 	$(call if_changed,u-boot-nand-spl_imx)
+endif
 
 targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
 
@@ -169,5 +196,5 @@ obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
 obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
-obj-$(CONFIG_MX8M) += mx8m/
+obj-$(CONFIG_IMX8M) += imx8m/
 obj-$(CONFIG_ARCH_IMX8) += imx8/

arch/arm/mach-imx/cpu.c

@@ -62,7 +62,7 @@ static char *get_reset_cause(void)
 		return "WDOG4";
 	case 0x00200:
 		return "TEMPSENSE";
-#elif defined(CONFIG_MX8M)
+#elif defined(CONFIG_IMX8M)
 	case 0x00100:
 		return "WDOG2";
 	case 0x00200:
@@ -142,8 +142,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
-	case MXC_CPU_MX8MQ:
-		return "8MQ";	/* Quad-core version of the mx8m */
+	case MXC_CPU_IMX8MQ:
+		return "8MQ";	/* Quad-core version of the imx8m */
 	case MXC_CPU_MX7S:
 		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
@@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
+#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 u32 get_ahb_clk(void)
 {
 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -300,7 +300,7 @@ void arch_preboot_os(void)
 #endif
 }
 
-#ifndef CONFIG_MX8M
+#ifndef CONFIG_IMX8M
 void set_chipselect_size(int const cs_size)
 {
 	unsigned int reg;
@@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size)
 }
 #endif
 
-#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
 /*
  * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  * defines a 2-bit SPEED_GRADING
@@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 }
 #endif
 
-#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
 enum boot_device get_boot_device(void)
 {
 	struct bootrom_sw_info **p =
@@ -438,7 +438,7 @@ enum boot_device get_boot_device(void)
 	case BOOT_TYPE_SPINOR:
 		boot_dev = SPI_NOR_BOOT;
 		break;
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 	case BOOT_TYPE_USB:
 		boot_dev = USB_BOOT;
 		break;

arch/arm/mach-imx/hab.c

@@ -6,6 +6,8 @@
 #include <common.h>
 #include <config.h>
 #include <fuse.h>
+#include <mapmem.h>
+#include <image.h>
 #include <asm/io.h>
 #include <asm/system.h>
 #include <asm/arch/clock.h>
@@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc,
 	return 0;
 }
 
+static ulong get_image_ivt_offset(ulong img_addr)
+{
+	const void *buf;
+
+	buf = map_sysmem(img_addr, 0);
+	switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+	case IMAGE_FORMAT_LEGACY:
+		return (image_get_image_size((image_header_t *)img_addr)
+			+ 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+#if IMAGE_ENABLE_FIT
+	case IMAGE_FORMAT_FIT:
+		return (fit_get_size(buf) + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+	default:
+		return 0;
+	}
+}
+
 static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
 				 char * const argv[])
 {
 	ulong	addr, length, ivt_offset;
 	int	rcode = 0;
 
-	if (argc < 4)
+	if (argc < 3)
 		return CMD_RET_USAGE;
 
 	addr = simple_strtoul(argv[1], NULL, 16);
 	length = simple_strtoul(argv[2], NULL, 16);
-	ivt_offset = simple_strtoul(argv[3], NULL, 16);
+	if (argc == 3)
+		ivt_offset = get_image_ivt_offset(addr);
+	else
+		ivt_offset = simple_strtoul(argv[3], NULL, 16);
 
 	rcode = imx_hab_authenticate_image(addr, length, ivt_offset);
 	if (rcode == 0)

arch/arm/mach-imx/imx8m/Kconfig

+if ARCH_IMX8M
+
+config IMX8M
+	bool
+	select ROM_UNIFIED_SECTIONS
+
+config SYS_SOC
+	default "imx8m"
+
+choice
+	prompt  "NXP i.MX8M board select"
+	optional
+
+config TARGET_IMX8MQ_EVK
+	bool "imx8mq_evk"
+	select IMX8M
+	select IMX8M_LPDDR4
+
+endchoice
+
+source "board/freescale/imx8mq_evk/Kconfig"
+
+endif

arch/arm/mach-imx/mx8m/clock.c → arch/arm/mach-imx/imx8m/clock.c

@@ -525,41 +525,127 @@ u32 imx_get_fecclk(void)
 	return get_root_clk(ENET_AXI_CLK_ROOT);
 }
 
-#ifdef CONFIG_SPL_BUILD
-void dram_pll_init(void)
+static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
+				CLK_ROOT_PRE_DIV2),
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
+				CLK_ROOT_PRE_DIV2),
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
+				CLK_ROOT_PRE_DIV2),
+};
+
+void dram_enable_bypass(ulong clk_val)
 {
-	struct src *src = (struct src *)SRC_BASE_ADDR;
-	void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
-	u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0;
-	u32 val;
-	int ret;
+	int i;
+	struct dram_bypass_clk_setting *config;
 
-	setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
-	setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
+	for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
+		if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
+		printf("No matched freq table %lu\n", clk_val);
+		return;
+	}
 
-	pwdn_mask = SSCG_PLL_PD_MASK;
-	pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
-	bypass1 = SSCG_PLL_BYPASS1_MASK;
-	bypass2 = SSCG_PLL_BYPASS2_MASK;
+	config = &imx8mq_dram_bypass_tbl[i];
 
-	/* Enable DDR1 and DDR2 domain */
-	writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
-	writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
+	clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
+			     CLK_ROOT_PRE_DIV(config->alt_pre_div));
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
+			     CLK_ROOT_PRE_DIV(config->apb_pre_div));
+	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1));
+}
+
+void dram_disable_bypass(void)
+{
+	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(0));
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(4) |
+			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
+}
+
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
+{
+	u32 val;
+	void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
+	void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
+
+	/* Bypass */
+	setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
+	setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
+
+	switch (pll_val) {
+	case MHZ(800):
+		val = readl(pll_cfg_reg2);
+		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+			 SSCG_PLL_REF_DIVR2_MASK);
+		val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
+		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
+		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+		val |= SSCG_PLL_REF_DIVR2_VAL(29);
+		writel(val, pll_cfg_reg2);
+		break;
+	case MHZ(600):
+		val = readl(pll_cfg_reg2);
+		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+			 SSCG_PLL_REF_DIVR2_MASK);
+		val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
+		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
+		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+		val |= SSCG_PLL_REF_DIVR2_VAL(29);
+		writel(val, pll_cfg_reg2);
+		break;
+	case MHZ(400):
+		val = readl(pll_cfg_reg2);
+		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+			 SSCG_PLL_REF_DIVR2_MASK);
+		val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
+		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
+		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+		val |= SSCG_PLL_REF_DIVR2_VAL(29);
+		writel(val, pll_cfg_reg2);
+		break;
+	case MHZ(167):
+		val = readl(pll_cfg_reg2);
+		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+			 SSCG_PLL_REF_DIVR2_MASK);
+		val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
+		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
+		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
+		val |= SSCG_PLL_REF_DIVR2_VAL(30);
+		writel(val, pll_cfg_reg2);
+		break;
+	default:
+		break;
+	}
 
 	/* Clear power down bit */
-	clrbits_le32(pll_control_reg, pwdn_mask);
+	clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
 	/* Eanble ARM_PLL/SYS_PLL  */
-	setbits_le32(pll_control_reg, pll_clke);
+	setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
 
 	/* Clear bypass */
-	clrbits_le32(pll_control_reg, bypass1);
+	clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
 	__udelay(100);
-	clrbits_le32(pll_control_reg, bypass2);
+	clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
 	/* Wait lock */
-	ret = readl_poll_timeout(pll_control_reg, val,
-				 val & SSCG_PLL_LOCK_MASK, 1);
-	if (ret)
-		printf("%s timeout\n", __func__);
+	while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
+		;
 }
 
 int frac_pll_init(u32 pll, enum frac_pll_out_val val)
@@ -730,7 +816,7 @@ int clock_init(void)
  * Dump some clockes.
  */
 #ifndef CONFIG_SPL_BUILD
-int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char * const argv[])
 {
 	u32 freq;
@@ -785,7 +871,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 }
 
 U_BOOT_CMD(
-	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks,
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
 	"display clocks",
 	""
 );

arch/arm/mach-imx/imx8m/imximage.cfg

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+FIT
+BOOT_FROM	sd
+SIGNED_HDMI	signed_hdmi_imx8m.bin
+LOADER		spl/u-boot-spl-ddr.bin	0x7E1000
+SECOND_LOADER	u-boot.itb		0x40200000 0x60000
+
+DDR_FW lpddr4_pmu_train_1d_imem.bin
+DDR_FW lpddr4_pmu_train_1d_dmem.bin
+DDR_FW lpddr4_pmu_train_2d_imem.bin
+DDR_FW lpddr4_pmu_train_2d_dmem.bin

arch/arm/mach-imx/mx8m/soc.c → arch/arm/mach-imx/imx8m/soc.c

@@ -77,6 +77,22 @@ static struct mm_region imx8m_mem_map[] = {
 		.size = 0x100000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* CAAM */
+		.virt = 0x100000UL,
+		.phys = 0x100000UL,
+		.size = 0x8000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* TCM */
+		.virt = 0x7C0000UL,
+		.phys = 0x7C0000UL,
+		.size = 0x80000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
 		/* OCRAM */
 		.virt = 0x900000UL,

arch/arm/mach-imx/imx_bootaux.c

@@ -17,15 +17,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 	if (!boot_private_data)
 		return -EINVAL;
 
-	stack = *(ulong *)boot_private_data;
-	pc = *(ulong *)(boot_private_data + 4);
+	stack = *(u32 *)boot_private_data;
+	pc = *(u32 *)(boot_private_data + 4);
 
 	/* Set the stack and pc to M4 bootROM */
 	writel(stack, M4_BOOTROM_BASE_ADDR);
 	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
 
 	/* Enable M4 */
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 	call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
 #else
 	clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
@@ -37,7 +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 
 int arch_auxiliary_core_check_up(u32 core_id)
 {
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 	return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
 #else
 	unsigned int val;

arch/arm/mach-imx/mkimage_fit_atf.sh

+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for i.MX8MQ boards with
+# ARM Trusted Firmware and multiple device trees (given on the command line)
+#
+# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+
+[ -z "$BL31" ] && BL31="bl31.bin"
+[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
+[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
+
+if [ ! -f $BL31 ]; then
+	echo "ERROR: BL31 file $BL31 NOT found" >&2
+	exit 0
+else
+	echo "$BL31 size: " >&2
+	ls -lct $BL31 | awk '{print $5}' >&2
+fi
+
+BL32="tee.bin"
+
+if [ ! -f $BL32 ]; then
+	BL32=/dev/null
+else
+	echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
+	echo "$BL32 size: " >&2
+	ls -lct $BL32 | awk '{print $5}' >&2
+fi
+
+BL33="u-boot-nodtb.bin"
+
+if [ ! -f $BL33 ]; then
+	echo "ERROR: $BL33 file NOT found" >&2
+	exit 0
+else
+	echo "u-boot-nodtb.bin size: " >&2
+	ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2
+fi
+
+for dtname in $*
+do
+	echo "$dtname size: " >&2
+	ls -lct $dtname | awk '{print $5}' >&2
+done
+
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+	description = "Configuration to load ATF before U-Boot";
+
+	images {
+		uboot@1 {
+			description = "U-Boot (64-bit)";
+			data = /incbin/("$BL33");
+			type = "standalone";
+			arch = "arm64";
+			compression = "none";
+			load = <0x40200000>;
+		};
+		atf@1 {
+			description = "ARM Trusted Firmware";
+			data = /incbin/("$BL31");
+			type = "firmware";
+			arch = "arm64";
+			compression = "none";
+			load = <$ATF_LOAD_ADDR>;
+			entry = <$ATF_LOAD_ADDR>;
+		};
+__HEADER_EOF
+
+if [ -f $BL32 ]; then
+cat << __HEADER_EOF
+		tee@1 {
+			description = "TEE firmware";
+			data = /incbin/("$BL32");
+			type = "firmware";
+			arch = "arm64";
+			compression = "none";
+			load = <$TEE_LOAD_ADDR>;
+			entry = <$TEE_LOAD_ADDR>;
+		};
+__HEADER_EOF
+fi
+
+cnt=1
+for dtname in $*
+do
+	cat << __FDT_IMAGE_EOF
+		fdt@$cnt {
+			description = "$(basename $dtname .dtb)";
+			data = /incbin/("$dtname");
+			type = "flat_dt";
+			compression = "none";
+		};
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+	};
+	configurations {
+		default = "config@1";
+
+__CONF_HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+if [ -f $BL32 ]; then
+cat << __CONF_SECTION_EOF
+		config@$cnt {
+			description = "$(basename $dtname .dtb)";
+			firmware = "uboot@1";
+			loadables = "atf@1", "tee@1";
+			fdt = "fdt@$cnt";
+		};
+__CONF_SECTION_EOF
+else
+cat << __CONF_SECTION1_EOF
+		config@$cnt {
+			description = "$(basename $dtname .dtb)";
+			firmware = "uboot@1";
+			loadables = "atf@1";
+			fdt = "fdt@$cnt";
+		};
+__CONF_SECTION1_EOF
+fi
+cnt=$((cnt+1))
+done
+
+cat << __ITS_EOF
+	};
+};
+__ITS_EOF

arch/arm/mach-imx/mx6/Kconfig

@@ -182,6 +182,7 @@ config TARGET_DISPLAY5
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 	select BOARD_LATE_INIT
+	select SUPPORT_SPL
 
 config TARGET_GE_BX50V3
 	bool "General Electric Bx50v3"

arch/arm/mach-imx/mx8m/Kconfig

-if ARCH_MX8M
-
-config MX8M
-	bool
-	select ROM_UNIFIED_SECTIONS
-
-config SYS_SOC
-	default "mx8m"
-
-endif

arch/arm/mach-imx/spl.c

@@ -96,8 +96,8 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NONE;
 }
 
-#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M)
-/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
 u32 spl_boot_device(void)
 {
 #if defined(CONFIG_MX7)
@@ -126,6 +126,7 @@ u32 spl_boot_device(void)
 	enum boot_device boot_device_spl = get_boot_device();
 
 	switch (boot_device_spl) {
+#if defined(CONFIG_MX7)
 	case SD1_BOOT:
 	case MMC1_BOOT:
 	case SD2_BOOT:
@@ -133,6 +134,14 @@ u32 spl_boot_device(void)
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8M)
+	case SD1_BOOT:
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC2;
+#endif
 	case NAND_BOOT:
 		return BOOT_DEVICE_NAND;
 	case SPI_NOR_BOOT:
@@ -143,7 +152,7 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_NONE;
 	}
 }
-#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
+#endif /* CONFIG_MX7 || CONFIG_IMX8M */
 
 #ifdef CONFIG_SPL_USB_GADGET_SUPPORT
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
@@ -220,14 +229,46 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 
 	debug("image entry point: 0x%lX\n", spl_image->entry_point);
 
-	/* HAB looks for the CSF at the end of the authenticated data therefore,
-	 * we need to subtract the size of the CSF from the actual filesize */
-	offset = spl_image->size - CONFIG_CSF_SIZE;
-	if (!imx_hab_authenticate_image(spl_image->load_addr,
-					offset + IVT_SIZE + CSF_PAD_SIZE,
-					offset)) {
+	if (spl_image->flags & SPL_FIT_FOUND) {
 		image_entry();
 	} else {
+		/*
+		 * HAB looks for the CSF at the end of the authenticated
+		 * data therefore, we need to subtract the size of the
+		 * CSF from the actual filesize
+		 */
+		offset = spl_image->size - CONFIG_CSF_SIZE;
+		if (!imx_hab_authenticate_image(spl_image->load_addr,
+						offset + IVT_SIZE +
+						CSF_PAD_SIZE, offset)) {
+			image_entry();
+		} else {
+			puts("spl: ERROR:  image authentication fail\n");
+			hang();
+		}
+	}
+}
+
+ulong board_spl_fit_size_align(ulong size)
+{
+	/*
+	 * HAB authenticate_image requests the IVT offset is
+	 * aligned to 0x1000
+	 */
+
+	size = ALIGN(size, 0x1000);
+	size += CONFIG_CSF_SIZE;
+
+	return size;
+}
+
+void board_spl_fit_post_load(ulong load_addr, size_t length)
+{
+	u32 offset = length - CONFIG_CSF_SIZE;
+
+	if (imx_hab_authenticate_image(load_addr,
+				       offset + IVT_SIZE + CSF_PAD_SIZE,
+				       offset)) {
 		puts("spl: ERROR:  image authentication unsuccessful\n");
 		hang();
 	}

board/embest/mx6boards/MAINTAINERS

@@ -5,3 +5,4 @@ F:	board/embest/mx6boards/
 F:	include/configs/embestmx6boards.h
 F:	configs/marsboard_defconfig
 F:	configs/riotboard_defconfig
+F:	configs/riotboard_spl_defconfig

board/embest/mx6boards/mx6boards.c

@@ -608,3 +608,51 @@ int checkboard(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+
+void board_init_f(ulong dummy)
+{
+	u32 cputype = cpu_type(get_cpu_rev());
+
+	switch (cputype) {
+	case MXC_CPU_MX6SOLO:
+		board_type = BOARD_IS_RIOTBOARD;
+		break;
+	case MXC_CPU_MX6D:
+		board_type = BOARD_IS_MARSBOARD;
+		break;
+	}
+	arch_cpu_init();
+
+	/* setup GP timer */
+	timer_init();
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	setup_iomux_uart();
+	preloader_console_init();
+#endif
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_MMC1;
+}
+
+/*
+ * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
+ * to pin 3 (ground).
+ */
+int spl_start_uboot(void)
+{
+	int gpio_key = IMX_GPIO_NR(4, 16);
+
+	gpio_direction_input(gpio_key);
+	if (gpio_get_value(gpio_key) == 0)
+		return 1;
+	else
+		return 0;
+}
+
+#endif

board/freescale/imx8mq_evk/Kconfig

+if TARGET_IMX8MQ_EVK
+
+config SYS_BOARD
+	default "imx8mq_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_evk"
+
+endif

board/freescale/imx8mq_evk/MAINTAINERS

+i.MX8MQ EVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8mq_evk/
+F:	include/configs/imx8mq_evk.h
+F:	configs/imx8mq_evk_defconfig

board/freescale/imx8mq_evk/Makefile

+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
+endif

board/freescale/imx8mq_evk/README

+U-Boot for the NXP i.MX8MQ EVK board
+
+Quick Start
+====================
+- Build the ARM Trusted firmware binary
+- Get ddr and hdmi fimware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+====================
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_4.14.62_1.0.0_beta
+$ make PLAT=imx8mq bl31
+
+Get the ddr and hdmi firmware
+====================
+Note: srctree is U-Boot source directory
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
+$ chmod +x firmware-imx-7.9.bin
+$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree)
+$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee)
+
+Build U-Boot
+====================
+$ export ARCH=arm64
+$ export CROSS_COMPILE=aarch64-poky-linux-
+$ make imx8mq_evk_defconfig
+$ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 33KB
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
+
+Boot
+====================
+Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.

board/freescale/imx8mq_evk/imx8mq_evk.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+	else
+		gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+					 ARRAY_SIZE(fec1_rst_pads));
+
+	gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
+	gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	setup_iomux_fec();
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "EVK");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+	return 0;
+}

board/freescale/imx8qxp_mek/imximage.cfg

@@ -7,7 +7,6 @@
  */
 
 #define __ASSEMBLY__
-#include <config.h>
 
 /* Boot from SD, sector size 0x400 */
 BOOT_FROM SD 0x400

board/ge/bx50v3/Kconfig

@@ -15,4 +15,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ge_bx50v3"
 
+source "board/ge/common/Kconfig"
+
 endif

board/ge/common/Kconfig

+config SYS_VPD_EEPROM_I2C_ADDR
+	hex "I2C address of the EEPROM device used for VPD"
+	help
+	  VPD = Vital Product Data
+
+config SYS_VPD_EEPROM_I2C_BUS
+	int "I2C bus of the EEPROM device used for VPD."
+
+config SYS_VPD_EEPROM_SIZE
+	int "Size in bytes of the EEPROM device used for VPD"
+
+config SYS_VPD_EEPROM_I2C_ADDR_LEN
+	int "Number of bytes to use for VPD EEPROM address"
+	default 1

board/ge/common/vpd_reader.h

@@ -5,12 +5,18 @@
 
 #include "common.h"
 
+struct vpd_cache;
+
 /*
- * Read VPD from given data, verify content, and call callback
- * for each vital product data block.
+ * Read VPD from given data, verify content, call callback for each vital
+ * product data block.
+ *
+ * cache: structure used by process block to store VPD information
+ * process_block: callback called for each VPD data block
  *
  * Returns Non-zero on error.  Negative numbers encode errno.
  */
-int vpd_reader(size_t size, u8 *data, void *userdata,
-	       int (*fn)(void *userdata, u8 id, u8 version, u8 type,
-			 size_t size, u8 const *data));
+int read_vpd(struct vpd_cache *cache,
+	     int (*process_block)(struct vpd_cache *,
+				  u8 id, u8 version, u8 type,
+				  size_t size, u8 const *data));

board/ge/mx53ppd/Kconfig

@@ -13,4 +13,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "mx53ppd"
 
+source "board/ge/common/Kconfig"
+
 endif

common/image.c

@@ -140,6 +140,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
 	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
 	{	IH_TYPE_IMX8IMAGE,  "imx8image",  "NXP i.MX8 Boot Image",},
+	{	IH_TYPE_IMX8MIMAGE, "imx8mimage", "NXP i.MX8M Boot Image",},
 	{	IH_TYPE_INVALID,    "invalid",	  "Invalid Image",	},
 	{	IH_TYPE_MULTI,	    "multi",	  "Multi-File Image",	},
 	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP SPL With GP CH",},

common/spl/Kconfig

@@ -286,6 +286,7 @@ config SPL_FIT_IMAGE_TINY
 	bool "Remove functionality from SPL FIT loading to reduce size"
 	depends on SPL_FIT
 	default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
+	default y if ARCH_IMX8M
 	help
 	  Enable this to reduce the size of the FIT image loading code
 	  in SPL, if space for the SPL binary is very tight.

configs/warp7_defconfig

@@ -8,6 +8,8 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set