SoC: qcom: add support for SDM845

Hi-end qualcomm chip, introduced in late 2017.
Mostly used in flagship phones and tablets of 2018.
Features:
- arm64 arch
- total of 8 Kryo 385 Gold / Silver cores
- Hexagon 685 DSP
- Adreno 630 GPU

Tested only as second-stage bootloader.
Signed-off-by: NDzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stephan Gerhold <stephan@gerhold.net>

arch/arm/dts/sdm845.dtsi

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM845 chip device tree source
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+
+/ {
+	soc: soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		gcc: clock-controller@100000 {
+			u-boot,dm-pre-reloc;
+			compatible = "qcom,gcc-sdm845";
+			reg = <0x100000 0x1f0000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		gpio_north: gpio_north@3900000 {
+			u-boot,dm-pre-reloc;
+			#gpio-cells = <2>;
+			compatible = "qcom,sdm845-pinctrl";
+			reg = <0x3900000 0x400000>;
+			gpio-count = <150>;
+			gpio-controller;
+			gpio-ranges = <&gpio_north 0 0 150>;
+			gpio-bank-name = "soc_north.";
+		};
+
+		tlmm_north: pinctrl_north@3900000 {
+			u-boot,dm-pre-reloc;
+			compatible = "qcom,tlmm-sdm845";
+			reg = <0x3900000 0x400000>;
+			gpio-count = <150>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm_north 0 0 150>;
+
+			/* DEBUG UART */
+			qup_uart9: qup-uart9-default {
+				pinmux {
+					pins = "GPIO_4", "GPIO_5";
+					function = "qup9";
+				};
+			};
+		};
+
+		debug_uart: serial@a84000 {
+			compatible = "qcom,msm-geni-uart";
+			reg = <0xa84000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc 0x58>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&qup_uart9>;
+			qcom,wrapper-core = <0x8a>;
+			status = "disabled";
+		};
+
+		spmi@c440000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0xc440000 0x1100>,
+			      <0xc600000 0x2000000>,
+			      <0xe600000 0x100000>;
+			reg-names = "cnfg", "core", "obsrvr";
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+
+			qcom,revid@100 {
+				compatible = "qcom,qpnp-revid";
+				reg = <0x100 0x100>;
+			};
+
+			pmic0: pm8998@0 {
+				compatible = "qcom,spmi-pmic";
+				reg = <0x0 0x1>;
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+
+				pm8998_pon: pm8998_pon@800 {
+					compatible = "qcom,pm8998-pwrkey";
+					reg = <0x800 0x100>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					gpio-bank-name = "pm8998_key.";
+				};
+
+				pm8998_gpios: pm8998_gpios@c000 {
+					compatible = "qcom,pm8998-gpio";
+					reg = <0xc000 0x1a00>;
+					gpio-controller;
+					gpio-count = <21>;
+					#gpio-cells = <2>;
+					gpio-bank-name = "pm8998.";
+				};
+			};
+
+			pmic1: pm8998@1 {
+				compatible = "qcom,spmi-pmic";
+				reg = <0x1 0x0>;
+				#address-cells = <0x2>;
+				#size-cells = <0x0>;
+			};
+		};
+	};
+};

arch/arm/mach-snapdragon/Kconfig

@@ -9,6 +9,10 @@ config SYS_MALLOC_F_LEN
 config SPL_SYS_MALLOC_F_LEN
 	default 0x2000
 
+config SDM845
+	bool "Qualcomm Snapdragon 845 SoC"
+	default n
+
 choice
 	prompt "Snapdragon board select"
 

arch/arm/mach-snapdragon/Makefile

@@ -2,6 +2,9 @@
 #
 # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 
+obj-$(CONFIG_SDM845) += clock-sdm845.o
+obj-$(CONFIG_SDM845) += sysmap-sdm845.o
+obj-$(CONFIG_SDM845) += init_sdm845.o
 obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
@@ -12,3 +15,4 @@ obj-y += dram.o
 obj-y += pinctrl-snapdragon.o
 obj-y += pinctrl-apq8016.o
 obj-y += pinctrl-apq8096.o
+obj-$(CONFIG_SDM845) += pinctrl-sdm845.o

arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm SDM845 sysmap
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ */
+#ifndef _MACH_SYSMAP_SDM845_H
+#define _MACH_SYSMAP_SDM845_H
+
+#define TLMM_BASE_ADDR			(0x1010000)
+
+/* Strength (sdc1) */
+#define SDC1_HDRV_PULL_CTL_REG		(TLMM_BASE_ADDR + 0x0012D000)
+
+/* Clocks: (from CLK_CTL_BASE)  */
+#define GPLL0_STATUS			(0x0000)
+#define APCS_GPLL_ENA_VOTE		(0x52000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE	(0x52004)
+
+#define SDCC2_BCR			(0x14000) /* block reset */
+#define SDCC2_APPS_CBCR			(0x14004) /* branch control */
+#define SDCC2_AHB_CBCR			(0x14008)
+#define SDCC2_CMD_RCGR			(0x1400c)
+#define SDCC2_CFG_RCGR			(0x14010)
+#define SDCC2_M				(0x14014)
+#define SDCC2_N				(0x14018)
+#define SDCC2_D				(0x1401C)
+
+#define RCG2_CFG_REG			0x4
+#define M_REG			0x8
+#define N_REG			0xc
+#define D_REG			0x10
+
+#define SE9_AHB_CBCR			(0x25004)
+#define SE9_UART_APPS_CBCR		(0x29004)
+#define SE9_UART_APPS_CMD_RCGR	(0x18148)
+#define SE9_UART_APPS_CFG_RCGR	(0x1814C)
+#define SE9_UART_APPS_M		(0x18150)
+#define SE9_UART_APPS_N		(0x18154)
+#define SE9_UART_APPS_D		(0x18158)
+
+#endif

arch/arm/mach-snapdragon/init_sdm845.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Common init part for boards based on SDM845
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ */
+
+#include <init.h>
+#include <env.h>
+#include <common.h>
+#include <asm/system.h>
+#include <asm/gpio.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+void reset_cpu(void)
+{
+	psci_system_reset();
+}
+
+__weak int board_init(void)
+{
+	return 0;
+}
+
+/* Check for vol- and power buttons */
+__weak int misc_init_r(void)
+{
+	struct udevice *pon;
+	struct gpio_desc resin;
+	int node, ret;
+
+	ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8998_pon@800", &pon);
+	if (ret < 0) {
+		printf("Failed to find PMIC pon node. Check device tree\n");
+		return 0;
+	}
+
+	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+				  "key_vol_down");
+	if (node < 0) {
+		printf("Failed to find key_vol_down node. Check device tree\n");
+		return 0;
+	}
+	if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+				       &resin, 0)) {
+		printf("Failed to request key_vol_down button.\n");
+		return 0;
+	}
+	if (dm_gpio_get_value(&resin)) {
+		env_set("key_vol_down", "1");
+		printf("Volume down button pressed\n");
+	} else {
+		env_set("key_vol_down", "0");
+	}
+
+	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+				  "key_power");
+	if (node < 0) {
+		printf("Failed to find key_power node. Check device tree\n");
+		return 0;
+	}
+	if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+				       &resin, 0)) {
+		printf("Failed to request key_power button.\n");
+		return 0;
+	}
+	if (dm_gpio_get_value(&resin)) {
+		env_set("key_power", "1");
+		printf("Power button pressed\n");
+	} else {
+		env_set("key_power", "0");
+	}
+
+	return 0;
+}

arch/arm/mach-snapdragon/sysmap-sdm845.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM845 memory map
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankousk@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region sdm845_mem_map[] = {
+	{
+		.virt = 0x0UL, /* Peripheral block */
+		.phys = 0x0UL, /* Peripheral block */
+		.size = 0x10000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL, /* DDR */
+		.phys = 0x80000000UL, /* DDR */
+		.size = 0x200000000UL, /* 8GiB - maximum allowed memory */
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = sdm845_mem_map;

include/configs/sdm845.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for boards, based on Qualcomm SDM845 chip
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ */
+
+#ifndef __CONFIGS_SDM845_H
+#define __CONFIGS_SDM845_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-sdm845.h>
+
+#define CONFIG_SYS_LOAD_ADDR	0x80000000
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY	19000000
+
+#define EXTRA_ENV_SETTINGS \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80000000\0"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + SZ_8M)
+#define CONFIG_SYS_BOOTM_LEN	SZ_64M
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	512
+#define CONFIG_SYS_MAXARGS	64
+
+#endif