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体验新版 GitCode,发现更多精彩内容 >>
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4a3c7eb9
编写于
8月 16, 2007
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
下载
差异文件
Merge with /home/wd/git/u-boot/custodian/u-boot-nand-flash
上级
2d78074d
a44e7a97
变更
31
隐藏空白更改
内联
并排
Showing
31 changed file
with
246 addition
and
474 deletion
+246
-474
board/esd/ash405/Makefile
board/esd/ash405/Makefile
+3
-1
board/esd/ash405/ash405.c
board/esd/ash405/ash405.c
+11
-33
board/esd/cms700/Makefile
board/esd/cms700/Makefile
+4
-1
board/esd/cms700/cms700.c
board/esd/cms700/cms700.c
+8
-31
board/esd/common/auto_update.c
board/esd/common/auto_update.c
+4
-0
board/esd/common/esd405ep_nand.c
board/esd/common/esd405ep_nand.c
+87
-0
board/esd/hh405/Makefile
board/esd/hh405/Makefile
+4
-1
board/esd/hh405/hh405.c
board/esd/hh405/hh405.c
+1
-21
board/esd/hub405/Makefile
board/esd/hub405/Makefile
+3
-1
board/esd/hub405/hub405.c
board/esd/hub405/hub405.c
+0
-34
board/esd/plu405/Makefile
board/esd/plu405/Makefile
+4
-1
board/esd/plu405/plu405.c
board/esd/plu405/plu405.c
+9
-47
board/esd/voh405/Makefile
board/esd/voh405/Makefile
+3
-1
board/esd/voh405/voh405.c
board/esd/voh405/voh405.c
+0
-20
board/esd/wuh405/Makefile
board/esd/wuh405/Makefile
+3
-1
board/esd/wuh405/wuh405.c
board/esd/wuh405/wuh405.c
+0
-36
common/cmd_nand.c
common/cmd_nand.c
+32
-5
drivers/nand/nand_ids.c
drivers/nand/nand_ids.c
+1
-0
include/configs/ASH405.h
include/configs/ASH405.h
+12
-31
include/configs/CMS700.h
include/configs/CMS700.h
+9
-30
include/configs/CPCI405.h
include/configs/CPCI405.h
+0
-2
include/configs/CPCI4052.h
include/configs/CPCI4052.h
+0
-2
include/configs/CPCI405AB.h
include/configs/CPCI405AB.h
+0
-3
include/configs/CPCI405DT.h
include/configs/CPCI405DT.h
+0
-2
include/configs/HH405.h
include/configs/HH405.h
+9
-30
include/configs/HUB405.h
include/configs/HUB405.h
+9
-30
include/configs/PLU405.h
include/configs/PLU405.h
+9
-48
include/configs/VOH405.h
include/configs/VOH405.h
+9
-30
include/configs/WUH405.h
include/configs/WUH405.h
+10
-32
include/linux/mtd/nand.h
include/linux/mtd/nand.h
+1
-0
include/nand.h
include/nand.h
+1
-0
未找到文件。
board/esd/ash405/Makefile
浏览文件 @
4a3c7eb9
...
...
@@ -28,7 +28,9 @@ endif
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
=
$(BOARD)
.o flash.o ../common/misc.o
COBJS
=
$(BOARD)
.o flash.o
\
../common/misc.o
\
../common/esd405ep_nand.o
\
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
...
...
board/esd/ash405/ash405.c
浏览文件 @
4a3c7eb9
...
...
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
...
...
@@ -33,6 +34,7 @@
#endif
extern
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
int
flag
,
int
argc
,
char
*
argv
[]);
extern
void
lxt971_no_sleep
(
void
);
/* fpga configuration data - gzip compressed and generated by bin2c */
const
unsigned
char
fpgadata
[]
=
...
...
@@ -164,17 +166,11 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
out
32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_DUART_RST
);
/* set reset to high */
out
_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
|
CFG_DUART_RST
);
udelay
(
10
);
/* wait 10us */
out
32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
CFG_DUART_RST
);
/* set reset to low */
out
_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
&
~
CFG_DUART_RST
);
udelay
(
1000
);
/* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
(
CFG_NAND_CLE
|
CFG_NAND_ALE
));
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_NAND_CE
);
/*
* Enable interrupts in exar duart mcr[3]
*/
...
...
@@ -218,35 +214,17 @@ long int initdram (int board_type)
mtdcr
(
memcfga
,
mem_mb0cf
);
val
=
mfdcr
(
memcfgd
);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return
(
4
*
1024
*
1024
<<
((
val
&
0x000e0000
)
>>
17
));
}
/* ------------------------------------------------------------------------- */
int
testdram
(
void
)
void
reset_phy
(
void
)
{
/* TODO: XXX XXX XXX */
printf
(
"test: 16 MB - ok
\n
"
);
return
(
0
);
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern
struct
nand_chip
nand_dev_desc
[
CFG_MAX_NAND_DEVICE
];
void
nand_init
(
void
)
{
nand_probe
(
CFG_NAND_BASE
);
if
(
nand_dev_desc
[
0
].
ChipID
!=
NAND_ChipID_UNKNOWN
)
{
print_size
(
nand_dev_desc
[
0
].
totlen
,
"
\n
"
);
}
}
#ifdef CONFIG_LXT971_NO_SLEEP
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep
();
#endif
}
board/esd/cms700/Makefile
浏览文件 @
4a3c7eb9
...
...
@@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o
\
../common/xilinx_jtag/ports.o
COBJS
=
$(BOARD)
.o flash.o ../common/misc.o
$(CPLD)
COBJS
=
$(BOARD)
.o flash.o
\
../common/misc.o
\
$(CPLD)
\
../common/esd405ep_nand.o
\
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
...
...
board/esd/cms700/cms700.c
浏览文件 @
4a3c7eb9
/*
* (C) Copyright 2005
* (C) Copyright 2005
-2007
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
...
...
@@ -68,9 +69,9 @@ int board_early_init_f (void)
/*
* Reset CPLD via GPIO12 (CS3) pin
*/
out
32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
CFG_PLD_RESET
);
out
_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
&
~
CFG_PLD_RESET
);
udelay
(
1000
);
/* wait 1ms */
out
32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_PLD_RESET
);
out
_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
|
CFG_PLD_RESET
);
udelay
(
1000
);
/* wait 1ms */
return
0
;
...
...
@@ -94,13 +95,7 @@ int misc_init_r (void)
/*
* Setup and enable EEPROM write protection
*/
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_EEPROM_WP
);
/*
* Set NAND-FLASH GPIO signals to default
*/
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
(
CFG_NAND_CLE
|
CFG_NAND_ALE
));
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_NAND_CE
);
out_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
|
CFG_EEPROM_WP
);
return
(
0
);
}
...
...
@@ -153,11 +148,6 @@ long int initdram (int board_type)
mtdcr
(
memcfga
,
mem_mb0cf
);
val
=
mfdcr
(
memcfgd
);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return
(
4
*
1024
*
1024
<<
((
val
&
0x000e0000
)
>>
17
));
}
...
...
@@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state)
switch
(
state
)
{
case
1
:
/* Enable write access, clear bit GPIO_SINT2. */
out
32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
CFG_EEPROM_WP
);
out
_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
&
~
CFG_EEPROM_WP
);
state
=
0
;
break
;
case
0
:
/* Disable write access, set bit GPIO_SINT2. */
out
32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_EEPROM_WP
);
out
_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
|
CFG_EEPROM_WP
);
state
=
0
;
break
;
default:
/* Read current status back. */
state
=
(
0
==
(
in
32
(
GPIO0_OR
)
&
CFG_EEPROM_WP
));
state
=
(
0
==
(
in
_be32
((
void
*
)
GPIO0_OR
)
&
CFG_EEPROM_WP
));
break
;
}
}
...
...
@@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern
struct
nand_chip
nand_dev_desc
[
CFG_MAX_NAND_DEVICE
];
void
nand_init
(
void
)
{
nand_probe
(
CFG_NAND_BASE
);
if
(
nand_dev_desc
[
0
].
ChipID
!=
NAND_ChipID_UNKNOWN
)
{
print_size
(
nand_dev_desc
[
0
].
totlen
,
"
\n
"
);
}
}
#endif
void
reset_phy
(
void
)
{
#ifdef CONFIG_LXT971_NO_SLEEP
...
...
board/esd/common/auto_update.c
浏览文件 @
4a3c7eb9
...
...
@@ -31,7 +31,9 @@
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
#if defined(CFG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
#endif
#include <fat.h>
#include <part.h>
...
...
@@ -294,6 +296,8 @@ int au_do_update(int i, long sz)
rc
=
nand_legacy_rw
(
nand_dev_desc
,
NANDRW_WRITE
|
NANDRW_JFFS2
,
start
,
nbytes
,
(
size_t
*
)
&
total
,
(
uchar
*
)
addr
);
debug
(
"nand_legacy_rw: ret=%x total=%d nbytes=%d
\n
"
,
rc
,
total
,
nbytes
);
#else
rc
=
-
1
;
#endif
}
if
(
rc
!=
0
)
{
...
...
board/esd/common/esd405ep_nand.c
0 → 100644
浏览文件 @
4a3c7eb9
/*
* (C) Copyright 2007
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#include <asm/io.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
static
void
esd405ep_nand_hwcontrol
(
struct
mtd_info
*
mtdinfo
,
int
cmd
)
{
switch
(
cmd
)
{
case
NAND_CTL_SETCLE
:
out_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
|
CFG_NAND_CLE
);
break
;
case
NAND_CTL_CLRCLE
:
out_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
&
~
CFG_NAND_CLE
);
break
;
case
NAND_CTL_SETALE
:
out_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
|
CFG_NAND_ALE
);
break
;
case
NAND_CTL_CLRALE
:
out_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
&
~
CFG_NAND_ALE
);
break
;
case
NAND_CTL_SETNCE
:
out_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
&
~
CFG_NAND_CE
);
break
;
case
NAND_CTL_CLRNCE
:
out_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
|
CFG_NAND_CE
);
break
;
}
}
/*
* read device ready pin
*/
static
int
esd405ep_nand_device_ready
(
struct
mtd_info
*
mtdinfo
)
{
if
(
in_be32
((
void
*
)
GPIO0_IR
)
&
CFG_NAND_RDY
)
return
1
;
return
0
;
}
int
board_nand_init
(
struct
nand_chip
*
nand
)
{
/*
* Set NAND-FLASH GPIO signals to defaults
*/
out_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
&
~
(
CFG_NAND_CLE
|
CFG_NAND_ALE
));
out_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
|
CFG_NAND_CE
);
/*
* Initialize nand_chip structure
*/
nand
->
hwcontrol
=
esd405ep_nand_hwcontrol
;
nand
->
dev_ready
=
esd405ep_nand_device_ready
;
nand
->
eccmode
=
NAND_ECC_SOFT
;
nand
->
chip_delay
=
NAND_BIG_DELAY_US
;
nand
->
options
=
NAND_SAMSUNG_LP_OPTIONS
;
return
0
;
}
#endif
board/esd/hh405/Makefile
浏览文件 @
4a3c7eb9
...
...
@@ -28,7 +28,10 @@ endif
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
=
$(BOARD)
.o flash.o ../common/misc.o ../common/auto_update.o
COBJS
=
$(BOARD)
.o flash.o
\
../common/misc.o
\
../common/esd405ep_nand.o
\
../common/auto_update.o
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
...
...
board/esd/hh405/hh405.c
浏览文件 @
4a3c7eb9
...
...
@@ -5,7 +5,7 @@
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* (C) Copyright 2006
-2007
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -476,12 +476,6 @@ int misc_init_r (void)
*/
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_EEPROM_WP
);
/*
* Set NAND-FLASH GPIO signals to default
*/
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
(
CFG_NAND_CLE
|
CFG_NAND_ALE
));
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_NAND_CE
);
/*
* Reset touch-screen controller
*/
...
...
@@ -690,20 +684,6 @@ void ide_set_reset(int on)
#endif
/* CONFIG_IDE_RESET */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern
struct
nand_chip
nand_dev_desc
[
CFG_MAX_NAND_DEVICE
];
void
nand_init
(
void
)
{
nand_probe
(
CFG_NAND_BASE
);
if
(
nand_dev_desc
[
0
].
ChipID
!=
NAND_ChipID_UNKNOWN
)
{
print_size
(
nand_dev_desc
[
0
].
totlen
,
"
\n
"
);
}
}
#endif
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
...
...
board/esd/hub405/Makefile
浏览文件 @
4a3c7eb9
...
...
@@ -28,7 +28,9 @@ endif
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
=
$(BOARD)
.o flash.o ../common/misc.o
COBJS
=
$(BOARD)
.o flash.o
\
../common/misc.o
\
../common/esd405ep_nand.o
\
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
...
...
board/esd/hub405/hub405.c
浏览文件 @
4a3c7eb9
...
...
@@ -152,12 +152,6 @@ int misc_init_r (void)
out32
(
GPIO0_OR
,
val
);
/*
* Set NAND-FLASH GPIO signals to default
*/
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
(
CFG_NAND_CLE
|
CFG_NAND_ALE
));
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_NAND_CE
);
/*
* check board type and setup AP power
*/
...
...
@@ -242,33 +236,5 @@ long int initdram (int board_type)
mtdcr
(
memcfga
,
mem_mb0cf
);
val
=
mfdcr
(
memcfgd
);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return
(
4
*
1024
*
1024
<<
((
val
&
0x000e0000
)
>>
17
));
}
int
testdram
(
void
)
{
/* TODO: XXX XXX XXX */
printf
(
"test: 16 MB - ok
\n
"
);
return
(
0
);
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern
struct
nand_chip
nand_dev_desc
[
CFG_MAX_NAND_DEVICE
];
void
nand_init
(
void
)
{
nand_probe
(
CFG_NAND_BASE
);
if
(
nand_dev_desc
[
0
].
ChipID
!=
NAND_ChipID_UNKNOWN
)
{
print_size
(
nand_dev_desc
[
0
].
totlen
,
"
\n
"
);
}
}
#endif
board/esd/plu405/Makefile
浏览文件 @
4a3c7eb9
...
...
@@ -28,7 +28,10 @@ endif
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
=
$(BOARD)
.o flash.o ../common/misc.o ../common/auto_update.o
COBJS
=
$(BOARD)
.o flash.o
\
../common/misc.o
\
../common/esd405ep_nand.o
\
../common/auto_update.o
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
...
...
board/esd/plu405/plu405.c
浏览文件 @
4a3c7eb9
...
...
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
...
...
@@ -31,6 +32,8 @@
#define FPGA_DEBUG
#endif
DECLARE_GLOBAL_DATA_PTR
;
extern
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
int
flag
,
int
argc
,
char
*
argv
[]);
extern
void
lxt971_no_sleep
(
void
);
...
...
@@ -114,6 +117,10 @@ int misc_init_r (void)
int
index
;
int
i
;
/* adjust flash start and offset */
gd
->
bd
->
bi_flashstart
=
0
-
gd
->
bd
->
bi_flashsize
;
gd
->
bd
->
bi_flashoffset
=
0
;
dst
=
malloc
(
CFG_FPGA_MAX_SIZE
);
if
(
gunzip
(
dst
,
CFG_FPGA_MAX_SIZE
,
(
uchar
*
)
fpgadata
,
&
len
)
!=
0
)
{
printf
(
"GUNZIP ERROR - must RESET board to recover
\n
"
);
...
...
@@ -177,17 +184,11 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
out
32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_DUART_RST
);
/* set reset to high */
out
_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
|
CFG_DUART_RST
);
udelay
(
10
);
/* wait 10us */
out
32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
CFG_DUART_RST
);
/* set reset to low */
out
_be32
((
void
*
)
GPIO0_OR
,
in_be32
((
void
*
)
GPIO0_OR
)
&
~
CFG_DUART_RST
);
udelay
(
1000
);
/* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
(
CFG_NAND_CLE
|
CFG_NAND_ALE
));
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_NAND_CE
);
/*
* Enable interrupts in exar duart mcr[3]
*/
...
...
@@ -226,24 +227,10 @@ long int initdram (int board_type)
mtdcr
(
memcfga
,
mem_mb0cf
);
val
=
mfdcr
(
memcfgd
);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return
(
4
*
1024
*
1024
<<
((
val
&
0x000e0000
)
>>
17
));
}
int
testdram
(
void
)
{
/* TODO: XXX XXX XXX */
printf
(
"test: 16 MB - ok
\n
"
);
return
(
0
);
}
#ifdef CONFIG_IDE_RESET
void
ide_set_reset
(
int
on
)
{
...
...
@@ -262,31 +249,6 @@ void ide_set_reset(int on)
#endif
/* CONFIG_IDE_RESET */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern
struct
nand_chip
nand_dev_desc
[
CFG_MAX_NAND_DEVICE
];
void
nand_init
(
void
)
{
nand_probe
(
CFG_NAND_BASE
);
if
(
nand_dev_desc
[
0
].
ChipID
!=
NAND_ChipID_UNKNOWN
)
{
print_size
(
nand_dev_desc
[
0
].
totlen
,
"
\n
"
);
}
}
#endif
#ifdef CONFIG_AUTO_UPDATE_SHOW
void
board_auto_update_show
(
int
au_active
)
{
if
(
au_active
)
{
printf
(
"
\n
Dies ist die board-funktion: Updating!!!
\n
"
);
}
else
{
printf
(
"
\n
Dies ist die board-funktion: Updating done!!!
\n
"
);
}
}
#endif
void
reset_phy
(
void
)
{
#ifdef CONFIG_LXT971_NO_SLEEP
...
...
board/esd/voh405/Makefile
浏览文件 @
4a3c7eb9
...
...
@@ -28,7 +28,9 @@ endif
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
=
$(BOARD)
.o flash.o ../common/misc.o
COBJS
=
$(BOARD)
.o flash.o
\
../common/misc.o
\
../common/esd405ep_nand.o
\
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
...
...
board/esd/voh405/voh405.c
浏览文件 @
4a3c7eb9
...
...
@@ -194,12 +194,6 @@ int misc_init_r (void)
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
CFG_DUART_RST
);
/* set reset to low */
udelay
(
1000
);
/* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
(
CFG_NAND_CLE
|
CFG_NAND_ALE
));
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_NAND_CE
);
/*
* Enable interrupts in exar duart mcr[3]
*/
...
...
@@ -340,17 +334,3 @@ void ide_set_reset(int on)
}
}
#endif
/* CONFIG_IDE_RESET */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern
struct
nand_chip
nand_dev_desc
[
CFG_MAX_NAND_DEVICE
];
void
nand_init
(
void
)
{
nand_probe
(
CFG_NAND_BASE
);
if
(
nand_dev_desc
[
0
].
ChipID
!=
NAND_ChipID_UNKNOWN
)
{
print_size
(
nand_dev_desc
[
0
].
totlen
,
"
\n
"
);
}
}
#endif
board/esd/wuh405/Makefile
浏览文件 @
4a3c7eb9
...
...
@@ -28,7 +28,9 @@ endif
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
=
$(BOARD)
.o flash.o ../common/misc.o
COBJS
=
$(BOARD)
.o flash.o
\
../common/misc.o
\
../common/esd405ep_nand.o
\
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
...
...
board/esd/wuh405/wuh405.c
浏览文件 @
4a3c7eb9
...
...
@@ -169,12 +169,6 @@ int misc_init_r (void)
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
CFG_DUART_RST
);
/* set reset to low */
udelay
(
1000
);
/* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
&
~
(
CFG_NAND_CLE
|
CFG_NAND_ALE
));
out32
(
GPIO0_OR
,
in32
(
GPIO0_OR
)
|
CFG_NAND_CE
);
/*
* Enable interrupts in exar duart mcr[3]
*/
...
...
@@ -218,35 +212,5 @@ long int initdram (int board_type)
mtdcr
(
memcfga
,
mem_mb0cf
);
val
=
mfdcr
(
memcfgd
);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return
(
4
*
1024
*
1024
<<
((
val
&
0x000e0000
)
>>
17
));
}
/* ------------------------------------------------------------------------- */
int
testdram
(
void
)
{
/* TODO: XXX XXX XXX */
printf
(
"test: 16 MB - ok
\n
"
);
return
(
0
);
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern
struct
nand_chip
nand_dev_desc
[
CFG_MAX_NAND_DEVICE
];
void
nand_init
(
void
)
{
nand_probe
(
CFG_NAND_BASE
);
if
(
nand_dev_desc
[
0
].
ChipID
!=
NAND_ChipID_UNKNOWN
)
{
print_size
(
nand_dev_desc
[
0
].
totlen
,
"
\n
"
);
}
}
#endif
common/cmd_nand.c
浏览文件 @
4a3c7eb9
...
...
@@ -468,14 +468,31 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
ulong
offset
,
ulong
addr
,
char
*
cmd
)
{
int
r
;
char
*
ep
;
char
*
ep
,
*
s
;
ulong
cnt
;
image_header_t
*
hdr
;
int
jffs2
=
0
;
s
=
strchr
(
cmd
,
'.'
);
if
(
s
!=
NULL
&&
(
!
strcmp
(
s
,
".jffs2"
)
||
!
strcmp
(
s
,
".e"
)
||
!
strcmp
(
s
,
".i"
)))
jffs2
=
1
;
printf
(
"
\n
Loading from %s, offset 0x%lx
\n
"
,
nand
->
name
,
offset
);
cnt
=
nand
->
oobblock
;
r
=
nand_read
(
nand
,
offset
,
&
cnt
,
(
u_char
*
)
addr
);
if
(
jffs2
)
{
nand_read_options_t
opts
;
memset
(
&
opts
,
0
,
sizeof
(
opts
));
opts
.
buffer
=
(
u_char
*
)
addr
;
opts
.
length
=
cnt
;
opts
.
offset
=
offset
;
opts
.
quiet
=
1
;
r
=
nand_read_opts
(
nand
,
&
opts
);
}
else
{
r
=
nand_read
(
nand
,
offset
,
&
cnt
,
(
u_char
*
)
addr
);
}
if
(
r
)
{
puts
(
"** Read error
\n
"
);
show_boot_progress
(
-
56
);
...
...
@@ -495,8 +512,18 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
print_image_hdr
(
hdr
);
cnt
=
(
ntohl
(
hdr
->
ih_size
)
+
sizeof
(
image_header_t
));
if
(
jffs2
)
{
nand_read_options_t
opts
;
memset
(
&
opts
,
0
,
sizeof
(
opts
));
opts
.
buffer
=
(
u_char
*
)
addr
;
opts
.
length
=
cnt
;
opts
.
offset
=
offset
;
opts
.
quiet
=
1
;
r
=
nand_read_opts
(
nand
,
&
opts
);
}
else
{
r
=
nand_read
(
nand
,
offset
,
&
cnt
,
(
u_char
*
)
addr
);
}
r
=
nand_read
(
nand
,
offset
,
&
cnt
,
(
u_char
*
)
addr
);
if
(
r
)
{
puts
(
"** Read error
\n
"
);
show_boot_progress
(
-
58
);
...
...
@@ -545,7 +572,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
if
(
argc
>
3
)
goto
usage
;
if
(
argc
==
3
)
addr
=
simple_strtoul
(
argv
[
2
],
NULL
,
16
);
addr
=
simple_strtoul
(
argv
[
1
],
NULL
,
16
);
else
addr
=
CFG_LOAD_ADDR
;
return
nand_load_image
(
cmdtp
,
&
nand_info
[
dev
->
id
->
num
],
...
...
@@ -604,7 +631,7 @@ usage:
U_BOOT_CMD
(
nboot
,
4
,
1
,
do_nandboot
,
"nboot - boot from NAND device
\n
"
,
"[partition] | [[[loadAddr] dev] offset]
\n
"
);
"[
.jffs2] [
partition] | [[[loadAddr] dev] offset]
\n
"
);
#endif
...
...
drivers/nand/nand_ids.c
浏览文件 @
4a3c7eb9
...
...
@@ -123,6 +123,7 @@ struct nand_manufacturers nand_manuf_ids[] = {
{
NAND_MFR_NATIONAL
,
"National"
},
{
NAND_MFR_RENESAS
,
"Renesas"
},
{
NAND_MFR_STMICRO
,
"ST Micro"
},
{
NAND_MFR_MICRON
,
"Micron"
},
{
0x0
,
"Unknown"
}
};
#endif
include/configs/ASH405.h
浏览文件 @
4a3c7eb9
...
...
@@ -53,9 +53,13 @@
#define CONFIG_LOADS_ECHO 1
/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1
/* allow baudrate change */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_MII 1
/* MII PHY management */
#define CONFIG_PHY_ADDR 0
/* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1
/* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1
/* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
/* 66 MHz OPB clock*/
...
...
@@ -144,39 +148,16 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
/* verify all writes!!! */
#define CFG_NAND_SKIP_BAD_DOT_I 1
/* ".i" read skips bad blocks */
/*-----------------------------------------------------------------------
...
...
include/configs/CMS700.h
浏览文件 @
4a3c7eb9
...
...
@@ -90,8 +90,6 @@
#define CONFIG_CMD_EEPROM
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG
/* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1
/* init onboard SDRAM bank 0 */
...
...
@@ -157,34 +155,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1
/* ".i" read skips bad blocks */
...
...
include/configs/CPCI405.h
浏览文件 @
4a3c7eb9
...
...
@@ -92,8 +92,6 @@
#define CONFIG_SUPPORT_VFAT
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG
/* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1
/* init onboard SDRAM bank 0 */
...
...
include/configs/CPCI4052.h
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4a3c7eb9
...
...
@@ -114,8 +114,6 @@
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#endif
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG
/* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1
/* init onboard SDRAM bank 0 */
...
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include/configs/CPCI405AB.h
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4a3c7eb9
...
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@@ -100,9 +100,6 @@
#define CONFIG_SUPPORT_VFAT
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG
/* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1
/* init onboard SDRAM bank 0 */
...
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include/configs/CPCI405DT.h
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...
...
@@ -111,8 +111,6 @@
#undef CONFIG_AUTO_UPDATE
/* autoupdate via compactflash */
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG
/* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1
/* init onboard SDRAM bank 0 */
...
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include/configs/HH405.h
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4a3c7eb9
...
...
@@ -141,8 +141,6 @@
#define CONFIG_AUTO_UPDATE 1
/* autoupdate via compactflash */
#undef CONFIG_AUTO_UPDATE_SHOW
/* use board show routine */
#define CFG_NAND_LEGACY
#undef CONFIG_BZIP2
/* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG
/* watchdog disabled */
...
...
@@ -209,34 +207,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1
/* ".i" read skips bad blocks */
...
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include/configs/HUB405.h
浏览文件 @
4a3c7eb9
...
...
@@ -147,36 +147,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1
/* ".i" read skips bad blocks */
...
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include/configs/PLU405.h
浏览文件 @
4a3c7eb9
...
...
@@ -96,7 +96,6 @@
#define CONFIG_SUPPORT_VFAT
#define CONFIG_AUTO_UPDATE 1
/* autoupdate via compactflash */
#define CONFIG_AUTO_UPDATE_SHOW 1
/* use board show routine */
#undef CONFIG_WATCHDOG
/* watchdog disabled */
...
...
@@ -168,36 +167,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1
/* ".i" read skips bad blocks */
...
...
@@ -276,11 +254,6 @@
#define CFG_FLASH_EMPTY_INFO
/* print 'E' for empty sector on flinfo */
#if 0 /* test-only */
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
#endif
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
...
...
@@ -306,9 +279,6 @@
#define CFG_ENV_SIZE 0x700
/* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
#define CFG_NVRAM_BASE_ADDR 0xF0000500
/* NVRAM base address */
#define CFG_NVRAM_SIZE 242
/* NVRAM size */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
...
...
@@ -317,7 +287,7 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50
/* EEPROM CAT24WC08 */
#if 1
/* test-only */
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1
/* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
...
...
@@ -325,15 +295,6 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 4
/* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#else
/* CAT24WC32/64... */
#define CFG_I2C_EEPROM_ADDR_LEN 2
/* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CFG_EEPROM_PAGE_WRITE_BITS 5
/* The Catalyst CAT24WC32 has */
/* 32 byte page write mode using*/
/* last 5 bits of the address */
#endif
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
...
...
include/configs/VOH405.h
浏览文件 @
4a3c7eb9
...
...
@@ -153,36 +153,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1
/* ".i" read skips bad blocks */
...
...
include/configs/WUH405.h
浏览文件 @
4a3c7eb9
...
...
@@ -145,38 +145,16 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
/* verify all writes!!! */
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1)
/* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4)
/* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2)
/* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3)
/* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1
/* ".i" read skips bad blocks */
/*-----------------------------------------------------------------------
...
...
include/linux/mtd/nand.h
浏览文件 @
4a3c7eb9
...
...
@@ -348,6 +348,7 @@ struct nand_chip {
#define NAND_MFR_NATIONAL 0x8f
#define NAND_MFR_RENESAS 0x07
#define NAND_MFR_STMICRO 0x20
#define NAND_MFR_MICRON 0x2c
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
...
...
include/nand.h
浏览文件 @
4a3c7eb9
...
...
@@ -32,6 +32,7 @@ typedef struct mtd_info nand_info_t;
extern
int
nand_curr_device
;
extern
nand_info_t
nand_info
[];
extern
void
nand_init
(
void
);
static
inline
int
nand_read
(
nand_info_t
*
info
,
ulong
ofs
,
ulong
*
len
,
u_char
*
buf
)
{
...
...
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