armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot

Signed-off-by: NYuan Yao <yao.yuan@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

@@ -129,6 +129,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
 #define DCFG_RCWSR13			0x130
 #define DCFG_RCWSR13_DSPI		(0 << 8)
+#define DCFG_RCWSR15			0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI	0x3
 
 #define DCFG_DCSR_BASE		0X700100000ULL
 #define DCFG_DCSR_PORCR1		0x000

board/freescale/ls2080aqds/ls2080aqds.c

@@ -208,6 +208,15 @@ int board_init(void)
 	else
 		config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+		QIXIS_WRITE(brdcfg[9],
+			    (QIXIS_READ(brdcfg[9]) & 0xf8) |
+			     FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
 	gd->env_addr = (ulong)&default_environment[0];
 #endif

include/configs/ls2080aqds.h

@@ -303,6 +303,12 @@ unsigned long get_board_ddr_clk(void);
 #define FSL_QSPI_FLASH_SIZE		(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM		4
 #endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI		0x1
 
 #endif