ColdFire:Update the timer_init since it was unified.

Signed-off-by: NJason Jin <Jason.jin@freescale.com>

arch/m68k/cpu/mcf547x_8x/slicetimer.c

@@ -72,7 +72,7 @@ void dtimer_interrupt(void *not_used)
 	}
 }
 
-void timer_init(void)
+int timer_init(void)
 {
 	volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
 
@@ -93,6 +93,7 @@ void timer_init(void)
 	/* set a period of 1us, set timer mode to restart and
 	   enable timer and interrupt */
 	timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN;
+	return 0;
 }
 
 ulong get_timer(ulong base)

arch/m68k/lib/board.c

@@ -78,8 +78,6 @@ static char *failed = "*** failed ***\n";
 extern ulong __init_end;
 extern ulong __bss_end__;
 
-extern	void timer_init(void);
-
 #if defined(CONFIG_WATCHDOG)
 # define INIT_FUNC_WATCHDOG_INIT	watchdog_init,
 # define WATCHDOG_DISABLE		watchdog_disable

arch/m68k/lib/time.c

@@ -91,7 +91,7 @@ void dtimer_interrupt(void *not_used)
 	}
 }
 
-void timer_init(void)
+int timer_init(void)
 {
 	volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
 
@@ -114,6 +114,8 @@ void timer_init(void)
 	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
 	timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
 	    DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
+
+	return 0;
 }
 
 ulong get_timer(ulong base)
@@ -162,6 +164,8 @@ void timer_init(void)
 	timerp->pcsr = PIT_PCSR_OVW;
 	timerp->pmr = lastinc = 0;
 	timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
+
+	return 0;
 }
 
 ulong get_timer(ulong base)