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体验新版 GitCode,发现更多精彩内容 >>
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43c377fc
编写于
7月 20, 2002
作者:
W
wdenk
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
Initial revision
上级
befe61a1
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
352 addition
and
0 deletion
+352
-0
board/ep7312/memsetup.S
board/ep7312/memsetup.S
+97
-0
board/impa7/memsetup.S
board/impa7/memsetup.S
+87
-0
board/smdk2410/memsetup.S
board/smdk2410/memsetup.S
+168
-0
未找到文件。
board/ep7312/memsetup.S
0 → 100644
浏览文件 @
43c377fc
/*
*
Memory
Setup
stuff
-
taken
from
???
*
*
See
file
CREDITS
for
list
of
people
who
contributed
to
this
*
project
.
*
*
This
program
is
free
software
; you can redistribute it and/or
*
modify
it
under
the
terms
of
the
GNU
General
Public
License
as
*
published
by
the
Free
Software
Foundation
; either version 2 of
*
the
License
,
or
(
at
your
option
)
any
later
version
.
*
*
This
program
is
distributed
in
the
hope
that
it
will
be
useful
,
*
but
WITHOUT
ANY
WARRANTY
; without even the implied warranty of
*
MERCHANTABILITY
or
FITNESS
FOR
A
PARTICULAR
PURPOSE
.
See
the
*
GNU
General
Public
License
for
more
details
.
*
*
You
should
have
received
a
copy
of
the
GNU
General
Public
License
*
along
with
this
program
; if not, write to the Free Software
*
Foundation
,
Inc
.
,
59
Temple
Place
,
Suite
330
,
Boston
,
*
MA
02111
-
1307
USA
*/
#include <config.h>
#include <version.h>
/*
some
parameters
for
the
board
*/
SYSCON1
:
.
long
0x80000100
SYSCON2
:
.
long
0x80001100
SYSCON3
:
.
long
0x80002200
MEMCFG1
:
.
long
0x80000180
MEMCFG2
:
.
long
0x800001C0
SDCONF
:
.
long
0x80002300
SDRFPR
:
.
long
0x80002340
syscon1_val
:
.
long
0x00040100
syscon2_val
:
.
long
0x00000102
syscon3_val
:
.
long
0x0000020E
memcfg1_val
:
.
long
0x1f101710
memcfg2_mask
:
.
long
0x0000ffff
@
only
set
lower
16
bits
memcfg2_val
:
.
long
0x00001f13
@
upper
16
bits
are
reserved
for
CS7
+
CS6
sdrfpr_val
:
.
long
0x00000240
sdconf_val
:
.
long
0x00000522
/*
setting
up
the
memory
*/
.
globl
memsetup
memsetup
:
/
*
*
SYSCON1
-
3
*/
ldr
r0
,
SYSCON1
ldr
r1
,
syscon1_val
str
r1
,
[
r0
]
ldr
r0
,
SYSCON2
ldr
r1
,
syscon2_val
str
r1
,
[
r0
]
ldr
r0
,
SYSCON3
ldr
r1
,
syscon3_val
str
r1
,
[
r0
]
/
*
*
MEMCFG1
*/
ldr
r0
,
MEMCFG1
ldr
r1
,
memcfg1_val
str
r1
,
[
r0
]
/
*
*
MEMCFG2
*/
ldr
r0
,
MEMCFG2
ldr
r2
,
[
r0
]
ldr
r1
,
memcfg2_mask
bic
r2
,
r2
,
r1
ldr
r1
,
memcfg2_val
orr
r2
,
r2
,
r1
str
r2
,
[
r0
]
/
*
*
SDRFPR
,
SDCONF
*/
ldr
r0
,
SDCONF
ldr
r1
,
sdconf_val
str
r1
,
[
r0
]
ldr
r0
,
SDRFPR
ldr
r1
,
sdrfpr_val
str
r1
,
[
r0
]
/
*
everything
is
fine
now
*/
mov
pc
,
lr
board/impa7/memsetup.S
0 → 100644
浏览文件 @
43c377fc
/*
*
Memory
Setup
stuff
-
taken
from
???
*
*
See
file
CREDITS
for
list
of
people
who
contributed
to
this
*
project
.
*
*
This
program
is
free
software
; you can redistribute it and/or
*
modify
it
under
the
terms
of
the
GNU
General
Public
License
as
*
published
by
the
Free
Software
Foundation
; either version 2 of
*
the
License
,
or
(
at
your
option
)
any
later
version
.
*
*
This
program
is
distributed
in
the
hope
that
it
will
be
useful
,
*
but
WITHOUT
ANY
WARRANTY
; without even the implied warranty of
*
MERCHANTABILITY
or
FITNESS
FOR
A
PARTICULAR
PURPOSE
.
See
the
*
GNU
General
Public
License
for
more
details
.
*
*
You
should
have
received
a
copy
of
the
GNU
General
Public
License
*
along
with
this
program
; if not, write to the Free Software
*
Foundation
,
Inc
.
,
59
Temple
Place
,
Suite
330
,
Boston
,
*
MA
02111
-
1307
USA
*/
#include <config.h>
#include <version.h>
/*
some
parameters
for
the
board
*/
SYSCON2
:
.
long
0x80001100
MEMCFG1
:
.
long
0x80000180
MEMCFG2
:
.
long
0x800001C0
DRFPR
:
.
long
0x80000200
syscon2_mask
:
.
long
0x00000004
memcfg1_val
:
.
long
0x160c1414
memcfg2_mask
:
.
long
0x0000ffff
@
only
set
lower
16
bits
memcfg2_val
:
.
long
0x00000000
@
upper
16
bits
are
reserved
for
CS7
+
CS6
drfpr_val
:
.
long
0x00000081
/*
setting
up
the
memory
*/
.
globl
memsetup
memsetup
:
/
*
*
DRFPR
*
64
kHz
DRAM
refresh
*/
ldr
r0
,
DRFPR
ldr
r1
,
drfpr_val
str
r1
,
[
r0
]
/
*
*
SYSCON2
:
clear
bit
2
,
DRAM
is
32
bits
wide
*/
ldr
r0
,
SYSCON2
ldr
r2
,
[
r0
]
ldr
r1
,
syscon2_mask
bic
r2
,
r2
,
r1
str
r2
,
[
r0
]
/
*
*
MEMCFG1
*
Setting
up
Keyboard
at
CS3
,
8
Bit
,
3
Waitstates
*
Setting
up
CS8900
(
Ethernet
)
at
CS2
,
32
Bit
,
5
Waitstates
*
Setting
up
flash
at
CS0
and
CS1
,
32
Bit
,
3
Waitstates
*/
ldr
r0
,
MEMCFG1
ldr
r1
,
memcfg1_val
str
r1
,
[
r0
]
/
*
*
MEMCFG2
*
Setting
up
?
with
0
*
*/
ldr
r0
,
MEMCFG2
ldr
r2
,
[
r0
]
ldr
r1
,
memcfg2_mask
bic
r2
,
r2
,
r1
ldr
r1
,
memcfg2_val
orr
r2
,
r2
,
r1
str
r2
,
[
r0
]
/
*
everything
is
fine
now
*/
mov
pc
,
lr
board/smdk2410/memsetup.S
0 → 100644
浏览文件 @
43c377fc
/*
*
Memory
Setup
stuff
-
taken
from
blob
memsetup
.
S
*
*
Copyright
(
C
)
1999
2000
2001
Erik
Mouw
(
J
.
A
.
K
.
Mouw
@
its
.
tudelft
.
nl
)
and
*
Jan
-
Derk
Bakker
(
J
.
D
.
Bakker
@
its
.
tudelft
.
nl
)
*
*
Modified
for
the
Samsung
SMDK2410
by
*
(
C
)
Copyright
2002
*
David
Mueller
,
ELSOFT
AG
,
<
d
.
mueller
@
elsoft
.
ch
>
*
*
See
file
CREDITS
for
list
of
people
who
contributed
to
this
*
project
.
*
*
This
program
is
free
software
; you can redistribute it and/or
*
modify
it
under
the
terms
of
the
GNU
General
Public
License
as
*
published
by
the
Free
Software
Foundation
; either version 2 of
*
the
License
,
or
(
at
your
option
)
any
later
version
.
*
*
This
program
is
distributed
in
the
hope
that
it
will
be
useful
,
*
but
WITHOUT
ANY
WARRANTY
; without even the implied warranty of
*
MERCHANTABILITY
or
FITNESS
FOR
A
PARTICULAR
PURPOSE
.
See
the
*
GNU
General
Public
License
for
more
details
.
*
*
You
should
have
received
a
copy
of
the
GNU
General
Public
License
*
along
with
this
program
; if not, write to the Free Software
*
Foundation
,
Inc
.
,
59
Temple
Place
,
Suite
330
,
Boston
,
*
MA
02111
-
1307
USA
*/
#include <config.h>
#include <version.h>
/*
some
parameters
for
the
board
*/
/*
*
*
Taken
from
linux
/
arch
/
arm
/
boot
/
compressed
/
head
-
s3c2410
.
S
*
*
Copyright
(
C
)
2002
Samsung
Electronics
SW
.
LEE
<
hitchcar
@
sec
.
samsung
.
com
>
*
*/
#define BWSCON 0x48000000
/*
BWSCON
*/
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)
#define B1_BWSCON (DW32)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW16 + WAIT + UBLB)
#define B4_BWSCON (DW16)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)
/*
BANK0CON
*/
#define B0_Tacs 0x0 /* 0clk */
#define B0_Tcos 0x0 /* 0clk */
#define B0_Tacc 0x7 /* 14clk */
#define B0_Tcoh 0x0 /* 0clk */
#define B0_Tah 0x0 /* 0clk */
#define B0_Tacp 0x0
#define B0_PMC 0x0 /* normal */
/*
BANK1CON
*/
#define B1_Tacs 0x0 /* 0clk */
#define B1_Tcos 0x0 /* 0clk */
#define B1_Tacc 0x7 /* 14clk */
#define B1_Tcoh 0x0 /* 0clk */
#define B1_Tah 0x0 /* 0clk */
#define B1_Tacp 0x0
#define B1_PMC 0x0
#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
#define B2_Tacp 0x0
#define B2_PMC 0x0
#define B3_Tacs 0x0 /* 0clk */
#define B3_Tcos 0x3 /* 4clk */
#define B3_Tacc 0x7 /* 14clk */
#define B3_Tcoh 0x1 /* 1clk */
#define B3_Tah 0x0 /* 0clk */
#define B3_Tacp 0x3 /* 6clk */
#define B3_PMC 0x0 /* normal */
#define B4_Tacs 0x0 /* 0clk */
#define B4_Tcos 0x0 /* 0clk */
#define B4_Tacc 0x7 /* 14clk */
#define B4_Tcoh 0x0 /* 0clk */
#define B4_Tah 0x0 /* 0clk */
#define B4_Tacp 0x0
#define B4_PMC 0x0 /* normal */
#define B5_Tacs 0x0 /* 0clk */
#define B5_Tcos 0x0 /* 0clk */
#define B5_Tacc 0x7 /* 14clk */
#define B5_Tcoh 0x0 /* 0clk */
#define B5_Tah 0x0 /* 0clk */
#define B5_Tacp 0x0
#define B5_PMC 0x0 /* normal */
#define B6_MT 0x3 /* SDRAM */
#define B6_Trcd 0x1
#define B6_SCAN 0x1 /* 9bit */
#define B7_MT 0x3 /* SDRAM */
#define B7_Trcd 0x1 /* 3clk */
#define B7_SCAN 0x1 /* 9bit */
/*
REFRESH
parameter
*/
#define REFEN 0x1 /* Refresh enable */
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp 0x0 /* 2clk */
#define Trc 0x3 /* 7clk */
#define Tchr 0x2 /* 3clk */
#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
/**************************************/
_TEXT_BASE
:
.
word
TEXT_BASE
.
globl
memsetup
memsetup
:
/
*
memory
control
configuration
*/
/
*
make
r0
relative
the
current
location
so
that
it
*/
/
*
reads
SMRDATA
out
of
FLASH
rather
than
memory
!
*/
ldr
r0
,
=
SMRDATA
ldr
r1
,
_TEXT_BASE
sub
r0
,
r0
,
r1
ldr
r1
,
=
BWSCON
/*
Bus
Width
Status
Controller
*/
add
r2
,
r0
,
#
13
*
4
0
:
ldr
r3
,
[
r0
],
#
4
str
r3
,
[
r1
],
#
4
cmp
r2
,
r0
bne
0
b
/
*
everything
is
fine
now
*/
mov
pc
,
lr
.
ltorg
/*
the
literal
pools
origin
*/
SMRDATA
:
.
word
(
0
+(
B1_BWSCON
<<
4
)+(
B2_BWSCON
<<
8
)+(
B3_BWSCON
<<
12
)+(
B4_BWSCON
<<
16
)+(
B5_BWSCON
<<
20
)+(
B6_BWSCON
<<
24
)+(
B7_BWSCON
<<
28
))
.
word
((
B0_Tacs
<<
13
)+(
B0_Tcos
<<
11
)+(
B0_Tacc
<<
8
)+(
B0_Tcoh
<<
6
)+(
B0_Tah
<<
4
)+(
B0_Tacp
<<
2
)+(
B0_PMC
))
.
word
((
B1_Tacs
<<
13
)+(
B1_Tcos
<<
11
)+(
B1_Tacc
<<
8
)+(
B1_Tcoh
<<
6
)+(
B1_Tah
<<
4
)+(
B1_Tacp
<<
2
)+(
B1_PMC
))
.
word
((
B2_Tacs
<<
13
)+(
B2_Tcos
<<
11
)+(
B2_Tacc
<<
8
)+(
B2_Tcoh
<<
6
)+(
B2_Tah
<<
4
)+(
B2_Tacp
<<
2
)+(
B2_PMC
))
.
word
((
B3_Tacs
<<
13
)+(
B3_Tcos
<<
11
)+(
B3_Tacc
<<
8
)+(
B3_Tcoh
<<
6
)+(
B3_Tah
<<
4
)+(
B3_Tacp
<<
2
)+(
B3_PMC
))
.
word
((
B4_Tacs
<<
13
)+(
B4_Tcos
<<
11
)+(
B4_Tacc
<<
8
)+(
B4_Tcoh
<<
6
)+(
B4_Tah
<<
4
)+(
B4_Tacp
<<
2
)+(
B4_PMC
))
.
word
((
B5_Tacs
<<
13
)+(
B5_Tcos
<<
11
)+(
B5_Tacc
<<
8
)+(
B5_Tcoh
<<
6
)+(
B5_Tah
<<
4
)+(
B5_Tacp
<<
2
)+(
B5_PMC
))
.
word
((
B6_MT
<<
15
)+(
B6_Trcd
<<
2
)+(
B6_SCAN
))
.
word
((
B7_MT
<<
15
)+(
B7_Trcd
<<
2
)+(
B7_SCAN
))
.
word
((
REFEN
<<
23
)+(
TREFMD
<<
22
)+(
Trp
<<
20
)+(
Trc
<<
18
)+(
Tchr
<<
16
)+
REFCNT
)
.
word
0x32
.
word
0x30
.
word
0x30
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