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43638c67
编写于
3月 06, 2006
作者:
M
Markus Klotzbcher
提交者:
Markus Klotzbcher
3月 06, 2006
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
Cleanup of NAND support of delta board using the Monahans Data Flash
Controller.
上级
f9e02918
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
125 addition
and
212 deletion
+125
-212
board/delta/nand.c
board/delta/nand.c
+78
-202
cpu/pxa/start.S
cpu/pxa/start.S
+9
-1
drivers/nand/nand_base.c
drivers/nand/nand_base.c
+1
-7
include/asm-arm/arch-pxa/pxa-regs.h
include/asm-arm/arch-pxa/pxa-regs.h
+17
-0
include/configs/delta.h
include/configs/delta.h
+20
-2
未找到文件。
board/delta/nand.c
浏览文件 @
43638c67
...
...
@@ -28,17 +28,6 @@
#include <nand.h>
#include <asm/arch/pxa-regs.h>
/* mk@tbd move this to pxa-regs */
#define OSCR_CLK_FREQ 3.250
/* MHz */
/* usefull */
#define CFG_DFC_DEBUG1
/* noisy */
#undef CFG_DFC_DEBUG2
/* wild west */
#undef CFG_DFC_DEBUG3
#ifdef CFG_DFC_DEBUG1
# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
#else
...
...
@@ -57,6 +46,9 @@
# define DFC_DEBUG3(fmt, args...)
#endif
#define MIN(x, y) ((x < y) ? x : y)
/* These really don't belong here, as they are specific to the NAND Model */
static
uint8_t
scan_ff_pattern
[]
=
{
0xff
,
0xff
};
static
struct
nand_bbt_descr
delta_bbt_descr
=
{
...
...
@@ -77,13 +69,14 @@ static struct nand_oobinfo delta_oob = {
/*
* not required for Monahans DFC
*/
static
void
d
elta
_hwcontrol
(
struct
mtd_info
*
mtdinfo
,
int
cmd
)
static
void
d
fc
_hwcontrol
(
struct
mtd_info
*
mtdinfo
,
int
cmd
)
{
return
;
}
#if 0
/* read device ready pin */
static
int
d
elta
_device_ready
(
struct
mtd_info
*
mtdinfo
)
static int d
fc
_device_ready(struct mtd_info *mtdinfo)
{
if(NDSR & NDSR_RDY)
return 1;
...
...
@@ -91,18 +84,19 @@ static int delta_device_ready(struct mtd_info *mtdinfo)
return 0;
return 0;
}
#endif
/*
* Write buf to the DFC Controller Data Buffer
*/
static
void
d
elta
_write_buf
(
struct
mtd_info
*
mtd
,
const
u_char
*
buf
,
int
len
)
static
void
d
fc
_write_buf
(
struct
mtd_info
*
mtd
,
const
u_char
*
buf
,
int
len
)
{
unsigned
long
bytes_multi
=
len
&
0xfffffffc
;
unsigned
long
rest
=
len
&
0x3
;
unsigned
long
*
long_buf
;
int
i
;
DFC_DEBUG2
(
"d
elta
_write_buf: writing %d bytes starting with 0x%x.
\n
"
,
len
,
*
((
unsigned
long
*
)
buf
));
DFC_DEBUG2
(
"d
fc
_write_buf: writing %d bytes starting with 0x%x.
\n
"
,
len
,
*
((
unsigned
long
*
)
buf
));
if
(
bytes_multi
)
{
for
(
i
=
0
;
i
<
bytes_multi
;
i
+=
4
)
{
long_buf
=
(
unsigned
long
*
)
&
buf
[
i
];
...
...
@@ -110,7 +104,7 @@ static void delta_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
}
}
if
(
rest
)
{
printf
(
"d
elta
_write_buf: ERROR, writing non 4-byte aligned data.
\n
"
);
printf
(
"d
fc
_write_buf: ERROR, writing non 4-byte aligned data.
\n
"
);
}
return
;
}
...
...
@@ -126,23 +120,23 @@ static void delta_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
*
* Solution: Don't use these with Mona's DFC and complain loudly.
*/
static
void
d
elta
_write_word
(
struct
mtd_info
*
mtd
,
u16
word
)
static
void
d
fc
_write_word
(
struct
mtd_info
*
mtd
,
u16
word
)
{
printf
(
"d
elta
_write_word: WARNING, this function does not work with the Monahans DFC!
\n
"
);
printf
(
"d
fc
_write_word: WARNING, this function does not work with the Monahans DFC!
\n
"
);
}
static
void
d
elta
_write_byte
(
struct
mtd_info
*
mtd
,
u_char
byte
)
static
void
d
fc
_write_byte
(
struct
mtd_info
*
mtd
,
u_char
byte
)
{
printf
(
"d
elta
_write_byte: WARNING, this function does not work with the Monahans DFC!
\n
"
);
printf
(
"d
fc
_write_byte: WARNING, this function does not work with the Monahans DFC!
\n
"
);
}
/* The original:
* static void d
elta
_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
* static void d
fc
_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
*
* Shouldn't this be "u_char * const buf" ?
*/
static
void
d
elta
_read_buf
(
struct
mtd_info
*
mtd
,
u_char
*
const
buf
,
int
len
)
static
void
d
fc
_read_buf
(
struct
mtd_info
*
mtd
,
u_char
*
const
buf
,
int
len
)
{
int
i
,
j
;
int
i
=
0
,
j
;
/* we have to be carefull not to overflow the buffer if len is
* not a multiple of 4 */
...
...
@@ -150,7 +144,7 @@ static void delta_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
unsigned
long
rest
=
len
&
0x3
;
unsigned
long
*
long_buf
;
DFC_DEBUG3
(
"d
elta
_read_buf: reading %d bytes.
\n
"
,
len
);
DFC_DEBUG3
(
"d
fc
_read_buf: reading %d bytes.
\n
"
,
len
);
/* if there are any, first copy multiple of 4 bytes */
if
(
bytes_multi
)
{
for
(
i
=
0
;
i
<
bytes_multi
;
i
+=
4
)
{
...
...
@@ -172,23 +166,31 @@ static void delta_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
/*
* read a word. Not implemented as not used in NAND code.
*/
static
u16
d
elta
_read_word
(
struct
mtd_info
*
mtd
)
static
u16
d
fc
_read_word
(
struct
mtd_info
*
mtd
)
{
printf
(
"delta_write_byte: UNIMPLEMENTED.
\n
"
);
printf
(
"dfc_write_byte: UNIMPLEMENTED.
\n
"
);
return
0
;
}
/* global var, too bad: mk@tbd: move to ->priv pointer */
static
unsigned
long
read_buf
=
0
;
static
int
bytes_read
=
-
1
;
static
unsigned
long
last_cmd
=
0
;
/* read a byte from NDDB Because we can only read 4 bytes from NDDB at
/*
* read a byte from NDDB Because we can only read 4 bytes from NDDB at
* a time, we buffer the remaining bytes. The buffer is reset when a
* new command is sent to the chip.
*
* WARNING:
* This function is currently only used to read status and id
* bytes. For these commands always 8 bytes need to be read from
* NDDB. So we read and discard these bytes right now. In case this
* function is used for anything else in the future, we must check
* what was the last command issued and read the appropriate amount of
* bytes respectively.
*/
static
u_char
d
elta
_read_byte
(
struct
mtd_info
*
mtd
)
static
u_char
d
fc
_read_byte
(
struct
mtd_info
*
mtd
)
{
/* struct nand_chip *this = mtd->priv; */
unsigned
char
byte
;
unsigned
long
dummy
;
...
...
@@ -201,7 +203,7 @@ static u_char delta_read_byte(struct mtd_info *mtd)
if
(
bytes_read
>=
4
)
bytes_read
=
-
1
;
DFC_DEBUG2
(
"d
elta
_read_byte: byte %u: 0x%x of (0x%x).
\n
"
,
bytes_read
-
1
,
byte
,
read_buf
);
DFC_DEBUG2
(
"d
fc
_read_byte: byte %u: 0x%x of (0x%x).
\n
"
,
bytes_read
-
1
,
byte
,
read_buf
);
return
byte
;
}
...
...
@@ -227,14 +229,14 @@ static void wait_us(unsigned long us)
}
}
static
void
d
elta
_clear_nddb
()
static
void
d
fc
_clear_nddb
()
{
NDCR
&=
~
NDCR_ND_RUN
;
wait_us
(
CFG_NAND_OTHER_TO
);
}
/* wait_event with timeout */
static
unsigned
long
d
elta_wait_event2
(
unsigned
long
event
)
static
unsigned
long
d
fc_wait_event
(
unsigned
long
event
)
{
unsigned
long
ndsr
,
timeout
,
start
=
OSCR
;
...
...
@@ -252,7 +254,7 @@ static unsigned long delta_wait_event2(unsigned long event)
break
;
}
if
(
get_delta
(
start
)
>
timeout
)
{
DFC_DEBUG1
(
"d
elta
_wait_event: TIMEOUT waiting for event: 0x%x.
\n
"
,
event
);
DFC_DEBUG1
(
"d
fc
_wait_event: TIMEOUT waiting for event: 0x%x.
\n
"
,
event
);
return
0xff000000
;
}
...
...
@@ -260,25 +262,8 @@ static unsigned long delta_wait_event2(unsigned long event)
return
ndsr
;
}
#if DEADCODE
/* poll the NAND Controller Status Register for event */
static
void
delta_wait_event
(
unsigned
long
event
)
{
if
(
!
event
)
return
;
while
(
1
)
{
if
(
NDSR
&
event
)
{
NDSR
|=
event
;
break
;
}
}
}
#endif
/* we don't always wan't to do this */
static
void
d
elta
_new_cmd
()
static
void
d
fc
_new_cmd
()
{
int
retry
=
0
;
unsigned
long
status
;
...
...
@@ -291,29 +276,20 @@ static void delta_new_cmd()
if
(
!
(
NDCR
&
NDCR_ND_RUN
))
NDCR
|=
NDCR_ND_RUN
;
status
=
d
elta_wait_event2
(
NDSR_WRCMDREQ
);
status
=
d
fc_wait_event
(
NDSR_WRCMDREQ
);
if
(
status
&
NDSR_WRCMDREQ
)
return
;
DFC_DEBUG2
(
"delta_new_cmd: FAILED to get WRITECMDREQ, retry: %d.
\n
"
,
retry
);
delta_clear_nddb
();
}
DFC_DEBUG1
(
"delta_new_cmd: giving up after %d retries.
\n
"
,
retry
);
#if DEADCODE
while
(
1
)
{
if
(
NDSR
&
NDSR_WRCMDREQ
)
{
NDSR
|=
NDSR_WRCMDREQ
;
/* Ack */
break
;
}
DFC_DEBUG2
(
"dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.
\n
"
,
retry
);
dfc_clear_nddb
();
}
#endif
DFC_DEBUG1
(
"dfc_new_cmd: giving up after %d retries.
\n
"
,
retry
);
}
/* this function is called after Programm and Erase Operations to
* check for success or failure */
static
int
d
elta
_wait
(
struct
mtd_info
*
mtd
,
struct
nand_chip
*
this
,
int
state
)
static
int
d
fc
_wait
(
struct
mtd_info
*
mtd
,
struct
nand_chip
*
this
,
int
state
)
{
unsigned
long
ndsr
=
0
,
event
=
0
;
...
...
@@ -328,7 +304,7 @@ static int delta_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
event
=
NDSR_CS0_CMDD
|
NDSR_CS0_BBD
;
}
ndsr
=
d
elta_wait_event2
(
event
);
ndsr
=
d
fc_wait_event
(
event
);
if
((
ndsr
&
NDSR_CS0_BBD
)
||
(
ndsr
&
0xff000000
))
return
(
0x1
);
/* Status Read error */
...
...
@@ -336,26 +312,20 @@ static int delta_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
}
/* cmdfunc send commands to the DFC */
static
void
d
elta
_cmdfunc
(
struct
mtd_info
*
mtd
,
unsigned
command
,
int
column
,
int
page_addr
)
static
void
d
fc
_cmdfunc
(
struct
mtd_info
*
mtd
,
unsigned
command
,
int
column
,
int
page_addr
)
{
/* register struct nand_chip *this = mtd->priv; */
unsigned
long
ndcb0
=
0
,
ndcb1
=
0
,
ndcb2
=
0
,
event
=
0
;
unsigned
long
what_the_hack
;
/* clear the ugly byte read buffer */
bytes_read
=
-
1
;
read_buf
=
0
;
last_cmd
=
0
;
/* if command is a double byte cmd, we set bit double cmd bit 19 */
/* command2 = (command>>8) & 0xFF; */
/* ndcb0 = command | ((command2 ? 1 : 0) << 19); *\/ */
switch
(
command
)
{
case
NAND_CMD_READ0
:
DFC_DEBUG3
(
"d
elta
_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.
\n
"
,
page_addr
,
(
column
>>
1
));
d
elta
_new_cmd
();
DFC_DEBUG3
(
"d
fc
_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.
\n
"
,
page_addr
,
(
column
>>
1
));
d
fc
_new_cmd
();
ndcb0
=
(
NAND_CMD_READ0
|
(
4
<<
16
));
column
>>=
1
;
/* adjust for 16 bit bus */
ndcb1
=
(((
column
>>
1
)
&
0xff
)
|
...
...
@@ -365,35 +335,34 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
event
=
NDSR_RDDREQ
;
goto
write_cmd
;
case
NAND_CMD_READ1
:
DFC_DEBUG2
(
"d
elta
_cmdfunc: NAND_CMD_READ1 unimplemented!
\n
"
);
DFC_DEBUG2
(
"d
fc
_cmdfunc: NAND_CMD_READ1 unimplemented!
\n
"
);
goto
end
;
case
NAND_CMD_READOOB
:
DFC_DEBUG1
(
"d
elta
_cmdfunc: NAND_CMD_READOOB unimplemented!
\n
"
);
DFC_DEBUG1
(
"d
fc
_cmdfunc: NAND_CMD_READOOB unimplemented!
\n
"
);
goto
end
;
case
NAND_CMD_READID
:
last_cmd
=
NAND_CMD_READID
;
delta_new_cmd
();
DFC_DEBUG2
(
"delta_cmdfunc: NAND_CMD_READID.
\n
"
);
dfc_new_cmd
();
DFC_DEBUG2
(
"dfc_cmdfunc: NAND_CMD_READID.
\n
"
);
ndcb0
=
(
NAND_CMD_READID
|
(
3
<<
21
)
|
(
1
<<
16
));
/* addr cycles*/
event
=
NDSR_RDDREQ
;
goto
write_cmd
;
case
NAND_CMD_PAGEPROG
:
/* sent as a multicommand in NAND_CMD_SEQIN */
DFC_DEBUG2
(
"d
elta
_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.
\n
"
);
DFC_DEBUG2
(
"d
fc
_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.
\n
"
);
goto
end
;
case
NAND_CMD_ERASE1
:
DFC_DEBUG2
(
"d
elta
_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.
\n
"
,
page_addr
,
(
column
>>
1
));
d
elta
_new_cmd
();
DFC_DEBUG2
(
"d
fc
_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.
\n
"
,
page_addr
,
(
column
>>
1
));
d
fc
_new_cmd
();
ndcb0
=
(
0xd060
|
(
1
<<
25
)
|
(
2
<<
21
)
|
(
1
<<
19
)
|
(
3
<<
16
));
ndcb1
=
(
page_addr
&
0x00ffffff
);
goto
write_cmd
;
case
NAND_CMD_ERASE2
:
DFC_DEBUG2
(
"d
elta
_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.
\n
"
);
DFC_DEBUG2
(
"d
fc
_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.
\n
"
);
goto
end
;
case
NAND_CMD_SEQIN
:
/* send PAGE_PROG command(0x1080) */
d
elta
_new_cmd
();
DFC_DEBUG2
(
"d
elta
_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.
\n
"
,
page_addr
,
(
column
>>
1
));
d
fc
_new_cmd
();
DFC_DEBUG2
(
"d
fc
_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.
\n
"
,
page_addr
,
(
column
>>
1
));
ndcb0
=
(
0x1080
|
(
1
<<
25
)
|
(
1
<<
21
)
|
(
1
<<
19
)
|
(
4
<<
16
));
column
>>=
1
;
/* adjust for 16 bit bus */
ndcb1
=
(((
column
>>
1
)
&
0xff
)
|
...
...
@@ -402,72 +371,19 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
((
page_addr
<<
8
)
&
0xff000000
));
/* make this 0x01000000 ? */
event
=
NDSR_WRDREQ
;
goto
write_cmd
;
/* case NAND_CMD_SEQIN_pointer_operation: */
/* /\* This is confusing because the command names are */
/* * different compared to the ones in the K9K12Q0C */
/* * datasheet. Infact this has nothing to do with */
/* * reading, as the but with page programming */
/* * (writing). */
/* * Here we send the multibyte commands */
/* * cmd1=0x00, cmd2=0x80 (for programming main area) or */
/* * cmd1=0x50, cmd2=0x80 (for spare area) */
/* * */
/* * When all data is written to the buffer, the page */
/* * program command (0x10) is sent to actually write */
/* * the data. */
/* *\/ */
/* printf("delta_cmdfunc: NAND_CMD_SEQIN pointer op called.\n"); */
/* ndcb0 = (NAND_CMD_SEQIN<<8) | (1<<21) | (1<<19) | (4<<16); */
/* if(column >= mtd->oobblock) { */
/* /\* OOB area *\/ */
/* column -= mtd->oobblock; */
/* ndcb0 |= NAND_CMD_READOOB; */
/* } else if (column < 256) { */
/* /\* First 256 bytes --> READ0 *\/ */
/* ndcb0 |= NAND_CMD_READ0; */
/* } else { */
/* /\* Only for 8 bit devices - not delta!!! *\/ */
/* column -= 256; */
/* ndcb0 |= NAND_CMD_READ1; */
/* } */
/* event = NDSR_WRDREQ; */
/* break; */
case
NAND_CMD_STATUS
:
DFC_DEBUG2
(
"delta_cmdfunc: NAND_CMD_STATUS.
\n
"
);
/* oh, this is not nice. for some reason the real
* status byte is in the second read from the data
* buffer. The hack is to read the first byte right
* here, so the next read access by the nand code
* yields the right one.
*/
delta_new_cmd
();
DFC_DEBUG2
(
"dfc_cmdfunc: NAND_CMD_STATUS.
\n
"
);
dfc_new_cmd
();
ndcb0
=
NAND_CMD_STATUS
|
(
4
<<
21
);
event
=
NDSR_RDDREQ
;
#undef READ_STATUS_BUG
#ifdef READ_STATUS_BUG
NDCB0
=
ndcb0
;
NDCB0
=
ndcb1
;
NDCB0
=
ndcb2
;
delta_wait_event2
(
event
);
what_the_hack
=
NDDB
;
if
(
what_the_hack
!=
0xffffffff
)
{
DFC_DEBUG2
(
"what the hack.
\n
"
);
read_buf
=
what_the_hack
;
bytes_read
=
0
;
}
goto
end
;
#endif
goto
write_cmd
;
case
NAND_CMD_RESET
:
DFC_DEBUG2
(
"d
elta
_cmdfunc: NAND_CMD_RESET.
\n
"
);
DFC_DEBUG2
(
"d
fc
_cmdfunc: NAND_CMD_RESET.
\n
"
);
ndcb0
=
NAND_CMD_RESET
|
(
5
<<
21
);
event
=
NDSR_CS0_CMDD
;
goto
write_cmd
;
default:
printk
(
"d
elta
_cmdfunc: error, unsupported command.
\n
"
);
printk
(
"d
fc
_cmdfunc: error, unsupported command.
\n
"
);
goto
end
;
}
...
...
@@ -476,13 +392,13 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
NDCB0
=
ndcb1
;
NDCB0
=
ndcb2
;
wait_event:
d
elta_wait_event2
(
event
);
/* wait_event: */
d
fc_wait_event
(
event
);
end:
return
;
}
static
void
d
elta_d
fc_gpio_init
()
static
void
dfc_gpio_init
()
{
DFC_DEBUG2
(
"Setting up DFC GPIO's.
\n
"
);
...
...
@@ -542,51 +458,11 @@ void board_nand_init(struct nand_chip *nand)
unsigned
long
tCH
,
tCS
,
tWH
,
tWP
,
tRH
,
tRP
,
tRP_high
,
tR
,
tWHR
,
tAR
;
/* set up GPIO Control Registers */
d
elta_d
fc_gpio_init
();
dfc_gpio_init
();
/* turn on the NAND Controller Clock (104 MHz @ D0) */
CKENA
|=
(
CKENA_4_NAND
|
CKENA_9_SMC
);
/* wait ? */
/* printf("stupid loop start...\n"); */
/* wait(200); */
/* printf("stupid loop end.\n"); */
/* NAND Timing Parameters (in ns) */
#define NAND_TIMING_tCH 10
#define NAND_TIMING_tCS 0
#define NAND_TIMING_tWH 20
#define NAND_TIMING_tWP 40
#define NAND_TIMING_tRH 20
#define NAND_TIMING_tRP 40
/* #define NAND_TIMING_tRH 25 */
/* #define NAND_TIMING_tRP 50 */
#define NAND_TIMING_tR 11123
/* #define NAND_TIMING_tWHR 110 */
#define NAND_TIMING_tWHR 100
#define NAND_TIMING_tAR 10
/* Maximum values for NAND Interface Timing Registers in DFC clock
* periods */
#define DFC_MAX_tCH 7
#define DFC_MAX_tCS 7
#define DFC_MAX_tWH 7
#define DFC_MAX_tWP 7
#define DFC_MAX_tRH 7
#define DFC_MAX_tRP 15
#define DFC_MAX_tR 65535
#define DFC_MAX_tWHR 15
#define DFC_MAX_tAR 15
#define DFC_CLOCK 104
/* DFC Clock is 104 MHz */
#define DFC_CLK_PER_US DFC_CLOCK/1000
/* clock period in ns */
#define MIN(x, y) ((x < y) ? x : y)
#undef CFG_TIMING_TIGHT
#ifndef CFG_TIMING_TIGHT
tCH
=
MIN
(((
unsigned
long
)
(
NAND_TIMING_tCH
*
DFC_CLK_PER_US
)
+
1
),
...
...
@@ -692,25 +568,25 @@ void board_nand_init(struct nand_chip *nand)
/* wait(10); */
nand
->
hwcontrol
=
d
elta
_hwcontrol
;
/* nand->dev_ready = d
elta
_device_ready; */
nand
->
hwcontrol
=
d
fc
_hwcontrol
;
/* nand->dev_ready = d
fc
_device_ready; */
nand
->
eccmode
=
NAND_ECC_SOFT
;
nand
->
chip_delay
=
NAND_DELAY_US
;
nand
->
options
=
NAND_BUSWIDTH_16
;
nand
->
waitfunc
=
d
elta
_wait
;
nand
->
read_byte
=
d
elta
_read_byte
;
nand
->
write_byte
=
d
elta
_write_byte
;
nand
->
read_word
=
d
elta
_read_word
;
nand
->
write_word
=
d
elta
_write_word
;
nand
->
read_buf
=
d
elta
_read_buf
;
nand
->
write_buf
=
d
elta
_write_buf
;
nand
->
cmdfunc
=
d
elta
_cmdfunc
;
nand
->
waitfunc
=
d
fc
_wait
;
nand
->
read_byte
=
d
fc
_read_byte
;
nand
->
write_byte
=
d
fc
_write_byte
;
nand
->
read_word
=
d
fc
_read_word
;
nand
->
write_word
=
d
fc
_write_word
;
nand
->
read_buf
=
d
fc
_read_buf
;
nand
->
write_buf
=
d
fc
_write_buf
;
nand
->
cmdfunc
=
d
fc
_cmdfunc
;
nand
->
autooob
=
&
delta_oob
;
nand
->
badblock_pattern
=
&
delta_bbt_descr
;
}
#else
#error "U-Boot legacy NAND support not available for
delta board
."
#error "U-Boot legacy NAND support not available for
Monahans DFC
."
#endif
#endif
cpu/pxa/start.S
浏览文件 @
43638c67
...
...
@@ -165,7 +165,15 @@ _start_armboot: .word start_armboot
/*
-
setup
memory
timing
*/
/*
*/
/****************************************************************************/
/*
mk
@
tbd
:
Fix
this
!
*/
#ifdef CONFIG_CPU_MONAHANS
#undef ICMR
#undef OSMR3
#undef OSCR
#undef OWER
#undef OIER
#endif
/*
Interrupt
-
Controller
base
address
*/
IC_BASE
:
.
word
0x40d00000
#define ICMR 0x04
...
...
drivers/nand/nand_base.c
浏览文件 @
43638c67
...
...
@@ -489,7 +489,6 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
return
nand_write_oob
(
mtd
,
ofs
,
2
,
&
retlen
,
buf
);
}
#if READ_STATUS_BUG
/**
* nand_check_wp - [GENERIC] check if the chip is write protected
* @mtd: MTD device structure
...
...
@@ -504,12 +503,7 @@ static int nand_check_wp (struct mtd_info *mtd)
this
->
cmdfunc
(
mtd
,
NAND_CMD_STATUS
,
-
1
,
-
1
);
return
(
this
->
read_byte
(
mtd
)
&
0x80
)
?
0
:
1
;
}
#else
static
int
nand_check_wp
(
struct
mtd_info
*
mtd
)
{
return
0
;
}
#endif
/**
* nand_block_checkbad - [GENERIC] Check if a block is marked bad
* @mtd: MTD device structure
...
...
include/asm-arm/arch-pxa/pxa-regs.h
浏览文件 @
43638c67
...
...
@@ -880,6 +880,8 @@ typedef void (*ExcpHndlr) (void) ;
#define OMCR9 __REG(0x40A000D4)
/* OS Match Control Register 9 */
#define OMCR10 __REG(0x40A000D8)
/* OS Match Control Register 10 */
#define OMCR11 __REG(0x40A000DC)
/* OS Match Control Register 11 */
#define OSCR_CLK_FREQ 3.250
/* MHz */
#endif
/* CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4)
/* Match status channel 4 */
...
...
@@ -2132,6 +2134,21 @@ typedef void (*ExcpHndlr) (void) ;
#define MCIO(s) MCIO0
#define MECR_CIT (1 << 1)
/* Card Is There: 0 -> no card, 1 -> card inserted */
/* Maximum values for NAND Interface Timing Registers in DFC clock
* periods */
#define DFC_MAX_tCH 7
#define DFC_MAX_tCS 7
#define DFC_MAX_tWH 7
#define DFC_MAX_tWP 7
#define DFC_MAX_tRH 7
#define DFC_MAX_tRP 15
#define DFC_MAX_tR 65535
#define DFC_MAX_tWHR 15
#define DFC_MAX_tAR 15
#define DFC_CLOCK 104
/* DFC Clock is 104 MHz */
#define DFC_CLK_PER_US DFC_CLOCK/1000
/* clock period in ns */
#else
/* CONFIG_CPU_MONAHANS */
#define MEMC_BASE __REG(0x48000000)
/* Base of Memory Controller */
...
...
include/configs/delta.h
浏览文件 @
43638c67
...
...
@@ -170,14 +170,32 @@
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
#define CFG_MAX_NAND_DEVICE 1
/* Max number of NAND devices */
#define SECTORSIZE 512
/* #define NAND_NO_RB */
#define NAND_DELAY_US 25
/* mk@tbd: could be 0, I guess */
/* nand timeout values */
#define CFG_NAND_PROG_ERASE_TO 3000
#define CFG_NAND_OTHER_TO 100
#define CFG_NAND_SENDCMD_RETRY 3
#define NAND_ALLOW_ERASE_ALL 1
#undef NAND_ALLOW_ERASE_ALL
/* Allow erasing bad blocks - don't use */
/* NAND Timing Parameters (in ns) */
#define NAND_TIMING_tCH 10
#define NAND_TIMING_tCS 0
#define NAND_TIMING_tWH 20
#define NAND_TIMING_tWP 40
#define NAND_TIMING_tRH 20
#define NAND_TIMING_tRP 40
#define NAND_TIMING_tR 11123
/* #define NAND_TIMING_tWHR 110 */
#define NAND_TIMING_tWHR 100
#define NAND_TIMING_tAR 10
/* NAND debugging */
#define CFG_DFC_DEBUG1
/* usefull */
#undef CFG_DFC_DEBUG2
/* noisy */
#undef CFG_DFC_DEBUG3
/* extremly noisy */
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
...
...
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