fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)

Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size

Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data

Workaround:
The workaround is to switch to GPCM mode for NOR Flash access.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -86,6 +86,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 	puts("Work-around for Erratum DDR111 enabled\n");
 	puts("Work-around for Erratum DDR134 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+	puts("Work-around for Erratum IFC-A002769 enabled\n");
 #endif
 	return 0;
 }

arch/powerpc/include/asm/config_mpc85xx.h

@@ -112,6 +112,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -160,6 +161,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 
 /* P1015 is single core version of P1024 */
 #elif defined(CONFIG_P1015)

arch/powerpc/include/asm/fsl_ifc.h

@@ -951,5 +951,10 @@ struct fsl_ifc {
 	struct fsl_ifc_gpcm ifc_gpcm;
 };
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#undef CSPR_MSEL_NOR
+#define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
+#endif
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_PPC_FSL_IFC_H */